Remove MVT:i1 xor instruction before SELECT. (Performance improvement).

[aymanmus]

Summary

Fold the two following sequences:
Sequence 1 (xor with 0):
%cond1 = xor i1:%cond0 Constant<i1>0
%res = select %cond1, m, n
into:
%res = select %cond0, m, n

Sequence 2 (xor with 1):
%cond1 = xor i1:%cond0 Constant<i1>1
%res = select %cond1, m, n
into:
%res = select %cond0, n, m

[aymanmus]

ping

[hfinkel]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

5244

It seems like this will be generally profitable regardless of how many uses N0 has (because it will break the dependence on the xor result, plus handles the case where several selects depend on the same condition).

5245

Add space after if.

5247

C->isOne()

[delena]

Could you, please, add a test for AVX-512? MVT::i1 is legal there.

[aymanmus]

• Added a test for AVX512 where the improvement is significant.
• Removed the "one use" condition for the xor instruction.

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (N2->getOpcode() == ISD::SELECT && N2->hasOneUse()) {
         // Otherwise see if we can optimize to a better pattern.
         if (SDValue Combined = visitORLike(N0, N2_0, N))
           return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), Combined,
                              N1, N2_2);
       }
     }
   }
 
+  // select (xor Cond, 1), X, Y -> select Cond, Y, X
+  // select (xor Cond, 0), X, Y -> selext Cond, X, Y
+  if (VT0 == MVT::i1) {
+    if (N0->getOpcode() == ISD::XOR) {
+      if (auto *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) {
+        SDValue Cond0 = N0->getOperand(0);
+        if (C->isOne()) 
+          return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), 
+                             Cond0, N2, N1);
+        else
+          return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), 
+                             Cond0, N1, N2);
+      }
+    }
+  }
+
   // fold selects based on a setcc into other things, such as min/max/abs
   if (N0.getOpcode() == ISD::SETCC) {
     // select x, y (fcmp lt x, y) -> fminnum x, y
     // select x, y (fcmp gt x, y) -> fmaxnum x, y
     //
     // This is OK if we don't care about what happens if either operand is a
     // NaN.
     //

test/CodeGen/PowerPC/select-i1-vs-i1.ll

entry:
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
   ret <4 x float> %cond
 
 ; CHECK-LABEL: @testv4floateq
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
-; CHECK-DAG: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK-DAG: xxlor [[REG2:[0-9]+]], 35, 35
+; CHECK-DAG: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
-; CHECK: xxlor [[REG2]], 35, 35
+; CHECK: xxlor [[REG2]], 34, 34
 ; CHECK: .LBB[[BB]]:
 ; CHECK: xxlor 34, [[REG2]], [[REG2]]
 ; CHECK: blr
 }
 
 define <4 x float> @testv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4

 
 ; CHECK-LABEL: @testppc_fp128eq
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 6, 8
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 5, 7
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 2, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 3
 ; CHECK: crand [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: crand [[REG2:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: creqv [[REG3:[0-9]+]], [[REG2]], [[REG1]]
+; CHECK: crxor [[REG3:[0-9]+]], [[REG2]], [[REG1]]
 ; CHECK: bc 12, [[REG3]], .LBB[[BB1:[0-9_]+]]
-; CHECK: fmr 9, 11
+; CHECK: fmr 11, 9
 ; CHECK: .LBB[[BB1]]:
 ; CHECK: bc 12, [[REG3]], .LBB[[BB2:[0-9_]+]]
-; CHECK: fmr 10, 12
+; CHECK: fmr 12, 10
 ; CHECK: .LBB[[BB2]]:
-; CHECK-DAG: fmr 1, 9
-; CHECK-DAG: fmr 2, 10
+; CHECK-DAG: fmr 1, 11
+; CHECK-DAG: fmr 2, 12
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doubleslt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
entry:
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
   %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
   ret <2 x double> %cond
 
 ; CHECK-LABEL: @testv2doubleeq
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
-; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bclr 12, [[REG1]], 0
-; CHECK: vor 2, 3, 3
+; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB55:[0-9_]+]]
+; CHECK: vor 3, 2, 2
+; CHECK: .LBB[[BB55]]
+; CHECK: xxlor 34, 35, 35
 ; CHECK: blr
 }
 
 define <2 x double> @testv2doublesge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
 entry:
   %cmp1 = fcmp oeq float %c3, %c4
   %cmp3tmp = fcmp oeq float %c1, %c2
   %cmp3 = icmp sge i1 %cmp3tmp, %cmp1

test/CodeGen/X86/xor-select-i1-combine.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+;RUN: llc < %s -O2 -mattr=+avx512f -mtriple=x86_64-unknown | FileCheck %s --check-prefix=CHECK
+
+@n = common global i32 0, align 4
+@m = common global i32 0, align 4
+
+define i32 @main(i8 %small) {
+; CHECK-LABEL: main:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    movl $n, %eax
+; CHECK-NEXT:    movl $m, %ecx
+; CHECK-NEXT:    testb $1, %dil
+; CHECK-NEXT:    cmovneq %rax, %rcx
+; CHECK-NEXT:    movl (%rcx), %eax
+; CHECK-NEXT:    retq
+entry:
+  %0 = and i8 %small, 1
+  %cmp = icmp eq i8 %0, 0
+  %m.n = select i1 %cmp, i32* @m, i32* @n
+  %retval = load volatile i32, i32* %m.n, align 4
+  ret i32 %retval
+}
+
+
+define i32 @main2(i8 %small) {
+; CHECK-LABEL: main2:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    movl $m, %eax
+; CHECK-NEXT:    movl $n, %ecx
+; CHECK-NEXT:    testb $1, %dil
+; CHECK-NEXT:    cmovneq %rax, %rcx
+; CHECK-NEXT:    movl (%rcx), %eax
+; CHECK-NEXT:    retq
+entry:
+  %0 = and i8 %small, 1
+  %cmp = icmp eq i8 %0, 1
+  %m.n = select i1 %cmp, i32* @m, i32* @n
+  %retval = load volatile i32, i32* %m.n, align 4
+  ret i32 %retval
+}