Split RC::getSize into RC::getSpillSize and RC::getRegSize

[kparzysz]

Summary

The function getSize in MCRegisterClass and TargetRegisterClass actually refers to the size of the spill slot needed for registers from this class. This may or may not be equal to the actual size of the register, since the register's representation in memory may not be identical to the register itself.
Moreover, the comments in the MCRegisterInfo.h and TargetRegisterInfo.h explicitly state that the function getSize refers to both, the size of the register and the size of the spill slot.

This patch will provide two new member functions: getSpillSize and getRegSize in both MCRegisterClass and TargetRegisterClass, each returning only the value corresponding to the name. The existing function getSize will remain until all callers are updated to use one of the new functions.

[kparzysz]

This will be implemented in a different way.

include/llvm/MC/MCRegisterInfo.h

public:
   typedef const MCPhysReg* const_iterator;
 
   const iterator RegsBegin;
   const uint8_t *const RegSet;
   const uint32_t NameIdx;
   const uint16_t RegsSize;
   const uint16_t RegSetSize;
   const uint16_t ID;
-  const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes
+  const uint16_t SpillSize;   // Size (in bytes) of register spill slot.
+  const uint16_t Alignment;   // Alignment (bytes) of register spill slot.
+  const uint16_t RegSize;     // Register size (in bytes).
   const int8_t CopyCost;
   const bool Allocatable;
 
   /// getID() - Return the register class ID number.
   ///
   unsigned getID() const { return ID; }
 
   /// begin/end - Return all of the registers in this class.
bool contains(unsigned Reg) const {
     return (RegSet[Byte] & (1 << InByte)) != 0;
   }
 
   /// contains - Return true if both registers are in this class.
   bool contains(unsigned Reg1, unsigned Reg2) const {
     return contains(Reg1) && contains(Reg2);
   }
 
-  /// getSize - Return the size of the register in bytes, which is also the size
-  /// of a stack slot allocated to hold a spilled copy of this register.
-  unsigned getSize() const { return RegSize; }
+  /// Return the size of a stack slot allocated to hold a spilled copy of
+  /// this register.
+  unsigned getSpillSize() const { return SpillSize; }
+  /// Same as above, present temporarily until all users are updated.
+  unsigned getSize() const { return SpillSize; }
 
-  /// getAlignment - Return the minimum required alignment for a register of
-  /// this class.
+  /// Return the minimum required alignment for a register of this class.
   unsigned getAlignment() const { return Alignment; }
 
+  /// Return the size of the register in bytes.
+  unsigned getRegSize() const { return RegSize; }
+
   /// getCopyCost - Return the cost of copying a value between two registers in
   /// this class. A negative number means the register class is very expensive
   /// to copy e.g. status flag register classes.
   int getCopyCost() const { return CopyCost; }
 
   /// isAllocatable - Return true if this register class may be used to create
   /// virtual registers.
   bool isAllocatable() const { return Allocatable; }

include/llvm/Target/Target.td

class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
   // RegType - Specify the list ValueType of the registers in this register
   // class.  Note that all registers in a register class must have the same
   // ValueTypes.  This is a list because some targets permit storing different
   // types in same register, for example vector values with 128-bit total size,
   // but different count/size of items, like SSE on x86.
   //
   list<ValueType> RegTypes = regTypes;
 
-  // Size - Specify the spill size in bits of the registers.  A default value of
+  // Specify the spill size in bits of the registers.  A default value of
   // zero lets tablgen pick an appropriate size.
-  int Size = 0;
+  int SpillSize = 0;
 
   // Alignment - Specify the alignment required of the registers when they are
   // stored or loaded to memory.
   //
   int Alignment = alignment;
 
+  // Specify the register size in bits.  A default value of zero will set it
+  // to the same value as SpillSize.
+  int RegSize = 0;
+
   // CopyCost - This value is used to specify the cost of copying a value
   // between two registers in this register class. The default value is one
   // meaning it takes a single instruction to perform the copying. A negative
   // value means copying is extremely expensive or impossible.
   int CopyCost = 1;
 
   // MemberList - Specify which registers are in this class.  If the
   // allocation_order_* method are not specified, this also defines the order of

include/llvm/Target/TargetRegisterInfo.h

bool contains(unsigned Reg) const {
     return MC->contains(Reg);
   }
 
   /// Return true if both registers are in this class.
   bool contains(unsigned Reg1, unsigned Reg2) const {
     return MC->contains(Reg1, Reg2);
   }
 
-  /// Return the size of the register in bytes, which is also the size
-  /// of a stack slot allocated to hold a spilled copy of this register.
+  /// Return the size of a stack slot allocated to hold a spilled copy of
+  /// this register.
+  unsigned getSpillSize() const { return MC->getSpillSize(); }
+  /// Same as above, present temporarily until all users are updated.
   unsigned getSize() const { return MC->getSize(); }
 
   /// Return the minimum required alignment for a register of this class.
   unsigned getAlignment() const { return MC->getAlignment(); }
 
+  /// Return the size of the register in bytes.
+  unsigned getRegSize() const { return MC->getRegSize(); }
+
   /// Return the cost of copying a value between two registers in this class.
   /// A negative number means the register class is very expensive
   /// to copy e.g. status flag register classes.
   int getCopyCost() const { return MC->getCopyCost(); }
 
   /// Return true if this register class may be used to create virtual
   /// registers.
   bool isAllocatable() const { return MC->isAllocatable(); }

lib/Target/AArch64/AArch64RegisterInfo.td

 def Q27   : AArch64Reg<27, "q27", [D27], ["v27", ""]>, DwarfRegAlias<B27>;
 def Q28   : AArch64Reg<28, "q28", [D28], ["v28", ""]>, DwarfRegAlias<B28>;
 def Q29   : AArch64Reg<29, "q29", [D29], ["v29", ""]>, DwarfRegAlias<B29>;
 def Q30   : AArch64Reg<30, "q30", [D30], ["v30", ""]>, DwarfRegAlias<B30>;
 def Q31   : AArch64Reg<31, "q31", [D31], ["v31", ""]>, DwarfRegAlias<B31>;
 }
 
 def FPR8  : RegisterClass<"AArch64", [untyped], 8, (sequence "B%u", 0, 31)> {
-  let Size = 8;
+  let SpillSize = 8;
 }
 def FPR16 : RegisterClass<"AArch64", [f16], 16, (sequence "H%u", 0, 31)> {
-  let Size = 16;
+  let SpillSize = 16;
 }
 def FPR32 : RegisterClass<"AArch64", [f32, i32], 32,(sequence "S%u", 0, 31)>;
 def FPR64 : RegisterClass<"AArch64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32,
                                     v1i64, v4f16],
                                     64, (sequence "D%u", 0, 31)>;
 // We don't (yet) have an f128 legal type, so don't use that here. We
 // normalize 128-bit vectors to v2f64 for arg passing and such, so use
 // that here.

 def DSeqPairs : RegisterTuples<[dsub0, dsub1], [(rotl FPR64, 0), (rotl FPR64, 1)]>;
 def DSeqTriples : RegisterTuples<[dsub0, dsub1, dsub2],
                                  [(rotl FPR64, 0), (rotl FPR64, 1),
                                   (rotl FPR64, 2)]>;
 def DSeqQuads : RegisterTuples<[dsub0, dsub1, dsub2, dsub3],
                                [(rotl FPR64, 0), (rotl FPR64, 1),
                                 (rotl FPR64, 2), (rotl FPR64, 3)]>;
 def DD   : RegisterClass<"AArch64", [untyped], 64, (add DSeqPairs)> {
-  let Size = 128;
+  let SpillSize = 128;
 }
 def DDD  : RegisterClass<"AArch64", [untyped], 64, (add DSeqTriples)> {
-  let Size = 196;
+  let SpillSize = 196;
 }
 def DDDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqQuads)> {
-  let Size = 256;
+  let SpillSize = 256;
 }
 
 // Pairs, triples, and quads of 128-bit vector registers.
 def QSeqPairs : RegisterTuples<[qsub0, qsub1], [(rotl FPR128, 0), (rotl FPR128, 1)]>;
 def QSeqTriples : RegisterTuples<[qsub0, qsub1, qsub2],
                                  [(rotl FPR128, 0), (rotl FPR128, 1),
                                   (rotl FPR128, 2)]>;
 def QSeqQuads : RegisterTuples<[qsub0, qsub1, qsub2, qsub3],
                                [(rotl FPR128, 0), (rotl FPR128, 1),
                                 (rotl FPR128, 2), (rotl FPR128, 3)]>;
 def QQ   : RegisterClass<"AArch64", [untyped], 128, (add QSeqPairs)> {
-  let Size = 256;
+  let SpillSize = 256;
 }
 def QQQ  : RegisterClass<"AArch64", [untyped], 128, (add QSeqTriples)> {
-  let Size = 384;
+  let SpillSize = 384;
 }
 def QQQQ : RegisterClass<"AArch64", [untyped], 128, (add QSeqQuads)> {
-  let Size = 512;
+  let SpillSize = 512;
 }
 
 
 // Vector operand versions of the FP registers. Alternate name printing and
 // assmebler matching.
 def VectorReg64AsmOperand : AsmOperandClass {
   let Name = "VectorReg64";
   let PredicateMethod = "isVectorReg";

 
 def WSeqPairs : RegisterTuples<[sube32, subo32], 
                                [(rotl GPR32, 0), (rotl GPR32, 1)]>;
 def XSeqPairs : RegisterTuples<[sube64, subo64], 
                                [(rotl GPR64, 0), (rotl GPR64, 1)]>;
 
 def WSeqPairsClass   : RegisterClass<"AArch64", [untyped], 32, 
                                      (add WSeqPairs)>{
-  let Size = 64;
+  let SpillSize = 64;
 }
 def XSeqPairsClass   : RegisterClass<"AArch64", [untyped], 64, 
                                      (add XSeqPairs)>{
-  let Size = 128;
+  let SpillSize = 128;
 }
 
 
 let RenderMethod = "addRegOperands", ParserMethod="tryParseGPRSeqPair" in {
   def WSeqPairsAsmOperandClass : AsmOperandClass { let Name = "WSeqPair"; }
   def XSeqPairsAsmOperandClass : AsmOperandClass { let Name = "XSeqPair"; }
 }
 

lib/Target/AMDGPU/SIRegisterInfo.td

 // Register class for all vector registers (VGPRs + Interploation Registers)
 def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32], 32, (add VGPR_64)> {
   // Requires 2 v_mov_b32 to copy
   let CopyCost = 2;
   let AllocationPriority = 2;
 }
 
 def VReg_96 : RegisterClass<"AMDGPU", [untyped], 32, (add VGPR_96)> {
-  let Size = 96;
+  let SpillSize = 96;
 
   // Requires 3 v_mov_b32 to copy
   let CopyCost = 3;
   let AllocationPriority = 3;
 }
 
 def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32, (add VGPR_128)> {
   // Requires 4 v_mov_b32 to copy
   let CopyCost = 4;
   let AllocationPriority = 4;
 }
 
 def VReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add VGPR_256)> {
   let CopyCost = 8;
   let AllocationPriority = 5;
 }
 
 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, (add VGPR_512)> {
   let CopyCost = 16;
   let AllocationPriority = 6;
 }
 
 def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
-  let Size = 32;
+  let SpillSize = 32;
 }
 
 def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VGPR_32, SReg_32)>;
 
 def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64)> {
   let CopyCost = 2;
 }
 

lib/Target/ARM/ARMRegisterInfo.td

 // Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP.
 // These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs.
 def Tuples2R : RegisterTuples<[gsub_0, gsub_1],
                               [(add R0, R2, R4, R6, R8, R10, R12),
                                (add R1, R3, R5, R7, R9, R11, SP)]>;
 
 // Register class representing a pair of even-odd GPRs.
 def GPRPair : RegisterClass<"ARM", [untyped], 64, (add Tuples2R)> {
-  let Size = 64; // 2 x 32 bits, we have no predefined type of that size.
+  let SpillSize = 64; // 2 x 32 bits, we have no predefined type of that size.
 }
 
 // Pseudo-registers representing 3 consecutive D registers.
 def Tuples3D : RegisterTuples<[dsub_0, dsub_1, dsub_2],
                               [(shl DPR, 0),
                                (shl DPR, 1),
                                (shl DPR, 2)]>;
 
 // 3 consecutive D registers.
 def DTriple : RegisterClass<"ARM", [untyped], 64, (add Tuples3D)> {
-  let Size = 192; // 3 x 64 bits, we have no predefined type of that size.
+  let SpillSize = 192; // 3 x 64 bits, we have no predefined type of that size.
 }
 
 // Pseudo 256-bit registers to represent pairs of Q registers. These should
 // never be present in the emitted code.
 // These are used for NEON load / store instructions, e.g., vld4, vst3.
 def Tuples2Q : RegisterTuples<[qsub_0, qsub_1], [(shl QPR, 0), (shl QPR, 1)]>;
 
 // Pseudo 256-bit vector register class to model pairs of Q registers

 
 def Tuples3DSpc : RegisterTuples<[dsub_0, dsub_2, dsub_4],
                                  [(shl DPR, 0),
                                   (shl DPR, 2),
                                   (shl DPR, 4)]>;
 
 // Spaced triples of D registers.
 def DTripleSpc : RegisterClass<"ARM", [untyped], 64, (add Tuples3DSpc)> {
-  let Size = 192; // 3 x 64 bits, we have no predefined type of that size.
+  let SpillSize = 192; // 3 x 64 bits, we have no predefined type of that size.
 }
 
 def Tuples4DSpc : RegisterTuples<[dsub_0, dsub_2, dsub_4, dsub_6],
                                  [(shl DPR, 0),
                                   (shl DPR, 2),
                                   (shl DPR, 4),
                                   (shl DPR, 6)]>;
 
 // Spaced quads of D registers.
 def DQuadSpc : RegisterClass<"ARM", [v4i64], 64, (add Tuples3DSpc)>;

lib/Target/Hexagon/HexagonRegisterInfo.td

def VecDblRegs128B : RegisterClass<"Hexagon",
                                (add (sequence "W%u", 0, 15))>;
 
 def VecPredRegs : RegisterClass<"Hexagon", [v512i1], 512,
                                 (add (sequence "Q%u", 0, 3))>;
 
 def VecPredRegs128B : RegisterClass<"Hexagon", [v1024i1], 1024,
                                    (add (sequence "Q%u", 0, 3))>;
 
+let SpillSize = 32 in
 def PredRegs : RegisterClass<"Hexagon", 
                              [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32,
-                             (add (sequence "P%u", 0, 3))>
-{
-  let Size = 32;
-}
+                             (add (sequence "P%u", 0, 3))>;
 
-let Size = 32 in
+let SpillSize = 32 in
 def ModRegs : RegisterClass<"Hexagon", [i32], 32, (add M0, M1)>;
 
-let Size = 32, isAllocatable = 0 in
+let SpillSize = 32, isAllocatable = 0 in
 def CtrRegs : RegisterClass<"Hexagon", [i32], 32,
                            (add LC0, SA0, LC1, SA1,
                                 P3_0,
                                  M0, M1, C6, C7, CS0, CS1, UPCL, UPCH,
                                  USR, USR_OVF, UGP, GP, PC)>;
 
-let Size = 64, isAllocatable = 0 in
+let SpillSize = 64, isAllocatable = 0 in
 def CtrRegs64 : RegisterClass<"Hexagon", [i64], 64,
                               (add C1_0, C3_2, C7_6, C9_8, C11_10, CS, UPC)>;
 
 def VolatileV3 {
   list<Register> Regs = [D0, D1, D2, D3, D4, D5, D6, D7,
                          R28, R31,
                          P0, P1, P2, P3,
                          M0, M1,

lib/Target/Mips/MipsRegisterInfo.td

 def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>;
 
 // Hardware registers
 def HWRegs : RegisterClass<"Mips", [i32], 32, (sequence "HWR%u", 0, 31)>,
              Unallocatable;
 
 // Accumulator Registers
 def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
-  let Size = 64;
+  let SpillSize = 64;
 }
 
 def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> {
-  let Size = 128;
+  let SpillSize = 128;
 }
 
 def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
-  let Size = 64;
+  let SpillSize = 64;
 }
 
 def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
 
 // Coprocessor 0 registers.
 def COP0 : RegisterClass<"Mips", [i32], 32, (sequence "COP0%u", 0, 31)>,
            Unallocatable;
 

lib/Target/PowerPC/PPCRegisterInfo.td

 
 // For QPX
 def QFRC : RegisterClass<"PPC", [v4f64], 256, (add (sequence "QF%u", 0, 13),
                                                 (sequence "QF%u", 31, 14))>;
 def QSRC : RegisterClass<"PPC", [v4f32], 128, (add QFRC)>;
 def QBRC : RegisterClass<"PPC", [v4i1], 256, (add QFRC)> {
   // These are actually stored as floating-point values where a positive
   // number is true and anything else (including NaN) is false.
-  let Size = 256;
+  let SpillSize = 256;
 }
 
 def CRBITRC : RegisterClass<"PPC", [i1], 32,
   (add CR2LT, CR2GT, CR2EQ, CR2UN,
        CR3LT, CR3GT, CR3EQ, CR3UN,
        CR4LT, CR4GT, CR4EQ, CR4UN,
        CR5LT, CR5GT, CR5EQ, CR5UN,
        CR6LT, CR6GT, CR6EQ, CR6UN,
        CR7LT, CR7GT, CR7EQ, CR7UN,
        CR1LT, CR1GT, CR1EQ, CR1UN,
        CR0LT, CR0GT, CR0EQ, CR0UN)> {
-  let Size = 32;
+  let SpillSize = 32;
 }
 
 def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6,
                                                 CR7, CR2, CR3, CR4)>;
 
 def CRRC0 : RegisterClass<"PPC", [i32], 32, (add CR0)>;
 
 // The CTR registers are not allocatable because they're used by the

lib/Target/SystemZ/SystemZRegisterInfo.td

 def subreg_hh32  : ComposedSubRegIndex<subreg_h64, subreg_h32>;
 def subreg_hl32  : ComposedSubRegIndex<subreg_h64, subreg_l32>;
 def subreg_hr32  : ComposedSubRegIndex<subreg_h64, subreg_r32>;
 }
 
 // Define a register class that contains values of types TYPES and an
 // associated operand called NAME.  SIZE is the size and alignment
 // of the registers and REGLIST is the list of individual registers.
-multiclass SystemZRegClass<string name, list<ValueType> types, int size,
+multiclass SystemZRegClass<string name, list<ValueType> types, int spillSize,
                            dag regList> {
   def AsmOperand : AsmOperandClass {
     let Name = name;
     let ParserMethod = "parse"##name;
     let RenderMethod = "addRegOperands";
   }
-  def Bit : RegisterClass<"SystemZ", types, size, regList> {
-    let Size = size;
+  def Bit : RegisterClass<"SystemZ", types, spillSize, regList> {
+    let SpillSize = spillSize;
   }
   def "" : RegisterOperand<!cast<RegisterClass>(name##"Bit")> {
     let ParserMatchClass = !cast<AsmOperandClass>(name##"AsmOperand");
   }
 }
 
 //===----------------------------------------------------------------------===//
 // General-purpose registers

lib/Target/X86/X86RegisterInfo.td

 
 // Extended VR128 and VR256 for AVX-512 instructions
 def VR128X : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64],
                            128, (add FR32X)>;
 def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
                            256, (sequence "YMM%u", 0, 31)>;
 
 // Mask registers
-def VK1     : RegisterClass<"X86", [i1],    16,  (sequence "K%u", 0, 7)> {let Size = 16;}
-def VK2     : RegisterClass<"X86", [v2i1],  16,  (add VK1)> {let Size = 16;}
-def VK4     : RegisterClass<"X86", [v4i1],  16,  (add VK2)> {let Size = 16;}
-def VK8     : RegisterClass<"X86", [v8i1],  16,  (add VK4)> {let Size = 16;}
-def VK16    : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;}
-def VK32    : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;}
-def VK64    : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;}
-
-def VK1WM   : RegisterClass<"X86", [i1],    16,  (sub VK1, K0)> {let Size = 16;}
-def VK2WM   : RegisterClass<"X86", [v2i1],  16,  (sub VK2, K0)> {let Size = 16;}
-def VK4WM   : RegisterClass<"X86", [v4i1],  16,  (sub VK4, K0)> {let Size = 16;}
-def VK8WM   : RegisterClass<"X86", [v8i1],  16,  (sub VK8, K0)> {let Size = 16;}
-def VK16WM  : RegisterClass<"X86", [v16i1], 16, (add VK8WM)>   {let Size = 16;}
-def VK32WM  : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;}
-def VK64WM  : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;}
+def VK1     : RegisterClass<"X86", [i1],    16,  (sequence "K%u", 0, 7)> {let SpillSize = 16;}
+def VK2     : RegisterClass<"X86", [v2i1],  16,  (add VK1)> {let SpillSize = 16;}
+def VK4     : RegisterClass<"X86", [v4i1],  16,  (add VK2)> {let SpillSize = 16;}
+def VK8     : RegisterClass<"X86", [v8i1],  16,  (add VK4)> {let SpillSize = 16;}
+def VK16    : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let SpillSize = 16;}
+def VK32    : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let SpillSize = 32;}
+def VK64    : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let SpillSize = 64;}
+
+def VK1WM   : RegisterClass<"X86", [i1],    16,  (sub VK1, K0)> {let SpillSize = 16;}
+def VK2WM   : RegisterClass<"X86", [v2i1],  16,  (sub VK2, K0)> {let SpillSize = 16;}
+def VK4WM   : RegisterClass<"X86", [v4i1],  16,  (sub VK4, K0)> {let SpillSize = 16;}
+def VK8WM   : RegisterClass<"X86", [v8i1],  16,  (sub VK8, K0)> {let SpillSize = 16;}
+def VK16WM  : RegisterClass<"X86", [v16i1], 16, (add VK8WM)>   {let SpillSize = 16;}
+def VK32WM  : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let SpillSize = 32;}
+def VK64WM  : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let SpillSize = 64;}
 
 // Bound registers
 def BNDR : RegisterClass<"X86", [v2i64], 128, (sequence "BND%u", 0, 3)>;

utils/TableGen/CodeGenRegisters.h

class CodeGenRegisterClass {
     BitVector TopoSigs;
 
   public:
     unsigned EnumValue;
     std::string Namespace;
     SmallVector<MVT::SimpleValueType, 4> VTs;
     unsigned SpillSize;
     unsigned SpillAlignment;
+    // The member RegSize does not participate in the calculation of the RC
+    // properties and relations. It only serves to provide register size to
+    // MCRegisterClass.
+    unsigned RegSize;
     int CopyCost;
     bool Allocatable;
     std::string AltOrderSelect;
     uint8_t AllocationPriority;
     /// Contains the combination of the lane masks of all subregisters.
     unsigned LaneMask;
     /// True if there are at least 2 subregisters which do not interfere.
     bool HasDisjunctSubRegs;
public:
 
     // A key representing the parts of a register class used for forming
     // sub-classes.  Note the ordering provided by this key is not the same as
     // the topological order used for the EnumValues.
     struct Key {
       const CodeGenRegister::Vec *Members;
       unsigned SpillSize;
       unsigned SpillAlignment;
+      unsigned RegSize;
 
-      Key(const CodeGenRegister::Vec *M, unsigned S = 0, unsigned A = 0)
-        : Members(M), SpillSize(S), SpillAlignment(A) {}
+      Key(const CodeGenRegister::Vec *M, unsigned S = 0, unsigned A = 0,
+          unsigned R = 0)
+        : Members(M), SpillSize(S), SpillAlignment(A), RegSize(R) {}
 
       Key(const CodeGenRegisterClass &RC)
         : Members(&RC.getMembers()),
           SpillSize(RC.SpillSize),
-          SpillAlignment(RC.SpillAlignment) {}
+          SpillAlignment(RC.SpillAlignment),
+          RegSize(RC.RegSize) {}
 
       // Lexicographical order of (Members, SpillSize, SpillAlignment).
       bool operator<(const Key&) const;
     };
 
     // Create a non-user defined register class.
     CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props);
 

utils/TableGen/CodeGenRegisters.cpp

while (!Order.empty()) {
       Order.pop_back();
       if (!contains(Reg))
         PrintFatalError(R->getLoc(), " AltOrder register " + Reg->getName() +
                       " is not a class member");
     }
   }
 
   // Allow targets to override the size in bits of the RegisterClass.
-  unsigned Size = R->getValueAsInt("Size");
+  unsigned SSize = R->getValueAsInt("SpillSize");
+  unsigned RSize = R->getValueAsInt("RegSize");
 
   Namespace = R->getValueAsString("Namespace");
-  SpillSize = Size ? Size : MVT(VTs[0]).getSizeInBits();
+  SpillSize = SSize ? SSize : MVT(VTs[0]).getSizeInBits();
   SpillAlignment = R->getValueAsInt("Alignment");
+  RegSize = RSize ? RSize : SpillSize;
   CopyCost = R->getValueAsInt("CopyCost");
   Allocatable = R->getValueAsBit("isAllocatable");
   AltOrderSelect = R->getValueAsString("AltOrderSelect");
   int AllocationPriority = R->getValueAsInt("AllocationPriority");
   if (AllocationPriority < 0 || AllocationPriority > 63)
     PrintFatalError(R->getLoc(), "AllocationPriority out of range [0,63]");
   this->AllocationPriority = AllocationPriority;
 }
 
 // Create an inferred register class that was missing from the .td files.
 // Most properties will be inherited from the closest super-class after the
 // class structure has been computed.
 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
                                            StringRef Name, Key Props)
   : Members(*Props.Members),
     TheDef(nullptr),
     Name(Name),
     TopoSigs(RegBank.getNumTopoSigs()),
     EnumValue(-1),
     SpillSize(Props.SpillSize),
     SpillAlignment(Props.SpillAlignment),
+    RegSize(Props.RegSize),
     CopyCost(0),
     Allocatable(true),
     AllocationPriority(0) {
   for (const auto R : Members)
     TopoSigs.set(R->getTopoSig());
 }
 
 // Compute inherited propertied for a synthesized register class.

 
 bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
   return std::binary_search(Members.begin(), Members.end(), Reg,
                             deref<llvm::less>());
 }
 
 namespace llvm {
   raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) {
-    OS << "{ S=" << K.SpillSize << ", A=" << K.SpillAlignment;
+    OS << "{ S=" << K.SpillSize << ", A=" << K.SpillAlignment
+       << ", R=" << K.RegSize;
     for (const auto R : *K.Members)
       OS << ", " << R->getName();
     return OS << " }";
   }
 }
 
 // This is a simple lexicographical order that can be used to search for sets.
 // It is not the same as the topological order provided by TopoOrderRC.
 bool CodeGenRegisterClass::Key::
 operator<(const CodeGenRegisterClass::Key &B) const {
   assert(Members && B.Members);
-  return std::tie(*Members, SpillSize, SpillAlignment) <
-         std::tie(*B.Members, B.SpillSize, B.SpillAlignment);
+  return std::tie(*Members, SpillSize, SpillAlignment, RegSize) <
+         std::tie(*B.Members, B.SpillSize, B.SpillAlignment, B.RegSize);
 }
 
 // Returns true if RC is a strict subclass.
 // RC is a sub-class of this class if it is a valid replacement for any
 // instruction operand where a register of this classis required. It must
 // satisfy these conditions:
 //
 // 1. All RC registers are also in this.
 // 2. The RC spill size must not be smaller than our spill size.
 // 3. RC spill alignment must be compatible with ours.
 //
 static bool testSubClass(const CodeGenRegisterClass *A,
                          const CodeGenRegisterClass *B) {
+  // Ignore RegSize.
   return A->SpillAlignment && B->SpillAlignment % A->SpillAlignment == 0 &&
          A->SpillSize <= B->SpillSize &&
          std::includes(A->getMembers().begin(), A->getMembers().end(),
                        B->getMembers().begin(), B->getMembers().end(),
                        deref<llvm::less>());
 }
 
 /// Sorting predicate for register classes.  This provides a topological
if (A->SpillSize > B->SpillSize)
     return false;
 
   // Order by ascending spill alignment.
   if (A->SpillAlignment < B->SpillAlignment)
     return true;
   if (A->SpillAlignment > B->SpillAlignment)
     return false;
 
+  // Ignore RegSize.
+
   // Order by descending set size.  Note that the classes' allocation order may
   // not have been computed yet.  The Members set is always vaild.
   if (A->getMembers().size() > B->getMembers().size())
     return true;
   if (A->getMembers().size() < B->getMembers().size())
     return false;
 
   // Finally order by name as a tie breaker.

 }
 
 // Create a synthetic sub-class if it is missing.
 CodeGenRegisterClass*
 CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC,
                                     const CodeGenRegister::Vec *Members,
                                     StringRef Name) {
   // Synthetic sub-class has the same size and alignment as RC.
-  CodeGenRegisterClass::Key K(Members, RC->SpillSize, RC->SpillAlignment);
+  CodeGenRegisterClass::Key K(Members, RC->SpillSize, RC->SpillAlignment,
+                              RC->RegSize);
   RCKeyMap::const_iterator FoundI = Key2RC.find(K);
   if (FoundI != Key2RC.end())
     return FoundI->second;
 
   // Sub-class doesn't exist, create a new one.
   RegClasses.emplace_back(*this, Name, K);
   addToMaps(&RegClasses.back());
   return &RegClasses.back();

utils/TableGen/RegisterInfoEmitter.cpp

#endif
   OS << "extern const MCRegisterClass " << TargetName
      << "MCRegisterClasses[] = {\n";
 
   for (const auto &RC : RegisterClasses) {
     // Asserts to make sure values will fit in table assuming types from
     // MCRegisterInfo.h
     assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
     assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
+    assert((RC.RegSize/8) <= 0xffff && "RegSize too large.");
     assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
 
     OS << "  { " << RC.getName() << ", " << RC.getName() << "Bits, "
        << RegClassStrings.get(RC.getName()) << ", "
        << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
        << RC.getQualifiedName() + "RegClassID" << ", "
        << RC.SpillSize/8 << ", "
        << RC.SpillAlignment/8 << ", "
+       << RC.RegSize/8 << ", "
        << RC.CopyCost << ", "
        << ( RC.Allocatable ? "true" : "false" ) << " },\n";
   }
 
   OS << "};\n\n";
 
   EmitRegMappingTables(OS, Regs, false);