This is an archive of the discontinued LLVM Phabricator instance.

Differential D23118

[mips] Fix c.<cc>.<fmt> instruction definition.
ClosedPublic

Authored by sdardis on Aug 3 2016, 5:22 AM.

Details

Reviewers
dsanders
vkalintiris
zoran.jovanovic
Summary

As part of this effort, remove MipsFCmp nodes and use tablegen
patterns rather than custom lowering through C++.

Unexpectedly, this improves codesize for microMIPS as previous floating
point setcc expansions would materialize 0 and 1 into GPRs before using
the relevant mov[tf].[sd] instruction. Now $zero is used directly.

Diff Detail

Event Timeline

sdardis updated this revision to Diff 66645.Aug 3 2016, 5:22 AM
sdardis retitled this revision from to [mips] Fix c.<cc>.<fmt> instruction definition..
sdardis updated this object.
sdardis added reviewers: dsanders, vkalintiris.
sdardis set the repository for this revision to rL LLVM.
sdardis added a subscriber: llvm-commits.
Herald added subscribers: sdardis, dsanders. · View Herald TranscriptAug 3 2016, 5:22 AM
sdardis added a comment.Aug 11 2016, 3:28 AM

Ping.

sdardis added a reviewer: zoran.jovanovic.Aug 26 2016, 5:57 AM

Zoran, can you take a look at this? Thanks.

sdardis added a comment.Sep 6 2016, 5:28 AM

Ping.

zoran.jovanovic accepted this revision.Sep 7 2016, 7:33 AM
zoran.jovanovic edited edge metadata.

LGTM.

lib/Target/Mips/MicroMipsInstrFPU.td
168

Nit: I do believe that MMRel is not necessary here. It seems that instruction mapping is not used in this case.

211

Nit: Line exceeds 80 characters.

lib/Target/Mips/MipsCondMov.td
337

Nit: Line exceeds 80 characters.

lib/Target/Mips/MipsFastISel.cpp
712

Nit: Line exceeds 80 characters.

This revision is now accepted and ready to land.Sep 7 2016, 7:33 AM
sdardis closed this revision.Sep 9 2016, 2:42 AM

Thanks, committed rL281022.

Revision Contents

PathSize
lib/
Target/
Mips/
InstPrinter/
1 line
6 lines
77 lines
17 lines
2 lines
7 lines
217 lines
3 lines
3 lines
142 lines
219 lines
3 lines
3 lines
9 lines
34 lines
test/
CodeGen/
Mips/
140 lines
2 lines
MC/
Mips/
mips32/
44 lines
36 lines
mips32r2/
28 lines
36 lines
mips32r3/
28 lines
36 lines
mips32r5/
28 lines
36 lines
mips4/
44 lines
36 lines
mips5/
28 lines
36 lines
mips64/
28 lines
36 lines
mips64r2/
28 lines
36 lines
mips64r3/
28 lines
36 lines
mips64r5/
28 lines
36 lines

Diff 66645

lib/Target/Mips/InstPrinter/MipsInstPrinter.h

Show First 20 Lines • Show All 91 Lines • ▼ Show 20 Lines void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
unsigned PrintMethodIdx, raw_ostream &O); unsigned PrintMethodIdx, raw_ostream &O);
private: private:
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
template <unsigned Bits, unsigned Offset = 0> template <unsigned Bits, unsigned Offset = 0>
void printUImm(const MCInst *MI, int opNum, raw_ostream &O); void printUImm(const MCInst *MI, int opNum, raw_ostream &O);
void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O); void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O);
void printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O); void printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O);
void printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O);
void printRegisterPair(const MCInst *MI, int opNum, raw_ostream &O); void printRegisterPair(const MCInst *MI, int opNum, raw_ostream &O);
void printSHFMask(const MCInst *MI, int opNum, raw_ostream &O); void printSHFMask(const MCInst *MI, int opNum, raw_ostream &O);
bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo, bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo,
raw_ostream &OS); raw_ostream &OS);
bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo0, bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo0,
unsigned OpNo1, raw_ostream &OS); unsigned OpNo1, raw_ostream &OS);
bool printAlias(const MCInst &MI, raw_ostream &OS); bool printAlias(const MCInst &MI, raw_ostream &OS);
void printSaveRestore(const MCInst *MI, raw_ostream &O); void printSaveRestore(const MCInst *MI, raw_ostream &O);
void printRegisterList(const MCInst *MI, int opNum, raw_ostream &O); void printRegisterList(const MCInst *MI, int opNum, raw_ostream &O);
}; };
} // end namespace llvm } // end namespace llvm
#endif #endif

lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp

Show First 20 Lines • Show All 186 Lines • ▼ Show 20 LinesprintMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) {
// print the same way as all normal 3 operand instructions. // print the same way as all normal 3 operand instructions.
printOperand(MI, opNum, O); printOperand(MI, opNum, O);
O << ", "; O << ", ";
printOperand(MI, opNum+1, O); printOperand(MI, opNum+1, O);
return; return;
} }
void MipsInstPrinter:: void MipsInstPrinter::
printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) {
const MCOperand& MO = MI->getOperand(opNum);
O << MipsFCCToString((Mips::CondCode)MO.getImm());
}
void MipsInstPrinter::
printRegisterPair(const MCInst *MI, int opNum, raw_ostream &O) { printRegisterPair(const MCInst *MI, int opNum, raw_ostream &O) {
printRegName(O, MI->getOperand(opNum).getReg()); printRegName(O, MI->getOperand(opNum).getReg());
} }
void MipsInstPrinter:: void MipsInstPrinter::
printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) { printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) {
llvm_unreachable("TODO"); llvm_unreachable("TODO");
} }
▲ Show 20 Lines • Show All 86 Lines • Show Last 20 Lines

lib/Target/Mips/MicroMipsInstrFPU.td

Show All 20 Linesdef LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>,
LWXC1_FM_MM<0x48>, INSN_MIPS4_32R2_NOT_32R6_64R6; LWXC1_FM_MM<0x48>, INSN_MIPS4_32R2_NOT_32R6_64R6;
def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>,
SWXC1_FM_MM<0x88>, INSN_MIPS4_32R2_NOT_32R6_64R6; SWXC1_FM_MM<0x88>, INSN_MIPS4_32R2_NOT_32R6_64R6;
def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>,
LWXC1_FM_MM<0x148>, INSN_MIPS5_32R2_NOT_32R6_64R6; LWXC1_FM_MM<0x148>, INSN_MIPS5_32R2_NOT_32R6_64R6;
def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>,
SWXC1_FM_MM<0x188>, INSN_MIPS5_32R2_NOT_32R6_64R6; SWXC1_FM_MM<0x188>, INSN_MIPS5_32R2_NOT_32R6_64R6;
def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>,
CEQS_FM_MM<0>;
def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>,
CEQS_FM_MM<1>;
def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>, def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>,
BC1F_FM_MM<0x1c>, ISA_MIPS1_NOT_32R6_64R6; BC1F_FM_MM<0x1c>, ISA_MIPS1_NOT_32R6_64R6;
def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>, def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>,
BC1F_FM_MM<0x1d>, ISA_MIPS1_NOT_32R6_64R6; BC1F_FM_MM<0x1d>, ISA_MIPS1_NOT_32R6_64R6;
def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
ROUND_W_FM_MM<0, 0x24>; ROUND_W_FM_MM<0, 0x24>;
def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>, def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
ROUND_W_FM_MM<0, 0xec>; ROUND_W_FM_MM<0, 0xec>;
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
let AdditionalPredicates = [InMicroMips] in { let AdditionalPredicates = [InMicroMips] in {
// Patterns for loads/stores with a reg+imm operand. // Patterns for loads/stores with a reg+imm operand.
let AddedComplexity = 40 in { let AddedComplexity = 40 in {
def : LoadRegImmPat<LDC1_MM, f64, load>, FGR_32; def : LoadRegImmPat<LDC1_MM, f64, load>, FGR_32;
def : StoreRegImmPat<SDC1_MM, f64>, FGR_32; def : StoreRegImmPat<SDC1_MM, f64>, FGR_32;
def : LoadRegImmPat<LWC1_MM, f32, load>; def : LoadRegImmPat<LWC1_MM, f32, load>;
def : StoreRegImmPat<SWC1_MM, f32>; def : StoreRegImmPat<SWC1_MM, f32>;
} }
// Floating point comparisons
multiclass C_COND_M_MM<string TypeStr, RegisterOperand RC, bits<2> fmt,
InstrItinClass itin> {
def C_F_#NAME : MMRel, C_COND_FT<"f", TypeStr, RC, itin>,
zoran.jovanovicUnsubmitted
Not Done
ReplyInline Actions

Nit: I do believe that MMRel is not necessary here. It seems that instruction mapping is not used in this case.

zoran.jovanovic: Nit: I do believe that MMRel is not necessary here. It seems that instruction mapping is not…
C_COND_FM_MM<fmt, 0>;
def C_UN_#NAME : MMRel, C_COND_FT<"un", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 1>;
def C_EQ_#NAME : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 2>;
def C_UEQ_#NAME : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 3>;
def C_OLT_#NAME : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 4>;
def C_ULT_#NAME : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 5>;
def C_OLE_#NAME : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 6>;
def C_ULE_#NAME : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 7>;
def C_SF_#NAME : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 8>;
def C_NGLE_#NAME : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 9>;
def C_SEQ_#NAME : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 10>;
def C_NGL_#NAME : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 11>;
def C_LT_#NAME : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 12>;
def C_NGE_#NAME : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 13>;
def C_LE_#NAME : MMRel, C_COND_FT<"le", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 14>;
def C_NGT_#NAME : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>,
C_COND_FM_MM<fmt, 15>;
}
defm S_MM : C_COND_M_MM<"s", FGR32Opnd, 0b00, II_C_CC_S>;
defm D32_MM : C_COND_M_MM<"d", AFGR64Opnd, 0b01, II_C_CC_D>, FGR_32;
// Floating point branch patterns
defm S_MM : FPBrcondPats<FGR32Opnd>, ISA_MIPS1_NOT_32R6_64R6;
defm D32_MM : FPBrcondPats<AFGR64Opnd>, FGR_32, ISA_MIPS1_NOT_32R6_64R6;
// Floating point setcc
defm S_MM : FPSetccPats<MOVT_I_MM, MOVF_I_MM, (LI16_MM 1), FGR32Opnd>;
defm D32_MM : FPSetccPats<MOVT_I_MM, MOVF_I_MM, (LI16_MM 1), AFGR64Opnd>, FGR_32;
zoran.jovanovicUnsubmitted
Not Done
ReplyInline Actions

Nit: Line exceeds 80 characters.

zoran.jovanovic: Nit: Line exceeds 80 characters.
// Floating point select patterns
defm : FPSelectPats<FGR32Opnd, FGR32Opnd, "S_MM", MOVT_S, MOVF_S_MM>,
ISA_MIPS1_NOT_32R6_64R6;
defm : FPSelectPats<FGR32Opnd, AFGR64Opnd, "S_MM", MOVT_D32, MOVF_D32_MM>,
FGR_32, ISA_MIPS1_NOT_32R6_64R6;
defm : FPSelectPats<AFGR64Opnd, AFGR64Opnd, "D32_MM", MOVT_D32, MOVF_D32_MM>,
FGR_32, ISA_MIPS1_NOT_32R6_64R6;
defm : FPSelectPats<AFGR64Opnd, FGR32Opnd, "D32_MM", MOVT_S, MOVF_S_MM>,
FGR_32, ISA_MIPS1_NOT_32R6_64R6;
defm : FPSelectPats<FGR32Opnd, GPR32Opnd, "S_MM", MOVT_I, MOVF_I_MM>,
ISA_MIPS1_NOT_32R6_64R6;
defm : FPSelectPats<AFGR64Opnd, GPR32Opnd, "D32_MM", MOVT_I, MOVF_I_MM>,
FGR_32, ISA_MIPS1_NOT_32R6_64R6;
}
//===----------------------------------------------------------------------===//
// Instruction aliases.
//===----------------------------------------------------------------------===//
let AdditionalPredicates = [InMicroMips] in {
defm S_MM : FPCAliases<FGR32Opnd, "s">;
defm D32_MM : FPCAliases<AFGR64Opnd, "d">;
} }

lib/Target/Mips/MicroMipsInstrFormats.td

Show First 20 Lines • Show All 716 Lines • ▼ Show 20 Linesclass ADDS_FM_MM<bits<2> fmt, bits<8> funct> : MMArch {
let Inst{15-11} = fd; let Inst{15-11} = fd;
let Inst{10} = 0; let Inst{10} = 0;
let Inst{9-8} = fmt; let Inst{9-8} = fmt;
let Inst{7-0} = funct; let Inst{7-0} = funct;
list<dag> Pattern = []; list<dag> Pattern = [];
} }
class C_COND_FM_MM<bits<2> fmt, bits<4> cond> : MMArch {
bits <5> ft;
bits <5> fs;
bits <3> cc;
bits<32> Inst;
let Inst{31-26} = 0b010101;
let Inst{25-21} = ft;
let Inst{20-16} = fs;
let Inst{15-13} = cc;
let Inst{12} = 0;
let Inst{11-10} = fmt;
let Inst{9-6} = cond;
let Inst{5-0} = 0b111100;
}
class LWXC1_FM_MM<bits<9> funct> : MMArch { class LWXC1_FM_MM<bits<9> funct> : MMArch {
bits<5> fd; bits<5> fd;
bits<5> base; bits<5> base;
bits<5> index; bits<5> index;
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = 0x15; let Inst{31-26} = 0x15;
▲ Show 20 Lines • Show All 293 Lines • Show Last 20 Lines

lib/Target/Mips/MipsAsmPrinter.h

Show First 20 Lines • Show All 130 Lines • ▼ Show 20 Lines bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant, const char *ExtraCode, unsigned AsmVariant, const char *ExtraCode,
raw_ostream &O) override; raw_ostream &O) override;
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
unsigned AsmVariant, const char *ExtraCode, unsigned AsmVariant, const char *ExtraCode,
raw_ostream &O) override; raw_ostream &O) override;
void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O); void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
void printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O); void printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O);
void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
const char *Modifier = nullptr);
void printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O); void printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O);
void EmitStartOfAsmFile(Module &M) override; void EmitStartOfAsmFile(Module &M) override;
void EmitEndOfAsmFile(Module &M) override; void EmitEndOfAsmFile(Module &M) override;
void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS); void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
}; };
} }
#endif #endif

lib/Target/Mips/MipsAsmPrinter.cpp

Show First 20 Lines • Show All 648 Lines • ▼ Show 20 LinesprintMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
// print the same way as all normal 3 operand instructions. // print the same way as all normal 3 operand instructions.
printOperand(MI, opNum, O); printOperand(MI, opNum, O);
O << ", "; O << ", ";
printOperand(MI, opNum+1, O); printOperand(MI, opNum+1, O);
return; return;
} }
void MipsAsmPrinter:: void MipsAsmPrinter::
printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
const char *Modifier) {
const MachineOperand &MO = MI->getOperand(opNum);
O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
}
void MipsAsmPrinter::
printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) { printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) {
for (int i = opNum, e = MI->getNumOperands(); i != e; ++i) { for (int i = opNum, e = MI->getNumOperands(); i != e; ++i) {
if (i != opNum) O << ", "; if (i != opNum) O << ", ";
printOperand(MI, i, O); printOperand(MI, i, O);
} }
} }
void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) { void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
▲ Show 20 Lines • Show All 399 Lines • Show Last 20 Lines

lib/Target/Mips/MipsCondMov.td

Show First 20 Lines • Show All 255 Lines • ▼ Show 20 Linesdefm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
FGR_64; FGR_64;
defm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64>, defm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64>,
INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6, defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
FGR_64; FGR_64;
defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6, defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
FGR_64; FGR_64;
multiclass FPSetccPats<Instruction MOVT, Instruction MOVF, dag ADD,
RegisterOperand RC> {
def : MipsPat<(seteq RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_EQ_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setgt RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_ULE_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setge RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_ULT_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setlt RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_OLT_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setle RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_OLE_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setne RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_UEQ_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setoeq RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_EQ_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setogt RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_ULE_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setoge RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_ULT_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setolt RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_OLT_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setole RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_OLE_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setone RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_UEQ_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(seto RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_UN_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setuo RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_UN_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setueq RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_UEQ_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setugt RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_OLE_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setuge RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_OLT_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setult RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_ULT_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setule RC:$lhs, RC:$rhs),
(MOVF ZERO, (!cast<Instruction>("C_ULE_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
def : MipsPat<(setune RC:$lhs, RC:$rhs),
(MOVT ZERO, (!cast<Instruction>("C_EQ_"#NAME) RC:$lhs, RC:$rhs),
ADD)>;
}
let AdditionalPredicates = [NotInMicroMips] in {
defm S : FPSetccPats<MOVT_I, MOVF_I, (ADDiu ZERO, 1), FGR32Opnd>,
INSN_MIPS4_32_NOT_32R6_64R6;
defm D32 : FPSetccPats<MOVT_I, MOVF_I, (ADDiu ZERO, 1), AFGR64Opnd>, FGR_32,
INSN_MIPS4_32_NOT_32R6_64R6;
defm D64 : FPSetccPats<MOVT_I, MOVF_I, (ADDiu ZERO, 1), FGR64Opnd>, FGR_64,
INSN_MIPS4_32_NOT_32R6_64R6;
}
multiclass FPSelectPats<RegisterOperand RC, RegisterOperand RO, string Type, Instruction MOVT,
zoran.jovanovicUnsubmitted
Not Done
ReplyInline Actions

Nit: Line exceeds 80 characters.

zoran.jovanovic: Nit: Line exceeds 80 characters.
Instruction MOVF> {
// Ordered
def : MipsPat<(select (i32 (setoeq RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_EQ_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setogt RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_ULE_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setoge RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_ULT_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setolt RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_OLT_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setole RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_OLE_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setone RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_UEQ_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (seto RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_UN_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
// Unordered
def : MipsPat<(select (i32 (setuo RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_UN_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setueq RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_UEQ_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setugt RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_ULE_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setuge RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_ULE_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setult RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_ULT_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setule RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_ULE_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setune RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_UEQ_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setuo RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_EQ_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
// Unspecified ordering - treated as ordered.
def : MipsPat<(select (i32 (seteq RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_EQ_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setgt RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_OLE_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setge RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_LT_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setlt RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_LT_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setle RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVT RO:$t, (!cast<Instruction>("C_OLE_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
def : MipsPat<(select (i32 (setne RC:$lhs, RC:$rhs)), RO:$t, RO:$f),
(MOVF RO:$t, (!cast<Instruction>("C_EQ_"#Type) RC:$lhs,
RC:$rhs),
RO:$f)>;
}
let AdditionalPredicates = [NotInMicroMips] in {
defm : FPSelectPats<FGR32Opnd, FGR32Opnd, "S", MOVT_S, MOVF_S>,
INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<FGR32Opnd, AFGR64Opnd, "S", MOVT_D32, MOVF_D32>,
FGR_32, INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<FGR32Opnd, FGR64Opnd, "S", MOVT_D64, MOVF_D64>,
FGR_64, INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<AFGR64Opnd, AFGR64Opnd, "D32", MOVT_D32, MOVF_D32>,
FGR_32, INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<AFGR64Opnd, FGR32Opnd, "D32", MOVT_S, MOVF_S>,
FGR_32, INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<FGR64Opnd, FGR64Opnd, "D64", MOVT_D64, MOVF_D64>,
FGR_64, INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<FGR64Opnd, FGR32Opnd, "D64", MOVT_S, MOVF_S>,
FGR_64, INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<FGR32Opnd, GPR32Opnd, "S", MOVT_I, MOVF_I>,
INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<AFGR64Opnd, GPR32Opnd, "D32", MOVT_I, MOVF_I>,
FGR_32, INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<FGR64Opnd, GPR32Opnd, "D64", MOVT_I, MOVF_I>,
FGR_64, INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<FGR32Opnd, GPR64Opnd,"S", MOVT_I64, MOVF_I64>,
INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<AFGR64Opnd, GPR64Opnd, "D32", MOVT_I64, MOVF_I64>,
FGR_32, INSN_MIPS4_32_NOT_32R6_64R6;
defm : FPSelectPats<FGR64Opnd, GPR64Opnd, "D64", MOVT_I64, MOVF_I64>,
FGR_64, INSN_MIPS4_32_NOT_32R6_64R6;
}
// For targets that don't have conditional-move instructions // For targets that don't have conditional-move instructions
// we have to match SELECT nodes with pseudo instructions. // we have to match SELECT nodes with pseudo instructions.
let usesCustomInserter = 1 in { let usesCustomInserter = 1 in {
class Select_Pseudo<RegisterOperand RC> : class Select_Pseudo<RegisterOperand RC> :
PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F), PseudoSE<(outs RC:$dst), (ins RC:$T, GPR32Opnd:$cond, RC:$F),
[(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>, [(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>,
ISA_MIPS1_NOT_4_32; ISA_MIPS1_NOT_4_32;
class SelectFP_Pseudo_T<RegisterOperand RC> : class SelectFP_Pseudo_T<RegisterOperand RC> :
PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F), PseudoSE<(outs RC:$dst), (ins RC:$T, FCC:$cond, RC:$F),
[(set RC:$dst, (MipsCMovFP_T RC:$T, GPR32Opnd:$cond, RC:$F))]>, [(set RC:$dst, (MipsCMovFP_T RC:$T, FCC:$cond, RC:$F))]>,
ISA_MIPS1_NOT_4_32; ISA_MIPS1_NOT_4_32;
class SelectFP_Pseudo_F<RegisterOperand RC> : class SelectFP_Pseudo_F<RegisterOperand RC> :
PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F), PseudoSE<(outs RC:$dst), (ins RC:$T, FCC:$cond, RC:$F),
[(set RC:$dst, (MipsCMovFP_F RC:$T, GPR32Opnd:$cond, RC:$F))]>, [(set RC:$dst, (MipsCMovFP_F RC:$T, FCC:$cond, RC:$F))]>,
ISA_MIPS1_NOT_4_32; ISA_MIPS1_NOT_4_32;
} }
def PseudoSELECT_I : Select_Pseudo<GPR32Opnd>; def PseudoSELECT_I : Select_Pseudo<GPR32Opnd>;
def PseudoSELECT_I64 : Select_Pseudo<GPR64Opnd>; def PseudoSELECT_I64 : Select_Pseudo<GPR64Opnd>;
def PseudoSELECT_S : Select_Pseudo<FGR32Opnd>; def PseudoSELECT_S : Select_Pseudo<FGR32Opnd>;
def PseudoSELECT_D32 : Select_Pseudo<AFGR64Opnd>, FGR_32; def PseudoSELECT_D32 : Select_Pseudo<AFGR64Opnd>, FGR_32;
def PseudoSELECT_D64 : Select_Pseudo<FGR64Opnd>, FGR_64; def PseudoSELECT_D64 : Select_Pseudo<FGR64Opnd>, FGR_64;
def PseudoSELECTFP_T_I : SelectFP_Pseudo_T<GPR32Opnd>; def PseudoSELECTFP_T_I : SelectFP_Pseudo_T<GPR32Opnd>;
def PseudoSELECTFP_T_I64 : SelectFP_Pseudo_T<GPR64Opnd>; def PseudoSELECTFP_T_I64 : SelectFP_Pseudo_T<GPR64Opnd>;
def PseudoSELECTFP_T_S : SelectFP_Pseudo_T<FGR32Opnd>; def PseudoSELECTFP_T_S : SelectFP_Pseudo_T<FGR32Opnd>;
def PseudoSELECTFP_T_D32 : SelectFP_Pseudo_T<AFGR64Opnd>, FGR_32; def PseudoSELECTFP_T_D32 : SelectFP_Pseudo_T<AFGR64Opnd>, FGR_32;
def PseudoSELECTFP_T_D64 : SelectFP_Pseudo_T<FGR64Opnd>, FGR_64; def PseudoSELECTFP_T_D64 : SelectFP_Pseudo_T<FGR64Opnd>, FGR_64;
def PseudoSELECTFP_F_I : SelectFP_Pseudo_F<GPR32Opnd>; def PseudoSELECTFP_F_I : SelectFP_Pseudo_F<GPR32Opnd>;
def PseudoSELECTFP_F_I64 : SelectFP_Pseudo_F<GPR64Opnd>; def PseudoSELECTFP_F_I64 : SelectFP_Pseudo_F<GPR64Opnd>;
def PseudoSELECTFP_F_S : SelectFP_Pseudo_F<FGR32Opnd>; def PseudoSELECTFP_F_S : SelectFP_Pseudo_F<FGR32Opnd>;
def PseudoSELECTFP_F_D32 : SelectFP_Pseudo_F<AFGR64Opnd>, FGR_32; def PseudoSELECTFP_F_D32 : SelectFP_Pseudo_F<AFGR64Opnd>, FGR_32;
def PseudoSELECTFP_F_D64 : SelectFP_Pseudo_F<FGR64Opnd>, FGR_64; def PseudoSELECTFP_F_D64 : SelectFP_Pseudo_F<FGR64Opnd>, FGR_64;
let AdditionalPredicates = [NotInMicroMips] in {
defm : FPSelectPats<FGR32Opnd, FGR32Opnd, "S", PseudoSELECTFP_T_S,
PseudoSELECTFP_F_S>, ISA_MIPS1_NOT_4_32;
defm : FPSelectPats<AFGR64Opnd, AFGR64Opnd, "D32", PseudoSELECTFP_T_D32,
PseudoSELECTFP_F_D32>, FGR_32, ISA_MIPS1_NOT_4_32;
defm : FPSelectPats<FGR64Opnd, FGR64Opnd, "D64", PseudoSELECTFP_T_D64,
PseudoSELECTFP_F_D64>, FGR_64, ISA_MIPS1_NOT_4_32;
}

lib/Target/Mips/MipsFastISel.cpp

Show First 20 Lines • Show All 703 Lines • ▼ Show 20 Lines case CmpInst::FCMP_OGE:
break; break;
default: default:
llvm_unreachable("Only switching of a subset of CCs."); llvm_unreachable("Only switching of a subset of CCs.");
} }
unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass); unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass); unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg( emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg).addReg(RightReg);
zoran.jovanovicUnsubmitted
Not Done
ReplyInline Actions

Nit: Line exceeds 80 characters.

zoran.jovanovic: Nit: Line exceeds 80 characters.
Mips::FCC0, RegState::ImplicitDefine);
emitInst(CondMovOpc, ResultReg) emitInst(CondMovOpc, ResultReg)
.addReg(RegWithOne) .addReg(RegWithOne)
.addReg(Mips::FCC0) .addReg(Mips::FCC0)
.addReg(RegWithZero); .addReg(RegWithZero);
break; break;
} }
} }
return true; return true;
▲ Show 20 Lines • Show All 1,359 Lines • Show Last 20 Lines

lib/Target/Mips/MipsISelLowering.h

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Lines enum NodeType : unsigned {
DynAlloc, DynAlloc,
Sync, Sync,
Ext, Ext,
Ins, Ins,
// Pseudo Node used to read the FCC registers.
PseudoReadFCC,
// EXTR.W instrinsic nodes. // EXTR.W instrinsic nodes.
EXTP, EXTP,
EXTPDP, EXTPDP,
EXTR_S_H, EXTR_S_H,
EXTR_W, EXTR_W,
EXTR_R_W, EXTR_R_W,
EXTR_RS_W, EXTR_RS_W,
SHILO, SHILO,
▲ Show 20 Lines • Show All 493 Lines • Show Last 20 Lines

lib/Target/Mips/MipsISelLowering.cpp

Show First 20 Lines • Show All 138 Lines • ▼ Show 20 Linesconst char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
case MipsISD::Wrapper: return "MipsISD::Wrapper"; case MipsISD::Wrapper: return "MipsISD::Wrapper";
case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
case MipsISD::Sync: return "MipsISD::Sync"; case MipsISD::Sync: return "MipsISD::Sync";
case MipsISD::Ext: return "MipsISD::Ext"; case MipsISD::Ext: return "MipsISD::Ext";
case MipsISD::Ins: return "MipsISD::Ins"; case MipsISD::Ins: return "MipsISD::Ins";
case MipsISD::PseudoReadFCC: return "MipsISD::PseudoReadFCC";
case MipsISD::LWL: return "MipsISD::LWL"; case MipsISD::LWL: return "MipsISD::LWL";
case MipsISD::LWR: return "MipsISD::LWR"; case MipsISD::LWR: return "MipsISD::LWR";
case MipsISD::SWL: return "MipsISD::SWL"; case MipsISD::SWL: return "MipsISD::SWL";
case MipsISD::SWR: return "MipsISD::SWR"; case MipsISD::SWR: return "MipsISD::SWR";
case MipsISD::LDL: return "MipsISD::LDL"; case MipsISD::LDL: return "MipsISD::LDL";
case MipsISD::LDR: return "MipsISD::LDR"; case MipsISD::LDR: return "MipsISD::LDR";
case MipsISD::SDL: return "MipsISD::SDL"; case MipsISD::SDL: return "MipsISD::SDL";
case MipsISD::SDR: return "MipsISD::SDR"; case MipsISD::SDR: return "MipsISD::SDR";
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 LinesMipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
// Mips Custom Operations // Mips Custom Operations
setOperationAction(ISD::BR_JT, MVT::Other, Custom); setOperationAction(ISD::BR_JT, MVT::Other, Custom);
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::BlockAddress, MVT::i32, Custom); setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
setOperationAction(ISD::JumpTable, MVT::i32, Custom); setOperationAction(ISD::JumpTable, MVT::i32, Custom);
setOperationAction(ISD::ConstantPool, MVT::i32, Custom); setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
setOperationAction(ISD::SELECT, MVT::f32, Custom);
setOperationAction(ISD::SELECT, MVT::f64, Custom);
setOperationAction(ISD::SELECT, MVT::i32, Custom);
setOperationAction(ISD::SETCC, MVT::f32, Custom);
setOperationAction(ISD::SETCC, MVT::f64, Custom);
setOperationAction(ISD::BRCOND, MVT::Other, Custom);
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
if (Subtarget.isGP64bit()) { if (Subtarget.isGP64bit()) {
setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
setOperationAction(ISD::BlockAddress, MVT::i64, Custom); setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
setOperationAction(ISD::JumpTable, MVT::i64, Custom); setOperationAction(ISD::JumpTable, MVT::i64, Custom);
setOperationAction(ISD::ConstantPool, MVT::i64, Custom); setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
setOperationAction(ISD::SELECT, MVT::i64, Custom);
setOperationAction(ISD::LOAD, MVT::i64, Custom); setOperationAction(ISD::LOAD, MVT::i64, Custom);
setOperationAction(ISD::STORE, MVT::i64, Custom); setOperationAction(ISD::STORE, MVT::i64, Custom);
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
} }
▲ Show 20 Lines • Show All 193 Lines • ▼ Show 20 Lines if (N->hasAnyUseOfValue(1)) {
SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
HI, Ty, InGlue); HI, Ty, InGlue);
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
} }
return SDValue(); return SDValue();
} }
static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
switch (CC) {
default: llvm_unreachable("Unknown fp condition code!");
case ISD::SETEQ:
case ISD::SETOEQ: return Mips::FCOND_OEQ;
case ISD::SETUNE: return Mips::FCOND_UNE;
case ISD::SETLT:
case ISD::SETOLT: return Mips::FCOND_OLT;
case ISD::SETGT:
case ISD::SETOGT: return Mips::FCOND_OGT;
case ISD::SETLE:
case ISD::SETOLE: return Mips::FCOND_OLE;
case ISD::SETGE:
case ISD::SETOGE: return Mips::FCOND_OGE;
case ISD::SETULT: return Mips::FCOND_ULT;
case ISD::SETULE: return Mips::FCOND_ULE;
case ISD::SETUGT: return Mips::FCOND_UGT;
case ISD::SETUGE: return Mips::FCOND_UGE;
case ISD::SETUO: return Mips::FCOND_UN;
case ISD::SETO: return Mips::FCOND_OR;
case ISD::SETNE:
case ISD::SETONE: return Mips::FCOND_ONE;
case ISD::SETUEQ: return Mips::FCOND_UEQ;
}
}
/// This function returns true if the floating point conditional branches and
/// conditional moves which use condition code CC should be inverted.
static bool invertFPCondCodeUser(Mips::CondCode CC) {
if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
return false;
assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
"Illegal Condition Code");
return true;
}
// Creates and returns an FPCmp node from a setcc node.
// Returns Op if setcc is not a floating point comparison.
static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
// must be a SETCC node
if (Op.getOpcode() != ISD::SETCC)
return Op;
SDValue LHS = Op.getOperand(0);
if (!LHS.getValueType().isFloatingPoint())
return Op;
SDValue RHS = Op.getOperand(1);
SDLoc DL(Op);
// Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
// node if necessary.
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
}
// Creates and returns a CMovFPT/F node.
static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
SDValue False, const SDLoc &DL) {
ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
True.getValueType(), True, FCC0, False, Cond);
}
static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI, TargetLowering::DAGCombinerInfo &DCI,
const MipsSubtarget &Subtarget) { const MipsSubtarget &Subtarget) {
if (DCI.isBeforeLegalizeOps()) if (DCI.isBeforeLegalizeOps())
return SDValue(); return SDValue();
SDValue SetCC = N->getOperand(0); SDValue SetCC = N->getOperand(0);
▲ Show 20 Lines • Show All 305 Lines • ▼ Show 20 Lines
} }
SDValue MipsTargetLowering:: SDValue MipsTargetLowering::
LowerOperation(SDValue Op, SelectionDAG &DAG) const LowerOperation(SDValue Op, SelectionDAG &DAG) const
{ {
switch (Op.getOpcode()) switch (Op.getOpcode())
{ {
case ISD::BR_JT: return lowerBR_JT(Op, DAG); case ISD::BR_JT: return lowerBR_JT(Op, DAG);
case ISD::BRCOND: return lowerBRCOND(Op, DAG);
case ISD::ConstantPool: return lowerConstantPool(Op, DAG); case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
case ISD::JumpTable: return lowerJumpTable(Op, DAG); case ISD::JumpTable: return lowerJumpTable(Op, DAG);
case ISD::SELECT: return lowerSELECT(Op, DAG);
case ISD::SETCC: return lowerSETCC(Op, DAG);
case ISD::VASTART: return lowerVASTART(Op, DAG); case ISD::VASTART: return lowerVASTART(Op, DAG);
case ISD::VAARG: return lowerVAARG(Op, DAG); case ISD::VAARG: return lowerVAARG(Op, DAG);
case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
▲ Show 20 Lines • Show All 775 Lines • ▼ Show 20 Lines if (isPositionIndependent() || ABI.IsN64()) {
// RelocBase can be JumpTable, GOT or some sort of global base. // RelocBase can be JumpTable, GOT or some sort of global base.
Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr, Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
getPICJumpTableRelocBase(Table, DAG)); getPICJumpTableRelocBase(Table, DAG));
} }
return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr); return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
} }
SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
// The first operand is the chain, the second is the condition, the third is
// the block to branch to if the condition is true.
SDValue Chain = Op.getOperand(0);
SDValue Dest = Op.getOperand(2);
SDLoc DL(Op);
assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
// Return if flag is not set by a floating point comparison.
if (CondRes.getOpcode() != MipsISD::FPCmp)
return Op;
SDValue CCNode = CondRes.getOperand(2);
Mips::CondCode CC =
(Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
FCC0, Dest, CondRes);
}
SDValue MipsTargetLowering::
lowerSELECT(SDValue Op, SelectionDAG &DAG) const
{
assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
// Return if flag is not set by a floating point comparison.
if (Cond.getOpcode() != MipsISD::FPCmp)
return Op;
return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
SDLoc(Op));
}
SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
SDValue Cond = createFPCmp(DAG, Op);
assert(Cond.getOpcode() == MipsISD::FPCmp &&
"Floating point operand expected.");
SDLoc DL(Op);
SDValue True = DAG.getConstant(1, DL, MVT::i32);
SDValue False = DAG.getConstant(0, DL, MVT::i32);
return createCMovFP(DAG, Cond, True, False, DL);
}
SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
EVT Ty = Op.getValueType(); EVT Ty = Op.getValueType();
GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
const GlobalValue *GV = N->getGlobal(); const GlobalValue *GV = N->getGlobal();
if (!isPositionIndependent() && !ABI.IsN64()) { if (!isPositionIndependent() && !ABI.IsN64()) {
const MipsTargetObjectFile *TLOF = const MipsTargetObjectFile *TLOF =
▲ Show 20 Lines • Show All 2,229 Lines • ▼ Show 20 LinesMachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
// Next, add the true and fallthrough blocks as its successors. // Next, add the true and fallthrough blocks as its successors.
BB->addSuccessor(copy0MBB); BB->addSuccessor(copy0MBB);
BB->addSuccessor(sinkMBB); BB->addSuccessor(sinkMBB);
if (isFPCmp) { if (isFPCmp) {
// bc1[tf] cc, sinkMBB // bc1[tf] cc, sinkMBB
BuildMI(BB, DL, TII->get(Opc)) BuildMI(BB, DL, TII->get(Opc))
.addReg(MI.getOperand(1).getReg()) .addReg(MI.getOperand(2).getReg())
.addMBB(sinkMBB); .addMBB(sinkMBB);
} else { } else {
// bne rs, $0, sinkMBB // bne rs, $0, sinkMBB
BuildMI(BB, DL, TII->get(Opc)) BuildMI(BB, DL, TII->get(Opc))
.addReg(MI.getOperand(1).getReg()) .addReg(MI.getOperand(2).getReg())
.addReg(Mips::ZERO) .addReg(Mips::ZERO)
.addMBB(sinkMBB); .addMBB(sinkMBB);
} }
// copy0MBB: // copy0MBB:
// %FalseValue = ... // %FalseValue = ...
// # fallthrough to sinkMBB // # fallthrough to sinkMBB
BB = copy0MBB; BB = copy0MBB;
// Update machine-CFG edges // Update machine-CFG edges
BB->addSuccessor(sinkMBB); BB->addSuccessor(sinkMBB);
// sinkMBB: // sinkMBB:
// %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
// ... // ...
BB = sinkMBB; BB = sinkMBB;
BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
.addReg(MI.getOperand(2).getReg()) .addReg(MI.getOperand(1).getReg())
.addMBB(thisMBB) .addMBB(thisMBB)
.addReg(MI.getOperand(3).getReg()) .addReg(MI.getOperand(3).getReg())
.addMBB(copy0MBB); .addMBB(copy0MBB);
MI.eraseFromParent(); // The pseudo instruction is gone now. MI.eraseFromParent(); // The pseudo instruction is gone now.
return BB; return BB;
} }
Show All 22 Lines

lib/Target/Mips/MipsInstrFPU.td

Show All 17 Lines
// - 32 64-bit registers (default mode) // - 32 64-bit registers (default mode)
// - 16 even 32-bit registers (32-bit compatible mode) for // - 16 even 32-bit registers (32-bit compatible mode) for
// single and double access. // single and double access.
// * 32bit fp: // * 32bit fp:
// - 16 even 32-bit registers - single and double (aliased) // - 16 even 32-bit registers - single and double (aliased)
// - 32 32-bit registers (within single-only mode) // - 32 32-bit registers (within single-only mode)
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Floating Point Compare and Branch
def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>,
SDTCisVT<1, i32>,
SDTCisVT<2, OtherVT>]>;
def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
SDTCisVT<2, i32>]>;
def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>, def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>,
SDTCisSameAs<1, 3>]>; SDTCisSameAs<1, 3>]>;
def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>; def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
SDTCisVT<1, i32>, SDTCisVT<1, i32>,
SDTCisSameAs<1, 2>]>; SDTCisSameAs<1, 2>]>;
def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
SDTCisVT<1, f64>, SDTCisVT<1, f64>,
SDTCisVT<2, i32>]>; SDTCisVT<2, i32>]>;
def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
[SDNPHasChain, SDNPOptInGlue]>;
def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>; def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>;
def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
SDT_MipsExtractElementF64>; SDT_MipsExtractElementF64>;
// Operand for printing out a condition code. // Operand for printing out a condition code.
let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in def invertbit : Operand<i1>;
def condcode : Operand<i32>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Feature predicates. // Feature predicates.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def IsFP64bit : Predicate<"Subtarget->isFP64bit()">, def IsFP64bit : Predicate<"Subtarget->isFP64bit()">,
AssemblerPredicate<"FeatureFP64Bit">; AssemblerPredicate<"FeatureFP64Bit">;
def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">, def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">,
▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
[(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin, [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
FrmFI, opstr>, HARDFLOAT { FrmFI, opstr>, HARDFLOAT {
let AddedComplexity = 20; let AddedComplexity = 20;
} }
class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin, class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
SDPatternOperator Op = null_frag, bit DelaySlot = 1> : SDPatternOperator Op = null_frag, bit DelaySlot = 1> :
InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
!strconcat(opstr, "\t$fcc, $offset"), !strconcat(opstr, "\t$fcc, $offset"), [], Itin, FrmFI, opstr>,
[(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin, HARDFLOAT {
FrmFI, opstr>, HARDFLOAT {
let isBranch = 1; let isBranch = 1;
let isTerminator = 1; let isTerminator = 1;
let hasDelaySlot = DelaySlot; let hasDelaySlot = DelaySlot;
let Defs = [AT]; let Defs = [AT];
} }
class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
SDPatternOperator OpNode = null_frag> :
InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
!strconcat("c.$cond.", typestr, "\t$fs, $ft"),
[(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR,
!strconcat("c.$cond.", typestr)>, HARDFLOAT {
let Defs = [FCC0];
let isCodeGenOnly = 1;
}
class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC, class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC,
InstrItinClass itin> : InstrItinClass itin> :
InstSE<(outs), (ins RC:$fs, RC:$ft), InstSE<(outs FCCRegsOpnd:$fcc), (ins RC:$fs, RC:$ft),
!strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], itin, !strconcat("c.", CondStr, ".", Typestr, "\t$fcc, $fs, $ft"),
FrmFR>, HARDFLOAT; [(set FCCRegsOpnd:$fcc, (null_frag RC:$fs, RC:$ft))], itin,
FrmFR>, HARDFLOAT {
let BaseOpcode = !strconcat("c.", CondStr, ".", Typestr);
}
multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt, multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt,
InstrItinClass itin> { InstrItinClass itin> {
def C_F_#NAME : C_COND_FT<"f", TypeStr, RC, itin>, C_COND_FM<fmt, 0>; def C_F_#NAME : C_COND_FT<"f", TypeStr, RC, itin>, C_COND_FM<fmt, 0>;
def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC, itin>, C_COND_FM<fmt, 1>; def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC, itin>, C_COND_FM<fmt, 1>;
def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC, itin>, C_COND_FM<fmt, 2>; def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC, itin>, C_COND_FM<fmt, 2>;
def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC, itin>, C_COND_FM<fmt, 3>; def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC, itin>, C_COND_FM<fmt, 3>;
def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC, itin>, C_COND_FM<fmt, 4>; def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC, itin>, C_COND_FM<fmt, 4>;
def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC, itin>, C_COND_FM<fmt, 5>; def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC, itin>, C_COND_FM<fmt, 5>;
def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC, itin>, C_COND_FM<fmt, 6>; def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC, itin>, C_COND_FM<fmt, 6>;
def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC, itin>, C_COND_FM<fmt, 7>; def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC, itin>, C_COND_FM<fmt, 7>;
def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC, itin>, C_COND_FM<fmt, 8>; def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC, itin>, C_COND_FM<fmt, 8>;
def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC, itin>, C_COND_FM<fmt, 9>; def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC, itin>, C_COND_FM<fmt, 9>;
def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC, itin>, C_COND_FM<fmt, 10>; def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC, itin>, C_COND_FM<fmt, 10>;
def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC, itin>, C_COND_FM<fmt, 11>; def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC, itin>, C_COND_FM<fmt, 11>;
def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC, itin>, C_COND_FM<fmt, 12>; def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC, itin>, C_COND_FM<fmt, 12>;
def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC, itin>, C_COND_FM<fmt, 13>; def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC, itin>, C_COND_FM<fmt, 13>;
def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC, itin>, C_COND_FM<fmt, 14>; def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC, itin>, C_COND_FM<fmt, 14>;
def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC, itin>, C_COND_FM<fmt, 15>; def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC, itin>, C_COND_FM<fmt, 15>;
} }
defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6; defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6;
defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>,
FGR_32; ISA_MIPS1_NOT_32R6_64R6, FGR_32;
let DecoderNamespace = "Mips64" in let DecoderNamespace = "Mips64" in
defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>,
FGR_64; ISA_MIPS1_NOT_32R6_64R6, FGR_64;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Floating Point Instructions // Floating Point Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def ROUND_W_S : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>, def ROUND_W_S : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
ABSS_FM<0xc, 16>, ISA_MIPS2; ABSS_FM<0xc, 16>, ISA_MIPS2;
defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2; defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;
def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>, def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
▲ Show 20 Lines • Show All 255 Lines • ▼ Show 20 Linesdef BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6; BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, II_BC1FL, MIPS_BRANCH_F, 0>, def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, II_BC1FL, MIPS_BRANCH_F, 0>,
BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6; BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>, def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6; BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, II_BC1TL, MIPS_BRANCH_T, 0>, def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, II_BC1TL, MIPS_BRANCH_T, 0>,
BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6; BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
/// Floating Point Compare // Compare and branch patterns
multiclass FPBrcondPats<RegisterOperand RC> {
// Ordered
def : MipsPat<(brcond (i32 (setoeq RC:$lhs, RC:$rhs)), bb:$dst),
(BC1T (!cast<Instruction>("C_EQ_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
def : MipsPat<(brcond (i32 (setogt RC:$lhs, RC:$rhs)), bb:$dst),
(BC1F (!cast<Instruction>("C_OLE_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
def : MipsPat<(brcond (i32 (setoge RC:$lhs, RC:$rhs)), bb:$dst),
(BC1F (!cast<Instruction>("C_LT_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
def : MipsPat<(brcond (i32 (setolt RC:$lhs, RC:$rhs)), bb:$dst),
(BC1T (!cast<Instruction>("C_LT_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
def : MipsPat<(brcond (i32 (setole RC:$lhs, RC:$rhs)), bb:$dst),
(BC1T (!cast<Instruction>("C_OLE_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
def : MipsPat<(brcond (i32 (setone RC:$lhs, RC:$rhs)), bb:$dst),
(BC1F (!cast<Instruction>("C_EQ_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
def : MipsPat<(brcond (i32 (seto RC:$lhs, RC:$rhs)), bb:$dst),
(BC1F (!cast<Instruction>("C_UN_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
// Unordered
def : MipsPat<(brcond (i32 (setuo RC:$lhs, RC:$rhs)), bb:$dst),
(BC1T (!cast<Instruction>("C_UN_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
def : MipsPat<(brcond (i32 (setueq RC:$lhs, RC:$rhs)), bb:$dst),
(BC1T (!cast<Instruction>("C_UEQ_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
def : MipsPat<(brcond (i32 (setugt RC:$lhs, RC:$rhs)), bb:$dst),
(BC1F (!cast<Instruction>("C_OLE_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
(BC1F (!cast<Instruction>("C_OLT_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
def : MipsPat<(brcond (i32 (setult RC:$lhs, RC:$rhs)), bb:$dst),
(BC1T (!cast<Instruction>("C_ULT_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
(BC1T (!cast<Instruction>("C_ULE_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
def : MipsPat<(brcond (i32 (setune RC:$lhs, RC:$rhs)), bb:$dst),
(BC1F (!cast<Instruction>("C_EQ_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
def : MipsPat<(brcond (i32 (setuo RC:$lhs, RC:$rhs)), bb:$dst),
(BC1T (!cast<Instruction>("C_EQ_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
// Unspecified ordering - treated as ordered.
def : MipsPat<(brcond (i32 (seteq RC:$lhs, RC:$rhs)), bb:$dst),
(BC1T (!cast<Instruction>("C_EQ_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
def : MipsPat<(brcond (i32 (setgt RC:$lhs, RC:$rhs)), bb:$dst),
(BC1F (!cast<Instruction>("C_OLE_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
(BC1F (!cast<Instruction>("C_LT_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
def : MipsPat<(brcond (i32 (setlt RC:$lhs, RC:$rhs)), bb:$dst),
(BC1T (!cast<Instruction>("C_LT_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
(BC1T (!cast<Instruction>("C_OLE_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
def : MipsPat<(brcond (i32 (setne RC:$lhs, RC:$rhs)), bb:$dst),
(BC1F (!cast<Instruction>("C_EQ_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>;
}
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>, defm S : FPBrcondPats<FGR32Opnd>, ISA_MIPS1_NOT_32R6_64R6;
ISA_MIPS1_NOT_32R6_64R6; defm D32 : FPBrcondPats<AFGR64Opnd>, FGR_32, ISA_MIPS1_NOT_32R6_64R6;
def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, defm D64 : FPBrcondPats<FGR64Opnd>, FGR_64, ISA_MIPS1_NOT_32R6_64R6;
ISA_MIPS1_NOT_32R6_64R6, FGR_32;
} }
let DecoderNamespace = "Mips64" in
def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
ISA_MIPS1_NOT_32R6_64R6, FGR_64;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Floating Point Pseudo-Instructions // Floating Point Pseudo-Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// This pseudo instr gets expanded into 2 mtc1 instrs after register // This pseudo instr gets expanded into 2 mtc1 instrs after register
// allocation. // allocation.
class BuildPairF64Base<RegisterOperand RO> : class BuildPairF64Base<RegisterOperand RO> :
Show All 27 Linesdef PseudoTRUNC_W_D32 : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
"trunc.w.d\t$fd, $fs, $rs">, "trunc.w.d\t$fd, $fs, $rs">,
FGR_32, HARDFLOAT; FGR_32, HARDFLOAT;
def PseudoTRUNC_W_D : MipsAsmPseudoInst<(outs FGR32Opnd:$fd), def PseudoTRUNC_W_D : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
(ins FGR64Opnd:$fs, GPR32Opnd:$rs), (ins FGR64Opnd:$fs, GPR32Opnd:$rs),
"trunc.w.d\t$fd, $fs, $rs">, "trunc.w.d\t$fd, $fs, $rs">,
FGR_64, HARDFLOAT; FGR_64, HARDFLOAT;
// Pseudo instructions to read $fcc0 - $fcc7
def PseudoReadFCC :
PseudoSE<(outs GPR32Opnd:$rd), (ins invertbit:$invert, FCC:$fcc),
[], II_CFC1>;
multiclass Mips3ReadFCC<RegisterOperand RC> {
def : MipsPat<(seteq RC:$lhs, RC:$rhs),
(PseudoReadFCC 0,
(!cast<Instruction>("C_EQ_"#NAME) RC:$lhs, RC:$rhs))>;
def : MipsPat<(setgt RC:$lhs, RC:$rhs),
(PseudoReadFCC 1,
(!cast<Instruction>("C_ULE_"#NAME) RC:$lhs, RC:$rhs))>;
def : MipsPat<(setge RC:$lhs, RC:$rhs),
(PseudoReadFCC 1,
(!cast<Instruction>("C_ULT_"#NAME) RC:$lhs, RC:$rhs))>;
def : MipsPat<(setlt RC:$lhs, RC:$rhs),
(PseudoReadFCC 0,
(!cast<Instruction>("C_OLT_"#NAME) RC:$lhs, RC:$rhs))>;
def : MipsPat<(setle RC:$lhs, RC:$rhs),
(PseudoReadFCC 0,
(!cast<Instruction>("C_OLE_"#NAME) RC:$lhs, RC:$rhs))>;
def : MipsPat<(setne RC:$lhs, RC:$rhs),
(PseudoReadFCC 1,
(!cast<Instruction>("C_UEQ_"#NAME) RC:$lhs, RC:$rhs))>;
def : MipsPat<(setoeq RC:$lhs, RC:$rhs),
(PseudoReadFCC 0,
(!cast<Instruction>("C_EQ_"#NAME) RC:$lhs, RC:$rhs))>;
def : MipsPat<(setogt RC:$lhs, RC:$rhs),
(PseudoReadFCC 1,
(!cast<Instruction>("C_ULE_"#NAME) RC:$lhs, RC:$rhs))>;
def : MipsPat<(setoge RC:$lhs, RC:$rhs),
(PseudoReadFCC 1,
(!cast<Instruction>("C_ULT_"#NAME) RC:$lhs, RC:$rhs))>;
def : MipsPat<(setolt RC:$lhs, RC:$rhs),
(PseudoReadFCC 0,
(!cast<Instruction>("C_OLT_"#NAME) RC:$lhs, RC:$rhs))>;
def : MipsPat<(setole RC:$lhs, RC:$rhs),
(PseudoReadFCC 0,
(!cast<Instruction>("C_OLE_"#NAME) RC:$lhs, RC:$rhs))>;
def : MipsPat<(setone RC:$lhs, RC:$rhs),
(PseudoReadFCC 1,
(!cast<Instruction>("C_UEQ_"#NAME) RC:$lhs, RC:$rhs))>;
def : MipsPat<(seto RC:$lhs, RC:$rhs),
(PseudoReadFCC 1,
(!cast<Instruction>("C_UN_"#NAME) RC:$lhs, RC:$rhs))>;
def : MipsPat<(setuo RC:$lhs, RC:$rhs),
(PseudoReadFCC 0,
(!cast<Instruction>("C_UN_"#NAME) RC:$lhs, RC:$rhs))>;
def : MipsPat<(setueq RC:$lhs, RC:$rhs),
(PseudoReadFCC 0,
(!cast<Instruction>("C_UEQ_"#NAME) RC:$lhs, RC:$rhs))>;
def : MipsPat<(setugt RC:$lhs, RC:$rhs),
(PseudoReadFCC 1,
(!cast<Instruction>("C_OLE_"#NAME) RC:$lhs, RC:$rhs))>;
def : MipsPat<(setuge RC:$lhs, RC:$rhs),
(PseudoReadFCC 1,
(!cast<Instruction>("C_OLT_"#NAME) RC:$lhs, RC:$rhs))>;
def : MipsPat<(setult RC:$lhs, RC:$rhs),
(PseudoReadFCC 0,
(!cast<Instruction>("C_ULT_"#NAME) RC:$lhs, RC:$rhs))>;
def : MipsPat<(setule RC:$lhs, RC:$rhs),
(PseudoReadFCC 0,
(!cast<Instruction>("C_ULE_"#NAME) RC:$lhs, RC:$rhs))>;
def : MipsPat<(setune RC:$lhs, RC:$rhs),
(PseudoReadFCC 1,
(!cast<Instruction>("C_EQ_"#NAME) RC:$lhs, RC:$rhs))>;
}
defm S : Mips3ReadFCC<FGR32Opnd>, ISA_MIPS1_NOT_4_32;
defm D32 : Mips3ReadFCC<AFGR64Opnd>, FGR_32, ISA_MIPS1_NOT_4_32;
defm D64 : Mips3ReadFCC<FGR64Opnd>, FGR_64, ISA_MIPS1_NOT_4_32;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// InstAliases. // InstAliases.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>, def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT; ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT;
def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>, def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>,
ISA_MIPS2_NOT_32R6_64R6, HARDFLOAT; ISA_MIPS2_NOT_32R6_64R6, HARDFLOAT;
def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>, def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>,
ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT; ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT;
def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>, def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>,
ISA_MIPS2_NOT_32R6_64R6, HARDFLOAT; ISA_MIPS2_NOT_32R6_64R6, HARDFLOAT;
multiclass FPCAliases<RegisterOperand RC, string TypeString> {
def : MipsInstAlias<!strconcat("c.f.", TypeString, " $rs, $rt"),
(!cast<Instruction>("C_F_"#NAME) FCC0, RC:$rs, RC:$rt), 1>;
def : MipsInstAlias<!strconcat("c.un.", TypeString, " $rs, $rt"),
(!cast<Instruction>("C_UN_"#NAME) FCC0, RC:$rs, RC:$rt), 1>;
def : MipsInstAlias<!strconcat("c.eq.", TypeString, " $rs, $rt"),
(!cast<Instruction>("C_EQ_"#NAME) FCC0, RC:$rs, RC:$rt), 1>;
def : MipsInstAlias<!strconcat("c.ueq.", TypeString, " $rs, $rt"),
(!cast<Instruction>("C_UEQ_"#NAME) FCC0, RC:$rs, RC:$rt), 1>;
def : MipsInstAlias<!strconcat("c.olt.", TypeString, " $rs, $rt"),
(!cast<Instruction>("C_OLT_"#NAME) FCC0, RC:$rs, RC:$rt), 1>;
def : MipsInstAlias<!strconcat("c.ult.", TypeString, " $rs, $rt"),
(!cast<Instruction>("C_ULT_"#NAME) FCC0, RC:$rs, RC:$rt), 1>;
def : MipsInstAlias<!strconcat("c.ole.", TypeString, " $rs, $rt"),
(!cast<Instruction>("C_OLE_"#NAME) FCC0, RC:$rs, RC:$rt), 1>;
def : MipsInstAlias<!strconcat("c.ule.", TypeString, " $rs, $rt"),
(!cast<Instruction>("C_ULE_"#NAME) FCC0, RC:$rs, RC:$rt), 1>;
def : MipsInstAlias<!strconcat("c.sf.", TypeString, " $rs, $rt"),
(!cast<Instruction>("C_SF_"#NAME) FCC0, RC:$rs, RC:$rt), 1>;
def : MipsInstAlias<!strconcat("c.ngle.", TypeString, " $rs, $rt"),
(!cast<Instruction>("C_NGLE_"#NAME) FCC0, RC:$rs, RC:$rt), 1>;
def : MipsInstAlias<!strconcat("c.seq.", TypeString, " $rs, $rt"),
(!cast<Instruction>("C_SEQ_"#NAME) FCC0, RC:$rs, RC:$rt), 1>;
def : MipsInstAlias<!strconcat("c.ngl.", TypeString, " $rs, $rt"),
(!cast<Instruction>("C_NGL_"#NAME) FCC0, RC:$rs, RC:$rt), 1>;
def : MipsInstAlias<!strconcat("c.lt.", TypeString, " $rs, $rt"),
(!cast<Instruction>("C_LT_"#NAME) FCC0, RC:$rs, RC:$rt), 1>;
def : MipsInstAlias<!strconcat("c.nge.", TypeString, " $rs, $rt"),
(!cast<Instruction>("C_NGE_"#NAME) FCC0, RC:$rs, RC:$rt), 1>;
def : MipsInstAlias<!strconcat("c.le.", TypeString, " $rs, $rt"),
(!cast<Instruction>("C_LE_"#NAME) FCC0, RC:$rs, RC:$rt), 1>;
def : MipsInstAlias<!strconcat("c.ngt.", TypeString, " $rs, $rt"),
(!cast<Instruction>("C_NGT_"#NAME) FCC0, RC:$rs, RC:$rt), 1>;
}
let AdditionalPredicates = [NotInMicroMips] in {
defm S : FPCAliases<FGR32Opnd, "s">, HARDFLOAT, ISA_MIPS1_NOT_32R6_64R6;
defm D32 : FPCAliases<AFGR64Opnd, "d">, HARDFLOAT, ISA_MIPS1_NOT_32R6_64R6;
defm D64 : FPCAliases<FGR64Opnd, "d">, HARDFLOAT, ISA_MIPS1_NOT_32R6_64R6;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Floating Point Patterns // Floating Point Patterns
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>; def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>; def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)), def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
(PseudoCVT_S_W GPR32Opnd:$src)>; (PseudoCVT_S_W GPR32Opnd:$src)>;
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

lib/Target/Mips/MipsInstrFormats.td

Show First 20 Lines • Show All 819 Lines • ▼ Show 20 Linesclass BC1F_FM<bit nd, bit tf> : StdArch {
let Inst{17} = nd; let Inst{17} = nd;
let Inst{16} = tf; let Inst{16} = tf;
let Inst{15-0} = offset; let Inst{15-0} = offset;
} }
class CEQS_FM<bits<5> fmt> : StdArch { class CEQS_FM<bits<5> fmt> : StdArch {
bits<5> fs; bits<5> fs;
bits<5> ft; bits<5> ft;
bits<3> fcc;
bits<4> cond; bits<4> cond;
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = 0x11; let Inst{31-26} = 0x11;
let Inst{25-21} = fmt; let Inst{25-21} = fmt;
let Inst{20-16} = ft; let Inst{20-16} = ft;
let Inst{15-11} = fs; let Inst{15-11} = fs;
let Inst{10-8} = 0; // cc let Inst{10-8} = fcc;
let Inst{7-4} = 0x3; let Inst{7-4} = 0x3;
let Inst{3-0} = cond; let Inst{3-0} = cond;
} }
class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> { class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
let cond = c; let cond = c;
} }
▲ Show 20 Lines • Show All 120 Lines • Show Last 20 Lines

lib/Target/Mips/MipsRegisterInfo.td

Show First 20 Lines • Show All 387 Lines • ▼ Show 20 Linesdef OddSP : RegisterClass<"Mips", [f32], 32,
(decimate (sequence "D%u_64", 1, 31), 2))>, (decimate (sequence "D%u_64", 1, 31), 2))>,
Unallocatable; Unallocatable;
// FP control registers. // FP control registers.
def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
Unallocatable; Unallocatable;
// FP condition code registers. // FP condition code registers.
def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>, def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>;
Unallocatable;
// MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers. // MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers.
// This class allows us to represent this in codegen patterns. // This class allows us to represent this in codegen patterns.
def FGRCC : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>; def FGRCC : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>;
def MSA128B: RegisterClass<"Mips", [v16i8], 128, def MSA128B: RegisterClass<"Mips", [v16i8], 128,
(sequence "W%u", 0, 31)>; (sequence "W%u", 0, 31)>;
def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128, def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128,
▲ Show 20 Lines • Show All 262 Lines • Show Last 20 Lines

lib/Target/Mips/MipsSEInstrInfo.h

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 Linesprivate:
/// MTC1 F4, A5 /// MTC1 F4, A5
/// CVT_D32_W D2, F4 /// CVT_D32_W D2, F4
/// ///
/// We do this expansion post-RA to avoid inserting a floating point copy /// We do this expansion post-RA to avoid inserting a floating point copy
/// instruction between MTC1 and CVT_D32_W. /// instruction between MTC1 and CVT_D32_W.
void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned CvtOpc, unsigned MovOpc, bool IsI64) const; unsigned CvtOpc, unsigned MovOpc, bool IsI64) const;
/// Expand pseudo ReadFCC(I) instructions like so:
///
/// cfc1 $dst, $fcr25
/// srl $dst, $dst, (register number if not $fcc0)
/// nor $dst, $dst, $dst (if inverted)
/// andi $dst, $dst, 1
///
void expandReadFCC(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;
void expandExtractElementF64(MachineBasicBlock &MBB, void expandExtractElementF64(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, bool FP64) const; MachineBasicBlock::iterator I, bool FP64) const;
void expandBuildPairF64(MachineBasicBlock &MBB, void expandBuildPairF64(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, bool FP64) const; MachineBasicBlock::iterator I, bool FP64) const;
void expandEhReturn(MachineBasicBlock &MBB, void expandEhReturn(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const; MachineBasicBlock::iterator I) const;
}; };
} }
#endif #endif

lib/Target/Mips/MipsSEInstrInfo.cpp

Show First 20 Lines • Show All 371 Lines • ▼ Show 20 Lines case Mips::PseudoCVT_D32_W:
expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false); expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
break; break;
case Mips::PseudoCVT_S_L: case Mips::PseudoCVT_S_L:
expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
break; break;
case Mips::PseudoCVT_D64_W: case Mips::PseudoCVT_D64_W:
expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true); expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
break; break;
case Mips::PseudoReadFCC:
expandReadFCC(MBB, MI);
break;
case Mips::PseudoCVT_D64_L: case Mips::PseudoCVT_D64_L:
expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
break; break;
case Mips::BuildPairF64: case Mips::BuildPairF64:
expandBuildPairF64(MBB, MI, false); expandBuildPairF64(MBB, MI, false);
break; break;
case Mips::BuildPairF64_64: case Mips::BuildPairF64_64:
expandBuildPairF64(MBB, MI, true); expandBuildPairF64(MBB, MI, true);
▲ Show 20 Lines • Show All 231 Lines • ▼ Show 20 Linesvoid MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
if (SrcIsLarger) if (SrcIsLarger)
DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc); BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
} }
void MipsSEInstrInfo::expandReadFCC(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
assert(I->getOperand(1).isImm() && "Malformed PseudoReadFCC Node");
bool Invert = (I->getOperand(1).getImm()) == 1;
const MachineOperand &Dest = I->getOperand(0), &Src = I->getOperand(2);
unsigned DstReg = Dest.getReg(), SrcReg = Src.getReg();
DebugLoc DL = I->getDebugLoc();
BuildMI(MBB, I, DL, get(Mips::CFC1), DstReg).addReg(Mips::FCR31);
unsigned Shift = 0;
switch (SrcReg) {
case Mips::FCC0: Shift = 23; break;
case Mips::FCC1: Shift = 25; break;
case Mips::FCC2: Shift = 26; break;
case Mips::FCC3: Shift = 27; break;
case Mips::FCC4: Shift = 28; break;
case Mips::FCC5: Shift = 29; break;
case Mips::FCC6: Shift = 30; break;
case Mips::FCC7: Shift = 31; break;
default:
llvm_unreachable("Unknown $fcc register for expandReadFCC!");
}
BuildMI(MBB, I, DL, get(Mips::SRL), DstReg).addReg(DstReg).addImm(Shift);
if (Invert)
BuildMI(MBB, I, DL, get(Mips::NOR), DstReg).addReg(DstReg).addReg(DstReg);
BuildMI(MBB, I, DL, get(Mips::ANDi), DstReg).addReg(DstReg).addImm(1);
}
void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
bool FP64) const { bool FP64) const {
unsigned DstReg = I->getOperand(0).getReg(); unsigned DstReg = I->getOperand(0).getReg();
unsigned SrcReg = I->getOperand(1).getReg(); unsigned SrcReg = I->getOperand(1).getReg();
unsigned N = I->getOperand(2).getImm(); unsigned N = I->getOperand(2).getImm();
DebugLoc dl = I->getDebugLoc(); DebugLoc dl = I->getDebugLoc();
▲ Show 20 Lines • Show All 120 Lines • Show Last 20 Lines

test/CodeGen/Mips/fcmp.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.s $f12, $f14 ; MM32R3-DAG: c.eq.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp oeq float %a, %b %1 = fcmp oeq float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 14 Lines
; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12 ; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.s $f12, $f14 ; MM32R3-DAG: c.ule.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12 ; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp ogt float %a, %b %1 = fcmp ogt float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 14 Lines
; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12 ; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.s $f12, $f14 ; MM32R3-DAG: c.ult.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12 ; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp oge float %a, %b %1 = fcmp oge float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 14 Lines
; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.s $f12, $f14 ; MM32R3-DAG: c.olt.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp olt float %a, %b %1 = fcmp olt float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 14 Lines
; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.s $f12, $f14 ; MM32R3-DAG: c.ole.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp ole float %a, %b %1 = fcmp ole float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 16 Lines
; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 32-CMP-DAG: andi $2, $[[T2]], 1 ; 32-CMP-DAG: andi $2, $[[T2]], 1
; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1 ; 64-CMP-DAG: andi $2, $[[T2]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.s $f12, $f14 ; MM32R3-DAG: c.ueq.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
; MMR6-DAG: andi16 $2, $[[T2]], 1 ; MMR6-DAG: andi16 $2, $[[T2]], 1
%1 = fcmp one float %a, %b %1 = fcmp one float %a, %b
Show All 17 Lines
; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 32-CMP-DAG: andi $2, $[[T2]], 1 ; 32-CMP-DAG: andi $2, $[[T2]], 1
; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1 ; 64-CMP-DAG: andi $2, $[[T2]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.s $f12, $f14 ; MM32R3-DAG: c.un.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
; MMR6-DAG: andi16 $2, $[[T2]], 1 ; MMR6-DAG: andi16 $2, $[[T2]], 1
%1 = fcmp ord float %a, %b %1 = fcmp ord float %a, %b
Show All 15 Lines
; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.s $f12, $f14 ; MM32R3-DAG: c.ueq.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp ueq float %a, %b %1 = fcmp ueq float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 14 Lines
; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12 ; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.s $f12, $f14 ; MM32R3-DAG: c.ole.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12 ; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp ugt float %a, %b %1 = fcmp ugt float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 14 Lines
; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12 ; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.s $f12, $f14 ; MM32R3-DAG: c.olt.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12 ; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp uge float %a, %b %1 = fcmp uge float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 14 Lines
; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.s $f12, $f14 ; MM32R3-DAG: c.ult.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp ult float %a, %b %1 = fcmp ult float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 14 Lines
; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.s $f12, $f14 ; MM32R3-DAG: c.ule.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp ule float %a, %b %1 = fcmp ule float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 16 Lines
; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 32-CMP-DAG: andi $2, $[[T2]], 1 ; 32-CMP-DAG: andi $2, $[[T2]], 1
; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1 ; 64-CMP-DAG: andi $2, $[[T2]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.s $f12, $f14 ; MM32R3-DAG: c.eq.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
; MMR6-DAG: andi16 $2, $[[T2]], 1 ; MMR6-DAG: andi16 $2, $[[T2]], 1
%1 = fcmp une float %a, %b %1 = fcmp une float %a, %b
Show All 15 Lines
; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.s $f12, $f14 ; MM32R3-DAG: c.un.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp uno float %a, %b %1 = fcmp uno float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.d $f12, $f14 ; MM32R3-DAG: c.eq.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp oeq double %a, %b %1 = fcmp oeq double %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 14 Lines
; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12 ; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.d $f12, $f14 ; MM32R3-DAG: c.ule.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12 ; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp ogt double %a, %b %1 = fcmp ogt double %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 14 Lines
; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12 ; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.d $f12, $f14 ; MM32R3-DAG: c.ult.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12 ; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp oge double %a, %b %1 = fcmp oge double %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 14 Lines
; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.d $f12, $f14 ; MM32R3-DAG: c.olt.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp olt double %a, %b %1 = fcmp olt double %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 14 Lines
; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.d $f12, $f14 ; MM32R3-DAG: c.ole.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp ole double %a, %b %1 = fcmp ole double %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 16 Lines
; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 32-CMP-DAG: andi $2, $[[T2]], 1 ; 32-CMP-DAG: andi $2, $[[T2]], 1
; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1 ; 64-CMP-DAG: andi $2, $[[T2]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.d $f12, $f14 ; MM32R3-DAG: c.ueq.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
; MMR6-DAG: andi16 $2, $[[T2]], 1 ; MMR6-DAG: andi16 $2, $[[T2]], 1
%1 = fcmp one double %a, %b %1 = fcmp one double %a, %b
Show All 17 Lines
; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 32-CMP-DAG: andi $2, $[[T2]], 1 ; 32-CMP-DAG: andi $2, $[[T2]], 1
; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1 ; 64-CMP-DAG: andi $2, $[[T2]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.d $f12, $f14 ; MM32R3-DAG: c.un.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
; MMR6-DAG: andi16 $2, $[[T2]], 1 ; MMR6-DAG: andi16 $2, $[[T2]], 1
%1 = fcmp ord double %a, %b %1 = fcmp ord double %a, %b
Show All 15 Lines
; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.d $f12, $f14 ; MM32R3-DAG: c.ueq.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp ueq double %a, %b %1 = fcmp ueq double %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 14 Lines
; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12 ; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.d $f12, $f14 ; MM32R3-DAG: c.ole.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12 ; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp ugt double %a, %b %1 = fcmp ugt double %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 14 Lines
; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12 ; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12 ; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.d $f12, $f14 ; MM32R3-DAG: c.olt.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12 ; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12 ; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp uge double %a, %b %1 = fcmp uge double %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 14 Lines
; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.d $f12, $f14 ; MM32R3-DAG: c.ult.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp ult double %a, %b %1 = fcmp ult double %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 14 Lines
; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.d $f12, $f14 ; MM32R3-DAG: c.ule.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp ule double %a, %b %1 = fcmp ule double %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
Show All 16 Lines
; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 32-CMP-DAG: andi $2, $[[T2]], 1 ; 32-CMP-DAG: andi $2, $[[T2]], 1
; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1 ; 64-CMP-DAG: andi $2, $[[T2]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.d $f12, $f14 ; MM32R3-DAG: c.eq.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movt $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]]
; MMR6-DAG: andi16 $2, $[[T2]], 1 ; MMR6-DAG: andi16 $2, $[[T2]], 1
%1 = fcmp une double %a, %b %1 = fcmp une double %a, %b
Show All 15 Lines
; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 ; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 32-CMP-DAG: andi $2, $[[T1]], 1 ; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 ; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1 ; 64-CMP-DAG: andi $2, $[[T1]], 1
; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 ; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.d $f12, $f14 ; MM32R3-DAG: c.un.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R3-DAG: movf $[[T0]], $zero, $fcc0
; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 ; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 ; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; MMR6-DAG: andi16 $2, $[[T1]], 1 ; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp uno double %a, %b %1 = fcmp uno double %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
▲ Show 20 Lines • Show All 159 Lines • Show Last 20 Lines

test/CodeGen/Mips/selectcc.ll

Show All 12 Lines
; SOURCE-SCHED: lui ; SOURCE-SCHED: lui
; SOURCE-SCHED: addiu ; SOURCE-SCHED: addiu
; SOURCE-SCHED: addu ; SOURCE-SCHED: addu
; SOURCE-SCHED: lw ; SOURCE-SCHED: lw
; SOURCE-SCHED: sw ; SOURCE-SCHED: sw
; SOURCE-SCHED: lw ; SOURCE-SCHED: lw
; SOURCE-SCHED: lui ; SOURCE-SCHED: lui
; SOURCE-SCHED: sw ; SOURCE-SCHED: sw
; SOURCE-SCHED: c.olt.s
; SOURCE-SCHED: lw ; SOURCE-SCHED: lw
; SOURCE-SCHED: lwc1 ; SOURCE-SCHED: lwc1
; SOURCE-SCHED: mtc1 ; SOURCE-SCHED: mtc1
; SOURCE-SCHED: c.olt.s
; SOURCE-SCHED: jr ; SOURCE-SCHED: jr
store float 0.000000e+00, float* @gf0, align 4 store float 0.000000e+00, float* @gf0, align 4
store float 1.000000e+00, float* @gf1, align 4 store float 1.000000e+00, float* @gf1, align 4
%cmp = fcmp olt float %a, %b %cmp = fcmp olt float %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
%conv1 = sitofp i32 %conv to float %conv1 = sitofp i32 %conv to float
ret float %conv1 ret float %conv1
} }
Show All 11 Lines

test/MC/Mips/mips32/valid-xfail.s

# Instructions that should be valid but currently fail for known reasons (e.g. # Instructions that should be valid but currently fail for known reasons (e.g.
# they aren't implemented yet). # they aren't implemented yet).
# This test is set up to XPASS if any instruction generates an encoding. # This test is set up to XPASS if any instruction generates an encoding.
# #
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | not FileCheck %s # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | not FileCheck %s
# CHECK-NOT: encoding # CHECK-NOT: encoding
# XFAIL: * # XFAIL: *
.set noat .set noat
c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17 c.f.ps $fcc6,$f11,$f11
c.f.d $fcc4,$f11,$f21 c.le.ps $fcc1,$f7,$f20
c.f.s $fcc4,$f30,$f7 c.lt.ps $f19,$f5
c.le.d $fcc4,$f18,$f1 c.nge.ps $f1,$f26
c.le.s $fcc6,$f24,$f4 c.ngl.ps $f21,$f30
c.lt.d $fcc3,$f9,$f3 c.ngle.ps $fcc7,$f12,$f20
c.lt.s $fcc2,$f17,$f14 c.ngt.ps $fcc5,$f30,$f6
c.nge.d $fcc5,$f21,$f16 c.ole.ps $fcc7,$f21,$f8
c.nge.s $fcc3,$f11,$f8 c.olt.ps $fcc3,$f7,$f16
c.ngl.s $fcc2,$f31,$f23 c.seq.ps $fcc6,$f31,$f14
c.ngle.s $fcc2,$f18,$f23 c.sf.ps $fcc6,$f4,$f6
c.ngt.d $fcc4,$f24,$f7 c.ueq.ps $fcc1,$f5,$f29
c.ngt.s $fcc5,$f8,$f13 c.ule.ps $fcc6,$f17,$f3
c.ole.d $fcc2,$f16,$f31 c.ult.ps $fcc7,$f14,$f0
c.ole.s $fcc3,$f7,$f20 c.un.ps $fcc4,$f2,$f26
c.olt.d $fcc4,$f19,$f28
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.s $fcc7,$f1,$f25
c.ueq.d $fcc4,$f13,$f25
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.s $fcc1,$f30,$f4
rorv $13,$a3,$s5 rorv $13,$a3,$s5

test/MC/Mips/mips32/valid.s

Show All 35 Linesa:
bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d]
bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59]
blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7]
bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a]
bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc]
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08]
c.ngl.d $f29,$f29 c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32]
c.ngle.d $f0,$f16 c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32]
c.sf.d $f30,$f0 c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30]
c.sf.s $f14,$f22 c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30]
c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e]
c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e]
c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c]
c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c]
c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d]
c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d]
c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b]
c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39]
c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b]
c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39]
c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f]
c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f]
c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36]
c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36]
c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34]
c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34]
c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a]
c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a]
c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38]
c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38]
c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33]
c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33]
c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37]
c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37]
c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35]
c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35]
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.s $f22,$f28 cvt.d.s $f22,$f28
cvt.d.w $f26,$f11 cvt.d.w $f26,$f11
▲ Show 20 Lines • Show All 188 Lines • Show Last 20 Lines

test/MC/Mips/mips32r2/valid-xfail.s

# Instructions that should be valid but currently fail for known reasons (e.g. # Instructions that should be valid but currently fail for known reasons (e.g.
# they aren't implemented yet). # they aren't implemented yet).
# This test is set up to XPASS if any instruction generates an encoding. # This test is set up to XPASS if any instruction generates an encoding.
# #
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | not FileCheck %s # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | not FileCheck %s
# CHECK-NOT: encoding # CHECK-NOT: encoding
# XFAIL: * # XFAIL: *
.set noat .set noat
abs.ps $f22,$f8 abs.ps $f22,$f8
add.ps $f25,$f27,$f13 add.ps $f25,$f27,$f13
addqh.w $s7,$s7,$k1 addqh.w $s7,$s7,$k1
addqh_r.w $8,$v1,$zero addqh_r.w $8,$v1,$zero
alnv.ps $f12,$f18,$f30,$12 alnv.ps $f12,$f18,$f30,$12
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9 c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.ps $fcc6,$f11,$f11 c.f.ps $fcc6,$f11,$f11
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.ps $fcc1,$f7,$f20 c.le.ps $fcc1,$f7,$f20
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.ps $f19,$f5 c.lt.ps $f19,$f5
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.ps $f1,$f26 c.nge.ps $f1,$f26
c.nge.s $fcc3,$f11,$f8
c.ngl.ps $f21,$f30 c.ngl.ps $f21,$f30
c.ngl.s $fcc2,$f31,$f23
c.ngle.ps $fcc7,$f12,$f20 c.ngle.ps $fcc7,$f12,$f20
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.ps $fcc5,$f30,$f6 c.ngt.ps $fcc5,$f30,$f6
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.ps $fcc7,$f21,$f8 c.ole.ps $fcc7,$f21,$f8
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.ps $fcc3,$f7,$f16 c.olt.ps $fcc3,$f7,$f16
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.ps $fcc6,$f31,$f14 c.seq.ps $fcc6,$f31,$f14
c.seq.s $fcc7,$f1,$f25
c.sf.ps $fcc6,$f4,$f6 c.sf.ps $fcc6,$f4,$f6
c.ueq.d $fcc4,$f13,$f25
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
c.un.s $fcc1,$f30,$f4
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
cfcmsa $s6,$19 cfcmsa $s6,$19
ctcmsa $31,$s7 ctcmsa $31,$s7
cvt.d.l $f4,$f16 cvt.d.l $f4,$f16
cvt.ps.s $f3,$f18,$f19 cvt.ps.s $f3,$f18,$f19
cvt.s.l $f15,$f30 cvt.s.l $f15,$f30
cvt.s.pl $f30,$f1 cvt.s.pl $f30,$f1
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

test/MC/Mips/mips32r2/valid.s

Show All 35 Linesa:
bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d]
bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59]
blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7]
bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a]
bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc]
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08]
c.ngl.d $f29,$f29 c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32]
c.ngle.d $f0,$f16 c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32]
c.sf.d $f30,$f0 c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30]
c.sf.s $f14,$f22 c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30]
c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e]
c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e]
c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c]
c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c]
c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d]
c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d]
c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b]
c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39]
c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b]
c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39]
c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f]
c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f]
c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36]
c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36]
c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34]
c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34]
c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a]
c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a]
c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38]
c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38]
c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33]
c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33]
c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37]
c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37]
c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35]
c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35]
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.s $f22,$f28 cvt.d.s $f22,$f28
cvt.d.w $f26,$f11 cvt.d.w $f26,$f11
▲ Show 20 Lines • Show All 227 Lines • Show Last 20 Lines

test/MC/Mips/mips32r3/valid-xfail.s

# Instructions that should be valid but currently fail for known reasons (e.g. # Instructions that should be valid but currently fail for known reasons (e.g.
# they aren't implemented yet). # they aren't implemented yet).
# This test is set up to XPASS if any instruction generates an encoding. # This test is set up to XPASS if any instruction generates an encoding.
# #
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r3 | not FileCheck %s # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r3 | not FileCheck %s
# CHECK-NOT: encoding # CHECK-NOT: encoding
# XFAIL: * # XFAIL: *
.set noat .set noat
abs.ps $f22,$f8 abs.ps $f22,$f8
add.ps $f25,$f27,$f13 add.ps $f25,$f27,$f13
addqh.w $s7,$s7,$k1 addqh.w $s7,$s7,$k1
addqh_r.w $8,$v1,$zero addqh_r.w $8,$v1,$zero
alnv.ps $f12,$f18,$f30,$12 alnv.ps $f12,$f18,$f30,$12
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9 c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.ps $fcc6,$f11,$f11 c.f.ps $fcc6,$f11,$f11
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.ps $fcc1,$f7,$f20 c.le.ps $fcc1,$f7,$f20
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.ps $f19,$f5 c.lt.ps $f19,$f5
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.ps $f1,$f26 c.nge.ps $f1,$f26
c.nge.s $fcc3,$f11,$f8
c.ngl.ps $f21,$f30 c.ngl.ps $f21,$f30
c.ngl.s $fcc2,$f31,$f23
c.ngle.ps $fcc7,$f12,$f20 c.ngle.ps $fcc7,$f12,$f20
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.ps $fcc5,$f30,$f6 c.ngt.ps $fcc5,$f30,$f6
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.ps $fcc7,$f21,$f8 c.ole.ps $fcc7,$f21,$f8
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.ps $fcc3,$f7,$f16 c.olt.ps $fcc3,$f7,$f16
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.ps $fcc6,$f31,$f14 c.seq.ps $fcc6,$f31,$f14
c.seq.s $fcc7,$f1,$f25
c.sf.ps $fcc6,$f4,$f6 c.sf.ps $fcc6,$f4,$f6
c.ueq.d $fcc4,$f13,$f25
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
c.un.s $fcc1,$f30,$f4
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
cfcmsa $s6,$19 cfcmsa $s6,$19
ctcmsa $31,$s7 ctcmsa $31,$s7
cvt.d.l $f4,$f16 cvt.d.l $f4,$f16
cvt.ps.s $f3,$f18,$f19 cvt.ps.s $f3,$f18,$f19
cvt.s.l $f15,$f30 cvt.s.l $f15,$f30
cvt.s.pl $f30,$f1 cvt.s.pl $f30,$f1
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

test/MC/Mips/mips32r3/valid.s

Show All 35 Linesa:
bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d]
bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59]
blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7]
bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a]
bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc]
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08]
c.ngl.d $f29,$f29 c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32]
c.ngle.d $f0,$f16 c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32]
c.sf.d $f30,$f0 c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30]
c.sf.s $f14,$f22 c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30]
c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e]
c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e]
c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c]
c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c]
c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d]
c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d]
c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b]
c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39]
c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b]
c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39]
c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f]
c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f]
c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36]
c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36]
c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34]
c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34]
c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a]
c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a]
c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38]
c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38]
c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33]
c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33]
c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37]
c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37]
c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35]
c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35]
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.s $f22,$f28 cvt.d.s $f22,$f28
cvt.d.w $f26,$f11 cvt.d.w $f26,$f11
▲ Show 20 Lines • Show All 227 Lines • Show Last 20 Lines

test/MC/Mips/mips32r5/valid-xfail.s

# Instructions that should be valid but currently fail for known reasons (e.g. # Instructions that should be valid but currently fail for known reasons (e.g.
# they aren't implemented yet). # they aren't implemented yet).
# This test is set up to XPASS if any instruction generates an encoding. # This test is set up to XPASS if any instruction generates an encoding.
# #
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r5 | not FileCheck %s # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r5 | not FileCheck %s
# CHECK-NOT: encoding # CHECK-NOT: encoding
# XFAIL: * # XFAIL: *
.set noat .set noat
abs.ps $f22,$f8 abs.ps $f22,$f8
add.ps $f25,$f27,$f13 add.ps $f25,$f27,$f13
addqh.w $s7,$s7,$k1 addqh.w $s7,$s7,$k1
addqh_r.w $8,$v1,$zero addqh_r.w $8,$v1,$zero
alnv.ps $f12,$f18,$f30,$12 alnv.ps $f12,$f18,$f30,$12
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9 c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.ps $fcc6,$f11,$f11 c.f.ps $fcc6,$f11,$f11
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.ps $fcc1,$f7,$f20 c.le.ps $fcc1,$f7,$f20
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.ps $f19,$f5 c.lt.ps $f19,$f5
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.ps $f1,$f26 c.nge.ps $f1,$f26
c.nge.s $fcc3,$f11,$f8
c.ngl.ps $f21,$f30 c.ngl.ps $f21,$f30
c.ngl.s $fcc2,$f31,$f23
c.ngle.ps $fcc7,$f12,$f20 c.ngle.ps $fcc7,$f12,$f20
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.ps $fcc5,$f30,$f6 c.ngt.ps $fcc5,$f30,$f6
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.ps $fcc7,$f21,$f8 c.ole.ps $fcc7,$f21,$f8
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.ps $fcc3,$f7,$f16 c.olt.ps $fcc3,$f7,$f16
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.ps $fcc6,$f31,$f14 c.seq.ps $fcc6,$f31,$f14
c.seq.s $fcc7,$f1,$f25
c.sf.ps $fcc6,$f4,$f6 c.sf.ps $fcc6,$f4,$f6
c.ueq.d $fcc4,$f13,$f25
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
c.un.s $fcc1,$f30,$f4
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
cfcmsa $s6,$19 cfcmsa $s6,$19
ctcmsa $31,$s7 ctcmsa $31,$s7
cvt.d.l $f4,$f16 cvt.d.l $f4,$f16
cvt.ps.s $f3,$f18,$f19 cvt.ps.s $f3,$f18,$f19
cvt.s.l $f15,$f30 cvt.s.l $f15,$f30
cvt.s.pl $f30,$f1 cvt.s.pl $f30,$f1
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

test/MC/Mips/mips32r5/valid.s

Show All 35 Linesa:
bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d]
bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59]
blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7]
bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a]
bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc]
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08]
c.ngl.d $f29,$f29 c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32]
c.ngle.d $f0,$f16 c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32]
c.sf.d $f30,$f0 c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30]
c.sf.s $f14,$f22 c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30]
c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e]
c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e]
c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c]
c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c]
c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d]
c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d]
c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b]
c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39]
c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b]
c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39]
c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f]
c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f]
c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36]
c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36]
c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34]
c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34]
c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a]
c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a]
c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38]
c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38]
c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33]
c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33]
c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37]
c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37]
c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35]
c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35]
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.s $f22,$f28 cvt.d.s $f22,$f28
cvt.d.w $f26,$f11 cvt.d.w $f26,$f11
▲ Show 20 Lines • Show All 228 Lines • Show Last 20 Lines

test/MC/Mips/mips4/valid-xfail.s

# Instructions that should be valid but currently fail for known reasons (e.g. # Instructions that should be valid but currently fail for known reasons (e.g.
# they aren't implemented yet). # they aren't implemented yet).
# This test is set up to XPASS if any instruction generates an encoding. # This test is set up to XPASS if any instruction generates an encoding.
# #
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | not FileCheck %s # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | not FileCheck %s
# CHECK-NOT: encoding # CHECK-NOT: encoding
# XFAIL: * # XFAIL: *
.set noat .set noat
c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17 c.f.ps $fcc6,$f11,$f11
c.f.d $fcc4,$f11,$f21 c.le.ps $fcc1,$f7,$f20
c.f.s $fcc4,$f30,$f7 c.lt.ps $f19,$f5
c.le.d $fcc4,$f18,$f1 c.nge.ps $f1,$f26
c.le.s $fcc6,$f24,$f4 c.ngl.ps $f21,$f30
c.lt.d $fcc3,$f9,$f3 c.ngle.ps $fcc7,$f12,$f20
c.lt.s $fcc2,$f17,$f14 c.ngt.ps $fcc5,$f30,$f6
c.nge.d $fcc5,$f21,$f16 c.ole.ps $fcc7,$f21,$f8
c.nge.s $fcc3,$f11,$f8 c.olt.ps $fcc3,$f7,$f16
c.ngl.s $fcc2,$f31,$f23 c.seq.ps $fcc6,$f31,$f14
c.ngle.s $fcc2,$f18,$f23 c.sf.ps $fcc6,$f4,$f6
c.ngt.d $fcc4,$f24,$f7 c.ueq.ps $fcc1,$f5,$f29
c.ngt.s $fcc5,$f8,$f13 c.ule.ps $fcc6,$f17,$f3
c.ole.d $fcc2,$f16,$f31 c.ult.ps $fcc7,$f14,$f0
c.ole.s $fcc3,$f7,$f20 c.un.ps $fcc4,$f2,$f26
c.olt.d $fcc4,$f19,$f28
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.s $fcc7,$f1,$f25
c.ueq.d $fcc4,$f13,$f25
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.s $fcc1,$f30,$f4
recip.d $f19,$f6 recip.d $f19,$f6
recip.s $f3,$f30 recip.s $f3,$f30
rsqrt.d $f3,$f28 rsqrt.d $f3,$f28
rsqrt.s $f4,$f8 rsqrt.s $f4,$f8

test/MC/Mips/mips4/valid.s

Show All 35 Linesa:
bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d]
bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59]
blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7]
bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a]
bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc]
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08]
c.ngl.d $f29,$f29 c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32]
c.ngle.d $f0,$f16 c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32]
c.sf.d $f30,$f0 c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30]
c.sf.s $f14,$f22 c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30]
c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e]
c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e]
c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c]
c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c]
c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d]
c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d]
c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b]
c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39]
c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b]
c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39]
c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f]
c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f]
c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36]
c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36]
c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34]
c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34]
c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a]
c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a]
c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38]
c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38]
c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33]
c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33]
c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37]
c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37]
c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35]
c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35]
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.l $f4,$f16 cvt.d.l $f4,$f16
cvt.d.s $f22,$f28 cvt.d.s $f22,$f28
▲ Show 20 Lines • Show All 260 Lines • Show Last 20 Lines

test/MC/Mips/mips5/valid-xfail.s

# Instructions that should be valid but currently fail for known reasons (e.g. # Instructions that should be valid but currently fail for known reasons (e.g.
# they aren't implemented yet). # they aren't implemented yet).
# This test is set up to XPASS if any instruction generates an encoding. # This test is set up to XPASS if any instruction generates an encoding.
# #
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | not FileCheck %s # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | not FileCheck %s
# CHECK-NOT: encoding # CHECK-NOT: encoding
# XFAIL: * # XFAIL: *
.set noat .set noat
abs.ps $f22,$f8 abs.ps $f22,$f8
add.ps $f25,$f27,$f13 add.ps $f25,$f27,$f13
alnv.ps $f12,$f18,$f30,$12 alnv.ps $f12,$f18,$f30,$12
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9 c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.ps $fcc6,$f11,$f11 c.f.ps $fcc6,$f11,$f11
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.ps $fcc1,$f7,$f20 c.le.ps $fcc1,$f7,$f20
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.ps $f19,$f5 c.lt.ps $f19,$f5
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.ps $f1,$f26 c.nge.ps $f1,$f26
c.nge.s $fcc3,$f11,$f8
c.ngl.ps $f21,$f30 c.ngl.ps $f21,$f30
c.ngl.s $fcc2,$f31,$f23
c.ngle.ps $fcc7,$f12,$f20 c.ngle.ps $fcc7,$f12,$f20
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.ps $fcc5,$f30,$f6 c.ngt.ps $fcc5,$f30,$f6
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.ps $fcc7,$f21,$f8 c.ole.ps $fcc7,$f21,$f8
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.ps $fcc3,$f7,$f16 c.olt.ps $fcc3,$f7,$f16
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.ps $fcc6,$f31,$f14 c.seq.ps $fcc6,$f31,$f14
c.seq.s $fcc7,$f1,$f25
c.sf.ps $fcc6,$f4,$f6 c.sf.ps $fcc6,$f4,$f6
c.ueq.d $fcc4,$f13,$f25
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
c.un.s $fcc1,$f30,$f4
cvt.ps.s $f3,$f18,$f19 cvt.ps.s $f3,$f18,$f19
cvt.s.pl $f30,$f1 cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25 cvt.s.pu $f14,$f25
madd.ps $f22,$f3,$f14,$f3 madd.ps $f22,$f3,$f14,$f3
mov.ps $f22,$f17 mov.ps $f22,$f17
movf.ps $f10,$f28,$fcc6 movf.ps $f10,$f28,$fcc6
movn.ps $f31,$f31,$s3 movn.ps $f31,$f31,$s3
movt.ps $f20,$f25,$fcc2 movt.ps $f20,$f25,$fcc2
Show All 15 Lines

test/MC/Mips/mips5/valid.s

Show All 35 Linesa:
bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d]
bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59]
blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7]
bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a]
bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc]
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08]
c.ngl.d $f29,$f29 c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32]
c.ngle.d $f0,$f16 c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32]
c.sf.d $f30,$f0 c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30]
c.sf.s $f14,$f22 c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30]
c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e]
c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e]
c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c]
c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c]
c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d]
c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d]
c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b]
c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39]
c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b]
c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39]
c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f]
c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f]
c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36]
c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36]
c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34]
c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34]
c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a]
c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a]
c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38]
c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38]
c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33]
c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33]
c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37]
c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37]
c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35]
c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35]
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
ctc1 $a2,$26 ctc1 $a2,$26
cvt.d.l $f4,$f16 cvt.d.l $f4,$f16
cvt.d.s $f22,$f28 cvt.d.s $f22,$f28
▲ Show 20 Lines • Show All 262 Lines • Show Last 20 Lines

test/MC/Mips/mips64/valid-xfail.s

# Instructions that should be valid but currently fail for known reasons (e.g. # Instructions that should be valid but currently fail for known reasons (e.g.
# they aren't implemented yet). # they aren't implemented yet).
# This test is set up to XPASS if any instruction generates an encoding. # This test is set up to XPASS if any instruction generates an encoding.
# #
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | not FileCheck %s # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | not FileCheck %s
# CHECK-NOT: encoding # CHECK-NOT: encoding
# XFAIL: * # XFAIL: *
.set noat .set noat
abs.ps $f22,$f8 abs.ps $f22,$f8
add.ps $f25,$f27,$f13 add.ps $f25,$f27,$f13
alnv.ob $v22,$v19,$v30,$v1 alnv.ob $v22,$v19,$v30,$v1
alnv.ob $v31,$v23,$v30,$at alnv.ob $v31,$v23,$v30,$at
alnv.ob $v8,$v17,$v30,$a1 alnv.ob $v8,$v17,$v30,$a1
alnv.ps $f12,$f18,$f30,$12 alnv.ps $f12,$f18,$f30,$12
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9 c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.ps $fcc6,$f11,$f11 c.f.ps $fcc6,$f11,$f11
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.ps $fcc1,$f7,$f20 c.le.ps $fcc1,$f7,$f20
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.ps $f19,$f5 c.lt.ps $f19,$f5
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.ps $f1,$f26 c.nge.ps $f1,$f26
c.nge.s $fcc3,$f11,$f8
c.ngl.ps $f21,$f30 c.ngl.ps $f21,$f30
c.ngl.s $fcc2,$f31,$f23
c.ngle.ps $fcc7,$f12,$f20 c.ngle.ps $fcc7,$f12,$f20
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.ps $fcc5,$f30,$f6 c.ngt.ps $fcc5,$f30,$f6
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.ps $fcc7,$f21,$f8 c.ole.ps $fcc7,$f21,$f8
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.ps $fcc3,$f7,$f16 c.olt.ps $fcc3,$f7,$f16
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.ps $fcc6,$f31,$f14 c.seq.ps $fcc6,$f31,$f14
c.seq.s $fcc7,$f1,$f25
c.sf.ps $fcc6,$f4,$f6 c.sf.ps $fcc6,$f4,$f6
c.ueq.d $fcc4,$f13,$f25
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
c.un.s $fcc1,$f30,$f4
cvt.ps.s $f3,$f18,$f19 cvt.ps.s $f3,$f18,$f19
cvt.s.pl $f30,$f1 cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25 cvt.s.pu $f14,$f25
dmfc0 $10,c0_watchhi,2 dmfc0 $10,c0_watchhi,2
dmtc0 $15,c0_datalo dmtc0 $15,c0_datalo
madd.ps $f22,$f3,$f14,$f3 madd.ps $f22,$f3,$f14,$f3
mov.ps $f22,$f17 mov.ps $f22,$f17
movf.ps $f10,$f28,$fcc6 movf.ps $f10,$f28,$fcc6
Show All 19 Lines

test/MC/Mips/mips64/valid.s

Show All 35 Linesa:
bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d]
bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59]
blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7]
bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a]
bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc]
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08]
c.ngl.d $f29,$f29 c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32]
c.ngle.d $f0,$f16 c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32]
c.sf.d $f30,$f0 c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30]
c.sf.s $f14,$f22 c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30]
c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e]
c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e]
c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c]
c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c]
c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d]
c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d]
c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b]
c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39]
c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b]
c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39]
c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f]
c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f]
c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36]
c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36]
c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34]
c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34]
c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a]
c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a]
c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38]
c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38]
c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33]
c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33]
c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37]
c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37]
c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35]
c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35]
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
▲ Show 20 Lines • Show All 281 Lines • Show Last 20 Lines

test/MC/Mips/mips64r2/valid-xfail.s

# Instructions that should be valid but currently fail for known reasons (e.g. # Instructions that should be valid but currently fail for known reasons (e.g.
# they aren't implemented yet). # they aren't implemented yet).
# This test is set up to XPASS if any instruction generates an encoding. # This test is set up to XPASS if any instruction generates an encoding.
# #
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | not FileCheck %s # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | not FileCheck %s
# CHECK-NOT: encoding # CHECK-NOT: encoding
# XFAIL: * # XFAIL: *
.set noat .set noat
abs.ps $f22,$f8 abs.ps $f22,$f8
add.ps $f25,$f27,$f13 add.ps $f25,$f27,$f13
addqh.w $s7,$s7,$k1 addqh.w $s7,$s7,$k1
addqh_r.w $8,$v1,$zero addqh_r.w $8,$v1,$zero
alnv.ps $f12,$f18,$f30,$12 alnv.ps $f12,$f18,$f30,$12
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9 c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.ps $fcc6,$f11,$f11 c.f.ps $fcc6,$f11,$f11
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.ps $fcc1,$f7,$f20 c.le.ps $fcc1,$f7,$f20
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.ps $f19,$f5 c.lt.ps $f19,$f5
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.ps $f1,$f26 c.nge.ps $f1,$f26
c.nge.s $fcc3,$f11,$f8
c.ngl.ps $f21,$f30 c.ngl.ps $f21,$f30
c.ngl.s $fcc2,$f31,$f23
c.ngle.ps $fcc7,$f12,$f20 c.ngle.ps $fcc7,$f12,$f20
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.ps $fcc5,$f30,$f6 c.ngt.ps $fcc5,$f30,$f6
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.ps $fcc7,$f21,$f8 c.ole.ps $fcc7,$f21,$f8
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.ps $fcc3,$f7,$f16 c.olt.ps $fcc3,$f7,$f16
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.ps $fcc6,$f31,$f14 c.seq.ps $fcc6,$f31,$f14
c.seq.s $fcc7,$f1,$f25
c.sf.ps $fcc6,$f4,$f6 c.sf.ps $fcc6,$f4,$f6
c.ueq.d $fcc4,$f13,$f25
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
c.un.s $fcc1,$f30,$f4
cvt.ps.s $f3,$f18,$f19 cvt.ps.s $f3,$f18,$f19
cvt.s.pl $f30,$f1 cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25 cvt.s.pu $f14,$f25
dmfc0 $10,c0_watchhi,2 dmfc0 $10,c0_watchhi,2
dmfgc0 $gp,c0_perfcnt,6 dmfgc0 $gp,c0_perfcnt,6
dmt $k0 dmt $k0
dmtc0 $15,c0_datalo dmtc0 $15,c0_datalo
dmtgc0 $a2,c0_watchlo,2 dmtgc0 $a2,c0_watchlo,2
▲ Show 20 Lines • Show All 59 Lines • Show Last 20 Lines

test/MC/Mips/mips64r2/valid.s

Show All 35 Linesa:
bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d]
bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59]
blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7]
bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a]
bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc]
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08]
c.ngl.d $f29,$f29 c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32]
c.ngle.d $f0,$f16 c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32]
c.sf.d $f30,$f0 c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30]
c.sf.s $f14,$f22 c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30]
c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e]
c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e]
c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c]
c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c]
c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d]
c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d]
c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b]
c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39]
c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b]
c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39]
c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f]
c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f]
c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36]
c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36]
c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34]
c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34]
c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a]
c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a]
c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38]
c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38]
c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33]
c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33]
c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37]
c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37]
c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35]
c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35]
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
▲ Show 20 Lines • Show All 309 Lines • Show Last 20 Lines

test/MC/Mips/mips64r3/valid-xfail.s

Show All 9 Lines# XFAIL: *
abs.ps $f22,$f8 abs.ps $f22,$f8
add.ps $f25,$f27,$f13 add.ps $f25,$f27,$f13
addqh.w $s7,$s7,$k1 addqh.w $s7,$s7,$k1
addqh_r.w $8,$v1,$zero addqh_r.w $8,$v1,$zero
alnv.ob $v22,$v19,$v30,$v1 alnv.ob $v22,$v19,$v30,$v1
alnv.ob $v31,$v23,$v30,$at alnv.ob $v31,$v23,$v30,$at
alnv.ob $v8,$v17,$v30,$a1 alnv.ob $v8,$v17,$v30,$a1
alnv.ps $f12,$f18,$f30,$12 alnv.ps $f12,$f18,$f30,$12
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9 c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.ps $fcc6,$f11,$f11 c.f.ps $fcc6,$f11,$f11
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.ps $fcc1,$f7,$f20 c.le.ps $fcc1,$f7,$f20
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.ps $f19,$f5 c.lt.ps $f19,$f5
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.ps $f1,$f26 c.nge.ps $f1,$f26
c.nge.s $fcc3,$f11,$f8
c.ngl.ps $f21,$f30 c.ngl.ps $f21,$f30
c.ngl.s $fcc2,$f31,$f23
c.ngle.ps $fcc7,$f12,$f20 c.ngle.ps $fcc7,$f12,$f20
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.ps $fcc5,$f30,$f6 c.ngt.ps $fcc5,$f30,$f6
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.ps $fcc7,$f21,$f8 c.ole.ps $fcc7,$f21,$f8
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.ps $fcc3,$f7,$f16 c.olt.ps $fcc3,$f7,$f16
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.ps $fcc6,$f31,$f14 c.seq.ps $fcc6,$f31,$f14
c.seq.s $fcc7,$f1,$f25
c.sf.ps $fcc6,$f4,$f6 c.sf.ps $fcc6,$f4,$f6
c.ueq.d $fcc4,$f13,$f25
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
c.un.s $fcc1,$f30,$f4
cvt.ps.s $f3,$f18,$f19 cvt.ps.s $f3,$f18,$f19
cvt.s.pl $f30,$f1 cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25 cvt.s.pu $f14,$f25
dmfc0 $10,c0_watchhi,2 dmfc0 $10,c0_watchhi,2
dmfgc0 $gp,c0_perfcnt,6 dmfgc0 $gp,c0_perfcnt,6
dmt $k0 dmt $k0
dmtc0 $15,c0_datalo dmtc0 $15,c0_datalo
dmtgc0 $a2,c0_watchlo,2 dmtgc0 $a2,c0_watchlo,2
▲ Show 20 Lines • Show All 59 Lines • Show Last 20 Lines

test/MC/Mips/mips64r3/valid.s

Show All 35 Linesa:
bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d]
bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59]
blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7]
bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a]
bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc]
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08]
c.ngl.d $f29,$f29 c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32]
c.ngle.d $f0,$f16 c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32]
c.sf.d $f30,$f0 c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30]
c.sf.s $f14,$f22 c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30]
c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e]
c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e]
c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c]
c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c]
c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d]
c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d]
c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b]
c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39]
c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b]
c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39]
c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f]
c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f]
c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36]
c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36]
c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34]
c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34]
c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a]
c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a]
c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38]
c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38]
c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33]
c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33]
c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37]
c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37]
c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35]
c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35]
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
▲ Show 20 Lines • Show All 301 Lines • Show Last 20 Lines

test/MC/Mips/mips64r5/valid-xfail.s

Show All 9 Lines# XFAIL: *
abs.ps $f22,$f8 abs.ps $f22,$f8
add.ps $f25,$f27,$f13 add.ps $f25,$f27,$f13
addqh.w $s7,$s7,$k1 addqh.w $s7,$s7,$k1
addqh_r.w $8,$v1,$zero addqh_r.w $8,$v1,$zero
alnv.ob $v22,$v19,$v30,$v1 alnv.ob $v22,$v19,$v30,$v1
alnv.ob $v31,$v23,$v30,$at alnv.ob $v31,$v23,$v30,$at
alnv.ob $v8,$v17,$v30,$a1 alnv.ob $v8,$v17,$v30,$a1
alnv.ps $f12,$f18,$f30,$12 alnv.ps $f12,$f18,$f30,$12
c.eq.d $fcc1,$f15,$f15
c.eq.ps $fcc5,$f0,$f9 c.eq.ps $fcc5,$f0,$f9
c.eq.s $fcc5,$f24,$f17
c.f.d $fcc4,$f11,$f21
c.f.ps $fcc6,$f11,$f11 c.f.ps $fcc6,$f11,$f11
c.f.s $fcc4,$f30,$f7
c.le.d $fcc4,$f18,$f1
c.le.ps $fcc1,$f7,$f20 c.le.ps $fcc1,$f7,$f20
c.le.s $fcc6,$f24,$f4
c.lt.d $fcc3,$f9,$f3
c.lt.ps $f19,$f5 c.lt.ps $f19,$f5
c.lt.s $fcc2,$f17,$f14
c.nge.d $fcc5,$f21,$f16
c.nge.ps $f1,$f26 c.nge.ps $f1,$f26
c.nge.s $fcc3,$f11,$f8
c.ngl.ps $f21,$f30 c.ngl.ps $f21,$f30
c.ngl.s $fcc2,$f31,$f23
c.ngle.ps $fcc7,$f12,$f20 c.ngle.ps $fcc7,$f12,$f20
c.ngle.s $fcc2,$f18,$f23
c.ngt.d $fcc4,$f24,$f7
c.ngt.ps $fcc5,$f30,$f6 c.ngt.ps $fcc5,$f30,$f6
c.ngt.s $fcc5,$f8,$f13
c.ole.d $fcc2,$f16,$f31
c.ole.ps $fcc7,$f21,$f8 c.ole.ps $fcc7,$f21,$f8
c.ole.s $fcc3,$f7,$f20
c.olt.d $fcc4,$f19,$f28
c.olt.ps $fcc3,$f7,$f16 c.olt.ps $fcc3,$f7,$f16
c.olt.s $fcc6,$f20,$f7
c.seq.d $fcc4,$f31,$f7
c.seq.ps $fcc6,$f31,$f14 c.seq.ps $fcc6,$f31,$f14
c.seq.s $fcc7,$f1,$f25
c.sf.ps $fcc6,$f4,$f6 c.sf.ps $fcc6,$f4,$f6
c.ueq.d $fcc4,$f13,$f25
c.ueq.ps $fcc1,$f5,$f29 c.ueq.ps $fcc1,$f5,$f29
c.ueq.s $fcc6,$f3,$f30
c.ule.d $fcc7,$f25,$f18
c.ule.ps $fcc6,$f17,$f3 c.ule.ps $fcc6,$f17,$f3
c.ule.s $fcc7,$f21,$f30
c.ult.d $fcc6,$f6,$f17
c.ult.ps $fcc7,$f14,$f0 c.ult.ps $fcc7,$f14,$f0
c.ult.s $fcc7,$f24,$f10
c.un.d $fcc6,$f23,$f24
c.un.ps $fcc4,$f2,$f26 c.un.ps $fcc4,$f2,$f26
c.un.s $fcc1,$f30,$f4
cvt.ps.s $f3,$f18,$f19 cvt.ps.s $f3,$f18,$f19
cvt.s.pl $f30,$f1 cvt.s.pl $f30,$f1
cvt.s.pu $f14,$f25 cvt.s.pu $f14,$f25
dmfc0 $10,c0_watchhi,2 dmfc0 $10,c0_watchhi,2
dmfgc0 $gp,c0_perfcnt,6 dmfgc0 $gp,c0_perfcnt,6
dmt $k0 dmt $k0
dmtc0 $15,c0_datalo dmtc0 $15,c0_datalo
dmtgc0 $a2,c0_watchlo,2 dmtgc0 $a2,c0_watchlo,2
▲ Show 20 Lines • Show All 59 Lines • Show Last 20 Lines

test/MC/Mips/mips64r5/valid.s

Show All 35 Linesa:
bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d]
bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59]
blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7]
bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a]
bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc]
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08]
c.ngl.d $f29,$f29 c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32]
c.ngle.d $f0,$f16 c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32]
c.sf.d $f30,$f0 c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30]
c.sf.s $f14,$f22 c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30]
c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e]
c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e]
c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c]
c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c]
c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d]
c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d]
c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b]
c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39]
c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b]
c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39]
c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f]
c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f]
c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36]
c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36]
c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34]
c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34]
c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a]
c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a]
c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38]
c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38]
c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33]
c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33]
c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37]
c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37]
c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35]
c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35]
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
ceil.l.d $f1,$f3 ceil.l.d $f1,$f3
ceil.l.s $f18,$f13 ceil.l.s $f18,$f13
ceil.w.d $f11,$f25 ceil.w.d $f11,$f25
ceil.w.s $f6,$f20 ceil.w.s $f6,$f20
cfc1 $s1,$21 cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
ctc1 $a2,$26 ctc1 $a2,$26
▲ Show 20 Lines • Show All 309 Lines • Show Last 20 Lines