As discussed on PR14593, this patch adds support for lowering to SHLD/SHRD from the patterns generated by DAGTypeLegalizer::ExpandShiftWithKnownAmountBit.
Might be nice to have a test which triggers this combine without going through legalization. (Should be possible, I think?)
Maybe it makes sense to split this into two separate if statements; one checking that the two outer shifts match, one checking that the inner shift is a shift by one. I found it a bit tricky to pick through. (I sort of wish we had an equivalent to IR pattern matching in SelectionDAG.)
Possibly - I'm interested in being able to match a lot of DAGCombiner patterns for both scalar and vector types.
Currently, at best we only match vector types with 'splatted' constant values - being able to generalize this would be very useful, I've played with some basic all_of style approaches but nothing has been great.
Could your template patterns make this any easier?
There's a pattern in X86InstrCompiler.td which does a shift->add transform because it's more efficient on x86... but we want to keep the SelectionDAG in canonical form as long as possible.