[X86] Improve 64-bit shifts on 32-bit targets (PR14593)

[RKSimon]

Summary

As discussed on PR14593, this patch adds support for lowering to SHLD/SHRD from the patterns generated by DAGTypeLegalizer::ExpandShiftWithKnownAmountBit.

[eli.friedman]

Might be nice to have a test which triggers this combine without going through legalization. (Should be possible, I think?)

lib/Target/X86/X86ISelLowering.cpp

28675

Maybe it makes sense to split this into two separate if statements; one checking that the two outer shifts match, one checking that the inner shift is a shift by one. I found it a bit tricky to pick through. (I sort of wish we had an equivalent to IR pattern matching in SelectionDAG.)

[majnemer]

lib/Target/X86/X86ISelLowering.cpp

28675

I actually worked on such a thing: http://pastebin.com/raw/A7WfuVC0

Think it makes sense for me to return to it?

[RKSimon]

Updated based on Feedback

[RKSimon]

lib/Target/X86/X86ISelLowering.cpp

28675

Possibly - I'm interested in being able to match a lot of DAGCombiner patterns for both scalar and vector types.

Currently, at best we only match vector types with 'splatted' constant values - being able to generalize this would be very useful, I've played with some basic all_of style approaches but nothing has been great.

Could your template patterns make this any easier?

[eli.friedman]

LGTM.

lib/Target/X86/X86ISelLowering.cpp

28679

If DAGCombine doesn't transform Y+Y to Y<<1, it should. (instcombine definitely does this.) Not really important for now, though.

[RKSimon]

Thanks Eli.

lib/Target/X86/X86ISelLowering.cpp

28679

In the old codegen we were seeing code like 'leal (%edx,%edx), %eax' being lowered from shl( v, 1 ) IR.

[eli.friedman]

lib/Target/X86/X86ISelLowering.cpp

28679

There's a pattern in X86InstrCompiler.td which does a shift->add transform because it's more efficient on x86... but we want to keep the SelectionDAG in canonical form as long as possible.

lib/Target/X86/X86ISelLowering.cpp

if (ShAmt0.getOpcode() == ISD::TRUNCATE)
     ShAmt0 = ShAmt0.getOperand(0);
   if (ShAmt1.getOpcode() == ISD::TRUNCATE)
     ShAmt1 = ShAmt1.getOperand(0);
 
   SDLoc DL(N);
   unsigned Opc = X86ISD::SHLD;
   SDValue Op0 = N0.getOperand(0);
   SDValue Op1 = N1.getOperand(0);
-  if (ShAmt0.getOpcode() == ISD::SUB) {
+  if (ShAmt0.getOpcode() == ISD::SUB ||
+      ShAmt0.getOpcode() == ISD::XOR) {
     Opc = X86ISD::SHRD;
     std::swap(Op0, Op1);
     std::swap(ShAmt0, ShAmt1);
   }
 
+  // OR( SHL( X, C ), SRL( Y, 32 - C ) ) -> SHLD( X, Y, C )
+  // OR( SRL( X, C ), SHL( Y, 32 - C ) ) -> SHRD( X, Y, C )
+  // OR( SHL( X, C ), SRL( SRL( Y, 1 ), XOR( C, 31 ) ) ) -> SHLD( X, Y, C )
+  // OR( SRL( X, C ), SHL( SHL( Y, 1 ), XOR( C, 31 ) ) ) -> SHRD( X, Y, C )
   unsigned Bits = VT.getSizeInBits();
   if (ShAmt1.getOpcode() == ISD::SUB) {
     SDValue Sum = ShAmt1.getOperand(0);
     if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
       SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
-      if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
+      if (ShAmt1Op1.getOpcode() == ISD::TRUNCATE)
         ShAmt1Op1 = ShAmt1Op1.getOperand(0);
       if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
         return DAG.getNode(Opc, DL, VT,
                            Op0, Op1,
                            DAG.getNode(ISD::TRUNCATE, DL,
                                        MVT::i8, ShAmt0));
     }
   } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
     ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
-    if (ShAmt0C &&
-        ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
+    if (ShAmt0C && (ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue()) == Bits)
       return DAG.getNode(Opc, DL, VT,
                          N0.getOperand(0), N1.getOperand(0),
                          DAG.getNode(ISD::TRUNCATE, DL,
                                        MVT::i8, ShAmt0));
+  } else if (ShAmt1.getOpcode() == ISD::XOR) {
+    SDValue Mask = ShAmt1.getOperand(1);
+    if (ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask)) {
+      unsigned InnerShift = (X86ISD::SHLD == Opc ? ISD::SRL : ISD::SHL);
+      SDValue ShAmt1Op0 = ShAmt1.getOperand(0);
+      if (ShAmt1Op0.getOpcode() == ISD::TRUNCATE)
+        ShAmt1Op0 = ShAmt1Op0.getOperand(0);
+      if (MaskC->getSExtValue() == (Bits - 1) && ShAmt1Op0 == ShAmt0 &&
+          Op1.getOpcode() == InnerShift &&
+          isa<ConstantSDNode>(Op1.getOperand(1)) &&
+          Op1.getConstantOperandVal(1) == 1) {
+        return DAG.getNode(Opc, DL, VT, Op0, Op1.getOperand(0),
+                           DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ShAmt0));
+      }
+    }
   }
 
   return SDValue();
 }
 
 // Generate NEG and CMOV for integer abs.
 static SDValue combineIntegerAbs(SDNode *N, SelectionDAG &DAG) {
   EVT VT = N->getValueType(0);

test/CodeGen/X86/legalize-shift-64.ll

; CHECK-NEXT:    retl
   %shl = shl i64 %conv, %sh_prom
   ret i64 %shl
 }
 
 define i64 @test2(i64 %xx, i32 %test) nounwind {
 ; CHECK-LABEL: test2:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    pushl %esi
-; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %ch
-; CHECK-NEXT:    andb $7, %ch
-; CHECK-NEXT:    movb %ch, %cl
-; CHECK-NEXT:    shll %cl, %esi
-; CHECK-NEXT:    movl %eax, %edx
-; CHECK-NEXT:    shrl %edx
-; CHECK-NEXT:    xorb $31, %cl
-; CHECK-NEXT:    shrl %cl, %edx
-; CHECK-NEXT:    orl %esi, %edx
-; CHECK-NEXT:    movb %ch, %cl
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; CHECK-NEXT:    andb $7, %cl
+; CHECK-NEXT:    movl %esi, %eax
 ; CHECK-NEXT:    shll %cl, %eax
+; CHECK-NEXT:    shldl %cl, %esi, %edx
 ; CHECK-NEXT:    popl %esi
 ; CHECK-NEXT:    retl
   %and = and i32 %test, 7
   %sh_prom = zext i32 %and to i64
   %shl = shl i64 %xx, %sh_prom
   ret i64 %shl
 }
 
 define i64 @test3(i64 %xx, i32 %test) nounwind {
 ; CHECK-LABEL: test3:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    pushl %esi
-; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %ch
-; CHECK-NEXT:    andb $7, %ch
-; CHECK-NEXT:    movb %ch, %cl
-; CHECK-NEXT:    shrl %cl, %esi
-; CHECK-NEXT:    leal (%edx,%edx), %eax
-; CHECK-NEXT:    xorb $31, %cl
-; CHECK-NEXT:    shll %cl, %eax
-; CHECK-NEXT:    orl %esi, %eax
-; CHECK-NEXT:    movb %ch, %cl
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; CHECK-NEXT:    andb $7, %cl
+; CHECK-NEXT:    shrdl %cl, %edx, %eax
 ; CHECK-NEXT:    shrl %cl, %edx
-; CHECK-NEXT:    popl %esi
 ; CHECK-NEXT:    retl
   %and = and i32 %test, 7
   %sh_prom = zext i32 %and to i64
   %shr = lshr i64 %xx, %sh_prom
   ret i64 %shr
 }
 
 define i64 @test4(i64 %xx, i32 %test) nounwind {
 ; CHECK-LABEL: test4:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    pushl %esi
-; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %ch
-; CHECK-NEXT:    andb $7, %ch
-; CHECK-NEXT:    movb %ch, %cl
-; CHECK-NEXT:    shrl %cl, %esi
-; CHECK-NEXT:    leal (%edx,%edx), %eax
-; CHECK-NEXT:    xorb $31, %cl
-; CHECK-NEXT:    shll %cl, %eax
-; CHECK-NEXT:    orl %esi, %eax
-; CHECK-NEXT:    movb %ch, %cl
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; CHECK-NEXT:    andb $7, %cl
+; CHECK-NEXT:    shrdl %cl, %edx, %eax
 ; CHECK-NEXT:    sarl %cl, %edx
-; CHECK-NEXT:    popl %esi
 ; CHECK-NEXT:    retl
   %and = and i32 %test, 7
   %sh_prom = zext i32 %and to i64
   %shr = ashr i64 %xx, %sh_prom
   ret i64 %shr
 }
 
 ; PR14668

test/CodeGen/X86/shift-double.ll

 }
 
 ; Shift i64 integers on 32-bit target by shift value less then 32 (PR14593)
 
 define i64 @test8(i64 %val, i32 %bits) nounwind {
 ; CHECK-LABEL: test8:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    pushl %esi
-; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %ch
-; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %cl
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; CHECK-NEXT:    movb %ch, %cl
-; CHECK-NEXT:    shll %cl, %esi
-; CHECK-NEXT:    movl %eax, %edx
-; CHECK-NEXT:    shrl %edx
-; CHECK-NEXT:    andb $31, %cl
-; CHECK-NEXT:    xorb $31, %cl
-; CHECK-NEXT:    shrl %cl, %edx
-; CHECK-NEXT:    orl %esi, %edx
-; CHECK-NEXT:    movb %ch, %cl
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; CHECK-NEXT:    movl %esi, %eax
 ; CHECK-NEXT:    shll %cl, %eax
+; CHECK-NEXT:    andb $31, %cl
+; CHECK-NEXT:    shldl %cl, %esi, %edx
 ; CHECK-NEXT:    popl %esi
 ; CHECK-NEXT:    retl
   %and = and i32 %bits, 31
   %sh_prom = zext i32 %and to i64
   %shl = shl i64 %val, %sh_prom
   ret i64 %shl
 }
 
 define i64 @test9(i64 %val, i32 %bits) nounwind {
 ; CHECK-LABEL: test9:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    pushl %esi
-; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %ch
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; CHECK-NEXT:    movb %ch, %cl
-; CHECK-NEXT:    shrl %cl, %esi
-; CHECK-NEXT:    leal (%edx,%edx), %eax
-; CHECK-NEXT:    andb $31, %cl
-; CHECK-NEXT:    xorb $31, %cl
-; CHECK-NEXT:    shll %cl, %eax
-; CHECK-NEXT:    orl %esi, %eax
-; CHECK-NEXT:    movb %ch, %cl
+; CHECK-NEXT:    movl %esi, %edx
 ; CHECK-NEXT:    sarl %cl, %edx
+; CHECK-NEXT:    andb $31, %cl
+; CHECK-NEXT:    shrdl %cl, %esi, %eax
 ; CHECK-NEXT:    popl %esi
 ; CHECK-NEXT:    retl
   %and = and i32 %bits, 31
   %sh_prom = zext i32 %and to i64
   %ashr = ashr i64 %val, %sh_prom
   ret i64 %ashr
 }
 
 define i64 @test10(i64 %val, i32 %bits) nounwind {
 ; CHECK-LABEL: test10:
 ; CHECK:       # BB#0:
 ; CHECK-NEXT:    pushl %esi
-; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %ch
+; CHECK-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; CHECK-NEXT:    movb %ch, %cl
-; CHECK-NEXT:    shrl %cl, %esi
-; CHECK-NEXT:    leal (%edx,%edx), %eax
-; CHECK-NEXT:    andb $31, %cl
-; CHECK-NEXT:    xorb $31, %cl
-; CHECK-NEXT:    shll %cl, %eax
-; CHECK-NEXT:    orl %esi, %eax
-; CHECK-NEXT:    movb %ch, %cl
+; CHECK-NEXT:    movl %esi, %edx
 ; CHECK-NEXT:    shrl %cl, %edx
+; CHECK-NEXT:    andb $31, %cl
+; CHECK-NEXT:    shrdl %cl, %esi, %eax
 ; CHECK-NEXT:    popl %esi
 ; CHECK-NEXT:    retl
   %and = and i32 %bits, 31
   %sh_prom = zext i32 %and to i64
   %lshr = lshr i64 %val, %sh_prom
   ret i64 %lshr
 }