AMDGPU: Set sizes on control flow pseudos

[nhaehnle]

Out of curiosity, what's the purpose of this? Does it affect heuristics somewhere?

Depending on what the semantics are supposed to be, you may want to change SI_ELSE to 8 instead of 12, since the most likely lowering requires only two instructions. (Of course, the maximum is still 12.)

Apart from the SI_ELSE point (which depends on the intended semantics here), LGTM.

[arsenm]

In D22989#502088, @nhaehnle wrote:

Out of curiosity, what's the purpose of this? Does it affect heuristics somewhere?

Depending on what the semantics are supposed to be, you may want to change SI_ELSE to 8 instead of 12, since the most likely lowering requires only two instructions. (Of course, the maximum is still 12.)

Apart from the SI_ELSE point (which depends on the intended semantics here), LGTM.

This needs to be the upper bound (inline asm for example assumes all instructions are the maximum size). The else part could be specially handled in the size target hook, but I don't think it's that important.

I'm not 100% sure this will end up being necessary in the end since these should probably be expanded earlier, but for estimating if long branches are going to need to be expanded there need to be more accurate code size estimates. Currently my plan is to relax long branches after RA, but an earlier guess might be necessary for making sure the necessary SGPR pair for manipulating the program counter is available.

[nhaehnle]

Thanks for the explanation!

I agree that long branches should go after RA, since they need to account for spill instructions. There'll probably always be cases where the long branch has to scavenge an SGPR pair :/

[arsenm]

r278276

lib/Target/AMDGPU/SIInstructions.td

 let Uses = [EXEC], Defs = [EXEC, SCC] in {
 
 let isBranch = 1, isTerminator = 1 in {
 
 def SI_IF: PseudoInstSI <
   (outs SReg_64:$dst), (ins SReg_64:$vcc, brtarget:$target),
   [(set i64:$dst, (int_amdgcn_if i1:$vcc, bb:$target))]> {
   let Constraints = "";
+  let Size = 8;
 }
 
 def SI_ELSE : PseudoInstSI <
   (outs SReg_64:$dst), (ins SReg_64:$src, brtarget:$target, i1imm:$execfix)> {
   let Constraints = "$src = $dst";
+  let Size = 12;
 }
 
 def SI_LOOP : PseudoInstSI <
   (outs), (ins SReg_64:$saved, brtarget:$target),
   [(int_amdgcn_loop i64:$saved, bb:$target)]
->;
+> {
+  let Size = 8;
+}
 
 } // End isBranch = 1, isTerminator = 1
 
 
 def SI_BREAK : PseudoInstSI <
   (outs SReg_64:$dst), (ins SReg_64:$src),
   [(set i64:$dst, (int_amdgcn_break i64:$src))]
->;
+> {
+  let Size = 4;
+}
 
 def SI_IF_BREAK : PseudoInstSI <
   (outs SReg_64:$dst), (ins SReg_64:$vcc, SReg_64:$src),
   [(set i64:$dst, (int_amdgcn_if_break i1:$vcc, i64:$src))]
->;
+> {
+  let Size = 4;
+}
 
 def SI_ELSE_BREAK : PseudoInstSI <
   (outs SReg_64:$dst), (ins SReg_64:$src0, SReg_64:$src1),
   [(set i64:$dst, (int_amdgcn_else_break i64:$src0, i64:$src1))]
->;
+> {
+  let Size = 4;
+}
 
 def SI_END_CF : PseudoInstSI <
   (outs), (ins SReg_64:$saved),
   [(int_amdgcn_end_cf i64:$saved)]
->;
+> {
+  let Size = 4;
+}
 
 } // End Uses = [EXEC], Defs = [EXEC, SCC]
 
 let Uses = [EXEC], Defs = [EXEC,VCC] in {
 def SI_KILL : PseudoInstSI <
   (outs), (ins VSrc_32:$src),
   [(AMDGPUkill i32:$src)]> {
   let isConvergent = 1;