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Differential D22964

[OpenCL] Add missing tests for getOCLTypeName
ClosedPublic

Authored by ashi1 on Jul 29 2016, 10:49 AM.

Details

Reviewers
• tstellarAMD
yaxunl
arsenm
Commits
rG86c052238a18: [OpenCL] Add missing tests for getOCLTypeName
rL277759: [OpenCL] Add missing tests for getOCLTypeName
Summary

Adding missing tests for OCL type names for half, float, double, char, short, long, and unknown.

Diff Detail

Repository
rL LLVM

Event Timeline

ashi1 updated this revision to Diff 66147.Jul 29 2016, 10:49 AM
ashi1 retitled this revision from to [OpenCL] Add missing tests for getOCLTypeName.
ashi1 updated this object.
ashi1 added reviewers: arsenm, • tstellarAMD, yaxunl.
ashi1 set the repository for this revision to rL LLVM.
ashi1 added a subscriber: llvm-commits.
Herald added a subscriber: arsenm. · View Herald TranscriptJul 29 2016, 10:49 AM
yaxunl accepted this revision.Aug 2 2016, 7:55 AM
yaxunl edited edge metadata.

LGTM. Thanks!

This revision is now accepted and ready to land.Aug 2 2016, 7:55 AM
Closed by commit rL277759: [OpenCL] Add missing tests for getOCLTypeName (authored by yaxunl). · Explain WhyAug 4 2016, 12:52 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
AMDGPUAsmPrinter.cpp
AMDGPUAsmPrinter.cpp (revision 277154)
2 lines
test/
CodeGen/
AMDGPU/
runtime-metadata.ll
runtime-metadata.ll (revision 277154)
217 lines

Diff 66147

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

Context not available.
return (Twine(getOCLTypeName(EleTy, Signed)) + Twine(Size)).str(); return (Twine(getOCLTypeName(EleTy, Signed)) + Twine(Size)).str();
} }
default: default:
llvm_unreachable("invalid type"); return "unknown";
} }
} }
Context not available.

test/CodeGen/AMDGPU/runtime-metadata.ll

Context not available.
ret void ret void
} }
; CHECK-LABEL:{{^}}test_vec_type_hint_half:
; CHECK: .section .AMDGPU.runtime_metadata
; CHECK-NEXT: .byte 4
; CHECK-NEXT: .byte 6
; CHECK-NEXT: .long 23
; CHECK-NEXT: .ascii "test_vec_type_hint_half"
; CHECK-NEXT: .byte 7
; CHECK-NEXT: .byte 9
; CHECK-NEXT: .long 4
; CHECK-NEXT: .byte 10
; CHECK-NEXT: .long 4
; CHECK-NEXT: .byte 11
; CHECK-NEXT: .long 3
; CHECK-NEXT: .ascii "int"
; CHECK-NEXT: .byte 13
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .byte 14
; CHECK-NEXT: .short 6
; CHECK-NEXT: .byte 16
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .byte 8
; CHECK-NEXT: .byte 23
; CHECK-NEXT: .long 4
; CHECK-NEXT: .ascii "half"
; CHECK-NEXT: .byte 5
define amdgpu_kernel void @test_vec_type_hint_half(i32 %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !4 !vec_type_hint !26 {
ret void
}
; CHECK-LABEL:{{^}}test_vec_type_hint_float:
; CHECK: .section .AMDGPU.runtime_metadata
; CHECK-NEXT: .byte 4
; CHECK-NEXT: .byte 6
; CHECK-NEXT: .long 24
; CHECK-NEXT: .ascii "test_vec_type_hint_float"
; CHECK-NEXT: .byte 7
; CHECK-NEXT: .byte 9
; CHECK-NEXT: .long 4
; CHECK-NEXT: .byte 10
; CHECK-NEXT: .long 4
; CHECK-NEXT: .byte 11
; CHECK-NEXT: .long 3
; CHECK-NEXT: .ascii "int"
; CHECK-NEXT: .byte 13
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .byte 14
; CHECK-NEXT: .short 6
; CHECK-NEXT: .byte 16
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .byte 8
; CHECK-NEXT: .byte 23
; CHECK-NEXT: .long 5
; CHECK-NEXT: .ascii "float"
; CHECK-NEXT: .byte 5
define amdgpu_kernel void @test_vec_type_hint_float(i32 %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !4 !vec_type_hint !27 {
ret void
}
; CHECK-LABEL:{{^}}test_vec_type_hint_double:
; CHECK: .section .AMDGPU.runtime_metadata
; CHECK-NEXT: .byte 4
; CHECK-NEXT: .byte 6
; CHECK-NEXT: .long 25
; CHECK-NEXT: .ascii "test_vec_type_hint_double"
; CHECK-NEXT: .byte 7
; CHECK-NEXT: .byte 9
; CHECK-NEXT: .long 4
; CHECK-NEXT: .byte 10
; CHECK-NEXT: .long 4
; CHECK-NEXT: .byte 11
; CHECK-NEXT: .long 3
; CHECK-NEXT: .ascii "int"
; CHECK-NEXT: .byte 13
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .byte 14
; CHECK-NEXT: .short 6
; CHECK-NEXT: .byte 16
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .byte 8
; CHECK-NEXT: .byte 23
; CHECK-NEXT: .long 6
; CHECK-NEXT: .ascii "double"
; CHECK-NEXT: .byte 5
define amdgpu_kernel void @test_vec_type_hint_double(i32 %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !4 !vec_type_hint !28 {
ret void
}
; CHECK-LABEL:{{^}}test_vec_type_hint_char:
; CHECK: .section .AMDGPU.runtime_metadata
; CHECK-NEXT: .byte 4
; CHECK-NEXT: .byte 6
; CHECK-NEXT: .long 23
; CHECK-NEXT: .ascii "test_vec_type_hint_char"
; CHECK-NEXT: .byte 7
; CHECK-NEXT: .byte 9
; CHECK-NEXT: .long 4
; CHECK-NEXT: .byte 10
; CHECK-NEXT: .long 4
; CHECK-NEXT: .byte 11
; CHECK-NEXT: .long 3
; CHECK-NEXT: .ascii "int"
; CHECK-NEXT: .byte 13
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .byte 14
; CHECK-NEXT: .short 6
; CHECK-NEXT: .byte 16
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .byte 8
; CHECK-NEXT: .byte 23
; CHECK-NEXT: .long 4
; CHECK-NEXT: .ascii "char"
; CHECK-NEXT: .byte 5
define amdgpu_kernel void @test_vec_type_hint_char(i32 %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !4 !vec_type_hint !29 {
ret void
}
; CHECK-LABEL:{{^}}test_vec_type_hint_short:
; CHECK: .section .AMDGPU.runtime_metadata
; CHECK-NEXT: .byte 4
; CHECK-NEXT: .byte 6
; CHECK-NEXT: .long 24
; CHECK-NEXT: .ascii "test_vec_type_hint_short"
; CHECK-NEXT: .byte 7
; CHECK-NEXT: .byte 9
; CHECK-NEXT: .long 4
; CHECK-NEXT: .byte 10
; CHECK-NEXT: .long 4
; CHECK-NEXT: .byte 11
; CHECK-NEXT: .long 3
; CHECK-NEXT: .ascii "int"
; CHECK-NEXT: .byte 13
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .byte 14
; CHECK-NEXT: .short 6
; CHECK-NEXT: .byte 16
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .byte 8
; CHECK-NEXT: .byte 23
; CHECK-NEXT: .long 5
; CHECK-NEXT: .ascii "short"
; CHECK-NEXT: .byte 5
define amdgpu_kernel void @test_vec_type_hint_short(i32 %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !4 !vec_type_hint !30 {
ret void
}
; CHECK-LABEL:{{^}}test_vec_type_hint_long:
; CHECK: .section .AMDGPU.runtime_metadata
; CHECK-NEXT: .byte 4
; CHECK-NEXT: .byte 6
; CHECK-NEXT: .long 23
; CHECK-NEXT: .ascii "test_vec_type_hint_long"
; CHECK-NEXT: .byte 7
; CHECK-NEXT: .byte 9
; CHECK-NEXT: .long 4
; CHECK-NEXT: .byte 10
; CHECK-NEXT: .long 4
; CHECK-NEXT: .byte 11
; CHECK-NEXT: .long 3
; CHECK-NEXT: .ascii "int"
; CHECK-NEXT: .byte 13
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .byte 14
; CHECK-NEXT: .short 6
; CHECK-NEXT: .byte 16
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .byte 8
; CHECK-NEXT: .byte 23
; CHECK-NEXT: .long 4
; CHECK-NEXT: .ascii "long"
; CHECK-NEXT: .byte 5
define amdgpu_kernel void @test_vec_type_hint_long(i32 %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !4 !vec_type_hint !31 {
ret void
}
; CHECK-LABEL:{{^}}test_vec_type_hint_unknown:
; CHECK: .section .AMDGPU.runtime_metadata
; CHECK-NEXT: .byte 4
; CHECK-NEXT: .byte 6
; CHECK-NEXT: .long 26
; CHECK-NEXT: .ascii "test_vec_type_hint_unknown"
; CHECK-NEXT: .byte 7
; CHECK-NEXT: .byte 9
; CHECK-NEXT: .long 4
; CHECK-NEXT: .byte 10
; CHECK-NEXT: .long 4
; CHECK-NEXT: .byte 11
; CHECK-NEXT: .long 3
; CHECK-NEXT: .ascii "int"
; CHECK-NEXT: .byte 13
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .byte 14
; CHECK-NEXT: .short 6
; CHECK-NEXT: .byte 16
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .byte 8
; CHECK-NEXT: .byte 23
; CHECK-NEXT: .long 7
; CHECK-NEXT: .ascii "unknown"
; CHECK-NEXT: .byte 5
define amdgpu_kernel void @test_vec_type_hint_unknown(i32 %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !4 !vec_type_hint !32 {
ret void
}
; CHECK-LABEL:{{^}}test_reqd_wgs_vec_type_hint: ; CHECK-LABEL:{{^}}test_reqd_wgs_vec_type_hint:
; CHECK: .section .AMDGPU.runtime_metadata ; CHECK: .section .AMDGPU.runtime_metadata
; CHECK-NEXT: .byte 4 ; CHECK-NEXT: .byte 4
Context not available.
!23 = !{!"none", !"none", !"none"} !23 = !{!"none", !"none", !"none"}
!24 = !{!"int", !"short2", !"char3"} !24 = !{!"int", !"short2", !"char3"}
!25 = !{!"", !"", !""} !25 = !{!"", !"", !""}
!26 = !{half undef, i32 1}
!27 = !{float undef, i32 1}
!28 = !{double undef, i32 1}
!29 = !{i8 undef, i32 1}
!30 = !{i16 undef, i32 1}
!31 = !{i64 undef, i32 1}
!32 = !{i32 *undef, i32 1}
!50 = !{i32 1, i32 2, i32 3} !50 = !{i32 1, i32 2, i32 3}
!51 = !{!"int *", !"int *", !"int *"} !51 = !{!"int *", !"int *", !"int *"}
!60 = !{i32 1, i32 1, i32 1} !60 = !{i32 1, i32 1, i32 1}
Context not available.