AArch64: Consolidate branch inversion logic

[arsenm]

Missed a spot

[rovka]

LGTM, thanks.

[arsenm]

r277431

lib/Target/AArch64/AArch64BranchRelaxation.cpp

class AArch64BranchRelaxation : public MachineFunctionPass {
   MachineFunction *MF;
   const AArch64InstrInfo *TII;
 
   bool relaxBranchInstructions();
   void scanFunction();
   MachineBasicBlock *splitBlockBeforeInstr(MachineInstr &MI);
   void adjustBlockOffsets(MachineBasicBlock &MBB);
   bool isBlockInRange(const MachineInstr &MI, const MachineBasicBlock &BB) const;
-  void invertConditionalBranch(MachineInstr &MI) const;
-  unsigned insertInvertedConditionalBranch(MachineBasicBlock &MBB,
+
+  unsigned insertInvertedConditionalBranch(MachineBasicBlock &SrcBB,
+                                           MachineBasicBlock::iterator InsPt,
+                                           const DebugLoc &DL,
                                            const MachineInstr &OldBr,
                                            MachineBasicBlock &NewDestBB) const;
   unsigned insertUnconditionalBranch(MachineBasicBlock &MBB,
                                      MachineBasicBlock &NewDestBB,
                                      const DebugLoc &DL) const;
 
   bool fixupConditionalBranch(MachineInstr &MI);
   void computeBlockSize(const MachineBasicBlock &MBB);
AArch64BranchRelaxation::splitBlockBeforeInstr(MachineInstr &MI) {
 
   // Splice the instructions starting with MI over to NewBB.
   NewBB->splice(NewBB->end(), OrigBB, MI.getIterator(), OrigBB->end());
 
   // Add an unconditional branch from OrigBB to NewBB.
   // Note the new unconditional branch is not being recorded.
   // There doesn't seem to be meaningful DebugInfo available; this doesn't
   // correspond to anything in the source.
-  BuildMI(OrigBB, DebugLoc(), TII->get(AArch64::B)).addMBB(NewBB);
+  insertUnconditionalBranch(*OrigBB, *NewBB, DebugLoc());
 
   // Insert an entry into BlockInfo to align it properly with the block numbers.
   BlockInfo.insert(BlockInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
 
   // Figure out how large the OrigBB is.  As the first half of the original
   // block, it cannot contain a tablejump.  The size includes
   // the new jump we added.  (It should be possible to do this without
   // recounting everything, but it's very confusing, and this is rarely

 static inline void invertBccCondition(MachineInstr &MI) {
   assert(MI.getOpcode() == AArch64::Bcc && "Unexpected opcode!");
   MachineOperand &CCOp = MI.getOperand(0);
 
   AArch64CC::CondCode CC = static_cast<AArch64CC::CondCode>(CCOp.getImm());
   CCOp.setImm(AArch64CC::getInvertedCondCode(CC));
 }
 
-/// Invert the branch condition of \p MI and change the destination to \p NewB
-void AArch64BranchRelaxation::invertConditionalBranch(MachineInstr &MI) const {
-  MI.setDesc(TII->get(getOppositeConditionOpcode(MI.getOpcode())));
-
-  if (MI.getOpcode() == AArch64::Bcc)
-    invertBccCondition(MI);
-}
-
 /// Insert a conditional branch at the end of \p MBB to \p NewDestBB, using the
 /// inverse condition of branch \p OldBr.
 /// \returns The number of bytes added to the block.
 unsigned AArch64BranchRelaxation::insertInvertedConditionalBranch(
-  MachineBasicBlock &MBB,
+  MachineBasicBlock &SrcMBB,
+  MachineBasicBlock::iterator InsPt,
+  const DebugLoc &DL,
   const MachineInstr &OldBr,
   MachineBasicBlock &NewDestBB) const {
   unsigned OppositeCondOpc = getOppositeConditionOpcode(OldBr.getOpcode());
 
   MachineInstrBuilder MIB =
-    BuildMI(&MBB, OldBr.getDebugLoc(), TII->get(OppositeCondOpc))
+    BuildMI(SrcMBB, InsPt, DL, TII->get(OppositeCondOpc))
     .addOperand(OldBr.getOperand(0));
 
   unsigned Opc = OldBr.getOpcode();
 
   if (Opc == AArch64::TBZW || Opc == AArch64::TBNZW ||
       Opc == AArch64::TBZX || Opc == AArch64::TBNZX)
     MIB.addOperand(OldBr.getOperand(1));
 
if (std::next(MachineBasicBlock::iterator(MI)) ==
       // =>
       // bne L2
       // b   L1
       MachineBasicBlock *NewDest = getDestBlock(*BMI);
       if (isBlockInRange(MI, *NewDest)) {
         DEBUG(dbgs() << "  Invert condition and swap its destination with "
                      << *BMI);
         changeBranchDestBlock(*BMI, *DestBB);
-        invertConditionalBranch(MI);
-        changeBranchDestBlock(MI, *NewDest);
+
+        int NewSize =
+          insertInvertedConditionalBranch(*MBB, MI.getIterator(),
+                                          MI.getDebugLoc(), MI, *NewDest);
+        int OldSize = TII->getInstSizeInBytes(MI);
+        BlockInfo[MBB->getNumber()].Size += (NewSize - OldSize);
+        MI.eraseFromParent();
         return true;
       }
     }
   }
 
   if (NeedSplit) {
     // Analyze the branch so we know how to update the successor lists.
     MachineBasicBlock *TBB, *FBB;
bool AArch64BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) {
   }
 
   MachineBasicBlock &NextBB = *std::next(MachineFunction::iterator(MBB));
 
   DEBUG(dbgs() << "  Insert B to BB#" << DestBB->getNumber()
                << ", invert condition and change dest. to BB#"
                << NextBB.getNumber() << '\n');
 
+  unsigned &MBBSize = BlockInfo[MBB->getNumber()].Size;
+
   // Insert a new conditional branch and a new unconditional branch.
-  BlockInfo[MBB->getNumber()].Size
-    += insertInvertedConditionalBranch(*MBB, MI, NextBB);
+  MBBSize += insertInvertedConditionalBranch(*MBB, MBB->end(),
+                                             MI.getDebugLoc(), MI, NextBB);
 
-  BlockInfo[MBB->getNumber()].Size +=
-    insertUnconditionalBranch(*MBB, *DestBB, MI.getDebugLoc());
+  MBBSize += insertUnconditionalBranch(*MBB, *DestBB, MI.getDebugLoc());
 
   // Remove the old conditional branch.  It may or may not still be in MBB.
-  BlockInfo[MBB->getNumber()].Size -= TII->getInstSizeInBytes(MI);
+  MBBSize -= TII->getInstSizeInBytes(MI);
   MI.eraseFromParent();
 
   // Finally, keep the block offsets up to date.
   adjustBlockOffsets(*MBB);
   return true;
 }
 
 bool AArch64BranchRelaxation::relaxBranchInstructions() {