AMDGPU: Turn dead checks into asserts

[nhaehnle]

The INT_TO_FP ones look good to me. The other I'm not sure of because the SelectS_BFE path only applies to GCN. If you made sure that the R600 case is covered by a test or irrelevant, then this change is fine with me.

[arsenm]

In D22877#498006, @nhaehnle wrote:

The INT_TO_FP ones look good to me. The other I'm not sure of because the SelectS_BFE path only applies to GCN. If you made sure that the R600 case is covered by a test or irrelevant, then this change is fine with me.

R600 is covered by tests already. It just selects BFE with td patterns. The S_BFE case required custom code I think because of the way the operands are packed in the scalar version vs. the node/vector version

[arsenm]

r276946

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

 }
 
 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
                                                SelectionDAG &DAG) const {
   assert(Op.getOperand(0).getValueType() == MVT::i64 &&
          "operation should be legal");
 
   EVT DestVT = Op.getValueType();
-  if (DestVT == MVT::f64)
-    return LowerINT_TO_FP64(Op, DAG, false);
 
   if (DestVT == MVT::f32)
     return LowerINT_TO_FP32(Op, DAG, false);
 
-  return SDValue();
+  assert(DestVT == MVT::f64);
+  return LowerINT_TO_FP64(Op, DAG, false);
 }
 
 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
                                               SelectionDAG &DAG) const {
   assert(Op.getOperand(0).getValueType() == MVT::i64 &&
          "operation should be legal");
 
   EVT DestVT = Op.getValueType();
   if (DestVT == MVT::f32)
     return LowerINT_TO_FP32(Op, DAG, true);
 
-  if (DestVT == MVT::f64)
-    return LowerINT_TO_FP64(Op, DAG, true);
-
-  return SDValue();
+  assert(DestVT == MVT::f64);
 }
 
 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
                                                bool Signed) const {
   SDLoc SL(Op);
 
   SDValue Src = Op.getOperand(0);
 

 }
 
 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
                                                      SelectionDAG &DAG) const {
   EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
   MVT VT = Op.getSimpleValueType();
   MVT ScalarVT = VT.getScalarType();
 
-  if (!VT.isVector())
-    return SDValue();
+  assert(VT.isVector());
 
   SDValue Src = Op.getOperand(0);
   SDLoc DL(Op);
 
   // TODO: Don't scalarize on Evergreen?
   unsigned NElts = VT.getVectorNumElements();
   SmallVector<SDValue, 8> Args;
   DAG.ExtractVectorElements(Src, Args, 0, NElts);