TargetOpcodes: Rewrite the documentation for SUBREG_TO_REG

[MatzeB]

Summary

After some IRC discussion it became clear that the description/intention of this instruction is hard to understand.

Add a more verbose description and clarify the fact that this should not generate any code.

[mkuper]

LGTM with a tiny nit.
But I'd appreciate another pair of eyes verifying (again :-) ) that this describes the correct semantics.

include/llvm/Target/TargetOpcodes.def

62 ↗

(On Diff #65189)

Extra space before "This".

[qcolombet]

LGTM as well.

llvm/trunk/include/llvm/Target/TargetOpcodes.def

 /// value of the second register inserted. The first register is often
 /// defined by an IMPLICIT_DEF, because it is commonly used to implement
 /// anyext operations on target architectures which support it.
 HANDLE_TARGET_OPCODE(INSERT_SUBREG)
 
 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
 HANDLE_TARGET_OPCODE(IMPLICIT_DEF)
 
-/// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
-/// the first operand is an immediate integer constant. This constant is
-/// often zero, because it is commonly used to assert that the instruction
-/// defining the register implicitly clears the high bits.
+/// SUBREG_TO_REG - Assert the value of bits in a super register.
+/// The result of this instruction is the value of the second operand inserted
+/// into the subregister specified by the third operand. All other bits are
+/// assumed to be equal to the bits in the immediate integer constant in the
+/// first operand. This instruction just communicates information; No code
+/// should be generated.
+/// This is typically used after an instruction where the write to a subregister
+/// implicitly cleared the bits in the super registers.
 HANDLE_TARGET_OPCODE(SUBREG_TO_REG)
 
 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
 /// register-to-register copy into a specific register class. This is only
 /// used between instruction selection and MachineInstr creation, before
 /// virtual registers have been created for all the instructions, and it's
 /// only needed in cases where the register classes implied by the
 /// instructions are insufficient. It is emitted as a COPY MachineInstr.