This patch teaches the MIPS backend to use shifts and bitwise extract and
inserts when a solid mask of the form 0...1 or 1...0 rather than synthesising
the corresponding mask into a register and performing a logical and.
For MIPSR2, (d)ins(u) and (d)ext along with the zero register can be used to
implement masking operations that would be use logical and with a large
This reduces all such masking operations to a maximum of 2 instructions (shift
left+shift right or vice versa) or a minimum of one (bitwise extract or bitwise
insert with zero) in some cases.
As part of this, use the same trick to optimize zeroext for MIPS64R2.