MIRParser: Use dot instead of colon to mark subregisters

[MatzeB]

Summary

Change the syntax to use %0.sub8 to denote a subregister.

This seems like a more natural fit to denote subregisters; I also plan
to introduce a new ":classname" syntax in upcoming patches to denote the
register class of a vreg.

Note that this commit disallows plain identifiers to start with a '.'
character. This shouldn't affect anything as external names/IR
references are all prefixed with '$'/'%', plain identifiers are only
used for instruction names, register mask names and subreg indexes which should not start with a dot.

[qcolombet]

LGTM.

llvm/trunk/lib/CodeGen/MIRParser/MILexer.h

enum TokenKind {
     Newline,
 
     // Tokens with no info.
     comma,
     equal,
     underscore,
     colon,
     coloncolon,
+    dot,
     exclaim,
     lparen,
     rparen,
     lbrace,
     rbrace,
     plus,
     minus,
     less,

llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp

return StringSwitch<MIToken::TokenKind>(Identifier)
       .Case("address-taken", MIToken::kw_address_taken)
       .Case("landing-pad", MIToken::kw_landing_pad)
       .Case("liveins", MIToken::kw_liveins)
       .Case("successors", MIToken::kw_successors)
       .Default(MIToken::Identifier);
 }
 
 static Cursor maybeLexIdentifier(Cursor C, MIToken &Token) {
-  if (!isalpha(C.peek()) && C.peek() != '_' && C.peek() != '.')
+  if (!isalpha(C.peek()) && C.peek() != '_')
     return None;
   auto Range = C;
   while (isIdentifierChar(C.peek()))
     C.advance();
   auto Identifier = Range.upto(C);
   Token.reset(getIdentifierKind(Identifier), Identifier)
       .setStringValue(Identifier);
   return C;
static Cursor lexVirtualRegister(Cursor C, MIToken &Token) {
   auto NumberRange = C;
   while (isdigit(C.peek()))
     C.advance();
   Token.reset(MIToken::VirtualRegister, Range.upto(C))
       .setIntegerValue(APSInt(NumberRange.upto(C)));
   return C;
 }
 
+/// Returns true for a character allowed in a register name.
+static bool isRegisterChar(char C) {
+  return isIdentifierChar(C) && C != '.';
+}
+
 static Cursor maybeLexRegister(Cursor C, MIToken &Token) {
   if (C.peek() != '%')
     return None;
   if (isdigit(C.peek(1)))
     return lexVirtualRegister(C, Token);
   auto Range = C;
   C.advance(); // Skip '%'
-  while (isIdentifierChar(C.peek()))
+  while (isRegisterChar(C.peek()))
     C.advance();
   Token.reset(MIToken::NamedRegister, Range.upto(C))
       .setStringValue(Range.upto(C).drop_front(1)); // Drop the '%'
   return C;
 }
 
 static Cursor maybeLexGlobalValue(Cursor C, MIToken &Token,
                                   ErrorCallbackType ErrorCallback) {
ErrorCallback(Token.location(),
                   "use of unknown metadata keyword '" + StrVal + "'");
   return C;
 }
 
 static MIToken::TokenKind symbolToken(char C) {
   switch (C) {
   case ',':
     return MIToken::comma;
+  case '.':
+    return MIToken::dot;
   case '=':
     return MIToken::equal;
   case ':':
     return MIToken::colon;
   case '(':
     return MIToken::lparen;
   case ')':
     return MIToken::rparen;

llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp

if (OldFlags == Flags)
     // We know that the same flag is specified more than once when the flags
     // weren't modified.
     return error("duplicate '" + Token.stringValue() + "' register flag");
   lex();
   return false;
 }
 
 bool MIParser::parseSubRegisterIndex(unsigned &SubReg) {
-  assert(Token.is(MIToken::colon));
+  assert(Token.is(MIToken::dot));
   lex();
   if (Token.isNot(MIToken::Identifier))
-    return error("expected a subregister index after ':'");
+    return error("expected a subregister index after '.'");
   auto Name = Token.stringValue();
   SubReg = getSubRegIndex(Name);
   if (!SubReg)
     return error(Twine("use of unknown subregister index '") + Name + "'");
   lex();
   return false;
 }
 
if (parseRegisterFlag(Flags))
       return true;
   }
   if (!Token.isRegister())
     return error("expected a register after register flags");
   if (parseRegister(Reg))
     return true;
   lex();
   unsigned SubReg = 0;
-  if (Token.is(MIToken::colon)) {
+  if (Token.is(MIToken::dot)) {
     if (parseSubRegisterIndex(SubReg))
       return true;
     if (!TargetRegisterInfo::isVirtualRegister(Reg))
       return error("subregister index expects a virtual register");
   }
   if ((Flags & RegState::Define) == 0) {
     if (consumeIfPresent(MIToken::lparen)) {
       unsigned Idx;

llvm/trunk/lib/CodeGen/MIRPrinter.cpp

if (Op.isUndef())
       OS << "undef ";
     if (Op.isEarlyClobber())
       OS << "early-clobber ";
     if (Op.isDebug())
       OS << "debug-use ";
     printReg(Op.getReg(), OS, TRI);
     // Print the sub register.
     if (Op.getSubReg() != 0)
-      OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());
+      OS << '.' << TRI->getSubRegIndexName(Op.getSubReg());
     if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
       OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(I) << ")";
     assert((!IsDef || MRI) && "for IsDef, MRI must be provided");
     if (IsDef && MRI->getSize(Op.getReg()))
       OS << '(' << MRI->getSize(Op.getReg()) << ')';
     break;
   case MachineOperand::MO_Immediate:
     OS << Op.getImm();

llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir

 ...
 ---
 # Combined use/def transfer check, the basics.
 # CHECK-LABEL: name: test0
 # CHECK: S_NOP 0, implicit-def %0
 # CHECK: S_NOP 0, implicit-def %1
 # CHECK: S_NOP 0, implicit-def dead %2
 # CHECK: %3 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %3:sub0
-# CHECK: S_NOP 0, implicit %3:sub1
-# CHECK: S_NOP 0, implicit undef %3:sub2
-# CHECK: %4 = COPY %3:sub0_sub1
-# CHECK: %5 = COPY undef %3:sub2_sub3
-# CHECK: S_NOP 0, implicit %4:sub0
-# CHECK: S_NOP 0, implicit %4:sub1
-# CHECK: S_NOP 0, implicit undef %5:sub0
+# CHECK: S_NOP 0, implicit %3.sub0
+# CHECK: S_NOP 0, implicit %3.sub1
+# CHECK: S_NOP 0, implicit undef %3.sub2
+# CHECK: %4 = COPY %3.sub0_sub1
+# CHECK: %5 = COPY undef %3.sub2_sub3
+# CHECK: S_NOP 0, implicit %4.sub0
+# CHECK: S_NOP 0, implicit %4.sub1
+# CHECK: S_NOP 0, implicit undef %5.sub0
 name: test0
 isSSA: true
 registers:
   - { id: 0, class: sreg_32 }
   - { id: 1, class: sreg_32 }
   - { id: 2, class: sreg_32 }
   - { id: 3, class: sreg_128 }
   - { id: 4, class: sreg_64 }
   - { id: 5, class: sreg_64 }
 body: |
   bb.0:
     S_NOP 0, implicit-def %0
     S_NOP 0, implicit-def %1
     S_NOP 0, implicit-def %2
     %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub3
-    S_NOP 0, implicit %3:sub0
-    S_NOP 0, implicit %3:sub1
-    S_NOP 0, implicit %3:sub2
-    %4 = COPY %3:sub0_sub1
-    %5 = COPY %3:sub2_sub3
-    S_NOP 0, implicit %4:sub0
-    S_NOP 0, implicit %4:sub1
-    S_NOP 0, implicit %5:sub0
+    S_NOP 0, implicit %3.sub0
+    S_NOP 0, implicit %3.sub1
+    S_NOP 0, implicit %3.sub2
+    %4 = COPY %3.sub0_sub1
+    %5 = COPY %3.sub2_sub3
+    S_NOP 0, implicit %4.sub0
+    S_NOP 0, implicit %4.sub1
+    S_NOP 0, implicit %5.sub0
 ...
 ---
 # Check defined lanes transfer; Includes checking for some special cases like
 # undef operands or IMPLICIT_DEF definitions.
 # CHECK-LABEL: name: test1
 # CHECK: %0 = REG_SEQUENCE %sgpr0, {{[0-9]+}}, %sgpr0, {{[0-9]+}}
 # CHECK: %1 = INSERT_SUBREG %0, %sgpr1, {{[0-9]+}}
-# CHECK: %2 = INSERT_SUBREG %0:sub2_sub3, %sgpr42, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %1:sub0
-# CHECK: S_NOP 0, implicit undef %1:sub1
-# CHECK: S_NOP 0, implicit %1:sub2
-# CHECK: S_NOP 0, implicit %1:sub3
-# CHECK: S_NOP 0, implicit %2:sub0
-# CHECK: S_NOP 0, implicit undef %2:sub1
+# CHECK: %2 = INSERT_SUBREG %0.sub2_sub3, %sgpr42, {{[0-9]+}}
+# CHECK: S_NOP 0, implicit %1.sub0
+# CHECK: S_NOP 0, implicit undef %1.sub1
+# CHECK: S_NOP 0, implicit %1.sub2
+# CHECK: S_NOP 0, implicit %1.sub3
+# CHECK: S_NOP 0, implicit %2.sub0
+# CHECK: S_NOP 0, implicit undef %2.sub1
 
 # CHECK: %3 = IMPLICIT_DEF
 # CHECK: %4 = INSERT_SUBREG %0, undef %3, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit undef %4:sub0
-# CHECK: S_NOP 0, implicit undef %4:sub1
-# CHECK: S_NOP 0, implicit %4:sub2
-# CHECK: S_NOP 0, implicit undef %4:sub3
+# CHECK: S_NOP 0, implicit undef %4.sub0
+# CHECK: S_NOP 0, implicit undef %4.sub1
+# CHECK: S_NOP 0, implicit %4.sub2
+# CHECK: S_NOP 0, implicit undef %4.sub3
 
 # CHECK: %5 = EXTRACT_SUBREG %0, {{[0-9]+}}
 # CHECK: %6 = EXTRACT_SUBREG %5, {{[0-9]+}}
 # CHECK: %7 = EXTRACT_SUBREG %5, {{[0-9]+}}
 # CHECK: S_NOP 0, implicit %5
 # CHECK: S_NOP 0, implicit %6
 # CHECK: S_NOP 0, implicit undef %7
 
registers:
   - { id: 7, class: sreg_32 }
   - { id: 8, class: sreg_64 }
   - { id: 9, class: sreg_32 }
   - { id: 10, class: sreg_128 }
 body: |
   bb.0:
     %0 = REG_SEQUENCE %sgpr0, %subreg.sub0, %sgpr0, %subreg.sub2
     %1 = INSERT_SUBREG %0, %sgpr1, %subreg.sub3
-    %2 = INSERT_SUBREG %0:sub2_sub3, %sgpr42, %subreg.sub0
-    S_NOP 0, implicit %1:sub0
-    S_NOP 0, implicit %1:sub1
-    S_NOP 0, implicit %1:sub2
-    S_NOP 0, implicit %1:sub3
-    S_NOP 0, implicit %2:sub0
-    S_NOP 0, implicit %2:sub1
+    %2 = INSERT_SUBREG %0.sub2_sub3, %sgpr42, %subreg.sub0
+    S_NOP 0, implicit %1.sub0
+    S_NOP 0, implicit %1.sub1
+    S_NOP 0, implicit %1.sub2
+    S_NOP 0, implicit %1.sub3
+    S_NOP 0, implicit %2.sub0
+    S_NOP 0, implicit %2.sub1
 
     %3 = IMPLICIT_DEF
     %4 = INSERT_SUBREG %0, %3, %subreg.sub0
-    S_NOP 0, implicit %4:sub0
-    S_NOP 0, implicit %4:sub1
-    S_NOP 0, implicit %4:sub2
-    S_NOP 0, implicit %4:sub3
+    S_NOP 0, implicit %4.sub0
+    S_NOP 0, implicit %4.sub1
+    S_NOP 0, implicit %4.sub2
+    S_NOP 0, implicit %4.sub3
 
     %5 = EXTRACT_SUBREG %0, %subreg.sub0_sub1
     %6 = EXTRACT_SUBREG %5, %subreg.sub0
     %7 = EXTRACT_SUBREG %5, %subreg.sub1
     S_NOP 0, implicit %5
     S_NOP 0, implicit %6
     S_NOP 0, implicit %7
 
     %8 = IMPLICIT_DEF
     %9 = EXTRACT_SUBREG %8, %subreg.sub1
     S_NOP 0, implicit %9
 
     %10 = EXTRACT_SUBREG undef %0, %subreg.sub2_sub3
     S_NOP 0, implicit %10
 ...
 ---
 # Check used lanes transfer; Includes checking for some special cases like
 # undef operands.
 # CHECK-LABEL: name: test2
 # CHECK: S_NOP 0, implicit-def dead %0
 # CHECK: S_NOP 0, implicit-def %1
 # CHECK: S_NOP 0, implicit-def %2
 # CHECK: %3 = REG_SEQUENCE undef %0, {{[0-9]+}}, %1, {{[0-9]+}}, %2, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %3:sub1
-# CHECK: S_NOP 0, implicit %3:sub3
+# CHECK: S_NOP 0, implicit %3.sub1
+# CHECK: S_NOP 0, implicit %3.sub3
 
 # CHECK: S_NOP 0, implicit-def %4
 # CHECK: S_NOP 0, implicit-def dead %5
 # CHECK: %6 = REG_SEQUENCE %4, {{[0-9]+}}, undef %5, {{[0-9]+}}
 # CHECK: S_NOP 0, implicit %6
 
 # CHECK: S_NOP 0, implicit-def dead %7
 # CHECK: S_NOP 0, implicit-def %8
 # CHECK: %9 = INSERT_SUBREG undef %7, %8, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %9:sub2
+# CHECK: S_NOP 0, implicit %9.sub2
 
 # CHECK: S_NOP 0, implicit-def %10
 # CHECK: S_NOP 0, implicit-def dead %11
 # CHECK: %12 = INSERT_SUBREG %10, undef %11, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %12:sub3
+# CHECK: S_NOP 0, implicit %12.sub3
 
 # CHECK: S_NOP 0, implicit-def %13
 # CHECK: S_NOP 0, implicit-def dead %14
 # CHECK: %15 = REG_SEQUENCE %13, {{[0-9]+}}, undef %14, {{[0-9]+}}
 # CHECK: %16 = EXTRACT_SUBREG %15, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %16:sub1
+# CHECK: S_NOP 0, implicit %16.sub1
 
 name: test2
 isSSA: true
 registers:
   - { id: 0, class: sreg_32 }
   - { id: 1, class: sreg_32 }
   - { id: 2, class: sreg_64 }
   - { id: 3, class: sreg_128 }
registers:
   - { id: 15, class: sreg_128 }
   - { id: 16, class: sreg_64 }
 body: |
   bb.0:
     S_NOP 0, implicit-def %0
     S_NOP 0, implicit-def %1
     S_NOP 0, implicit-def %2
     %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2_sub3
-    S_NOP 0, implicit %3:sub1
-    S_NOP 0, implicit %3:sub3
+    S_NOP 0, implicit %3.sub1
+    S_NOP 0, implicit %3.sub3
 
     S_NOP 0, implicit-def %4
     S_NOP 0, implicit-def %5
     %6 = REG_SEQUENCE %4, %subreg.sub0, undef %5, %subreg.sub1
     S_NOP 0, implicit %6
 
     S_NOP 0, implicit-def %7
     S_NOP 0, implicit-def %8
     %9 = INSERT_SUBREG %7, %8, %subreg.sub2_sub3
-    S_NOP 0, implicit %9:sub2
+    S_NOP 0, implicit %9.sub2
 
     S_NOP 0, implicit-def %10
     S_NOP 0, implicit-def %11
     %12 = INSERT_SUBREG %10, %11, %subreg.sub0_sub1
-    S_NOP 0, implicit %12:sub3
+    S_NOP 0, implicit %12.sub3
 
     S_NOP 0, implicit-def %13
     S_NOP 0, implicit-def %14
     %15 = REG_SEQUENCE %13, %subreg.sub0_sub1, %14, %subreg.sub2_sub3
     %16 = EXTRACT_SUBREG %15, %subreg.sub0_sub1
-    S_NOP 0, implicit %16:sub1
+    S_NOP 0, implicit %16.sub1
 ...
 ---
 # Check that copies to physregs use all lanes, copies from physregs define all
 # lanes. So we should not get a dead/undef flag here.
 # CHECK-LABEL: name: test3
 # CHECK: S_NOP 0, implicit-def %0
 # CHECK: %vcc = COPY %0
 # CHECK: %1 = COPY %vcc
bb.0:
     S_NOP 0, implicit %1
 ...
 ---
 # Check that unused inputs are marked as undef, even if the vreg itself is
 # used.
 # CHECK-LABEL: name: test5
 # CHECK: S_NOP 0, implicit-def %0
 # CHECK: %1 = REG_SEQUENCE undef %0, {{[0-9]+}}, %0, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %1:sub1
+# CHECK: S_NOP 0, implicit %1.sub1
 name: test5
 isSSA: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: sreg_32 }
   - { id: 1, class: sreg_64 }
 body: |
   bb.0:
     S_NOP 0, implicit-def %0
     %1 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1
-    S_NOP 0, implicit %1:sub1
+    S_NOP 0, implicit %1.sub1
 ...
 ---
 # Check "optimistic" dataflow fixpoint in phi-loops.
 # CHECK-LABEL: name: loop0
 # CHECK: bb.0:
 # CHECK: S_NOP 0, implicit-def %0
 # CHECK: S_NOP 0, implicit-def dead %1
 # CHECK: S_NOP 0, implicit-def dead %2
 # CHECK: %3 = REG_SEQUENCE %0, {{[0-9]+}}, undef %1, {{[0-9]+}}, undef %2, {{[0-9]+}}
 
 # CHECK: bb.1:
 # CHECK: %4 = PHI %3, %bb.0, %5, %bb.1
 
 # CHECK: bb.2:
-# CHECK:   S_NOP 0, implicit %4:sub0
-# CHECK:   S_NOP 0, implicit undef %4:sub3
+# CHECK:   S_NOP 0, implicit %4.sub0
+# CHECK:   S_NOP 0, implicit undef %4.sub3
 name: loop0
 isSSA: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: sreg_32 }
   - { id: 1, class: sreg_32 }
   - { id: 2, class: sreg_32 }
   - { id: 3, class: sreg_128 }
   - { id: 4, class: sreg_128 }
   - { id: 5, class: sreg_128 }
 body: |
   bb.0:
     successors: %bb.1
     S_NOP 0, implicit-def %0
     S_NOP 0, implicit-def %1
     S_NOP 0, implicit-def %2
     %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2
     S_BRANCH %bb.1
 
   bb.1:
     successors: %bb.1, %bb.2
     %4 = PHI %3, %bb.0, %5, %bb.1
 
     ; let's swiffle some lanes around for fun...
-    %5 = REG_SEQUENCE %4:sub0, %subreg.sub0, %4:sub2, %subreg.sub1, %4:sub1, %subreg.sub2, %4:sub3, %subreg.sub3
+    %5 = REG_SEQUENCE %4.sub0, %subreg.sub0, %4.sub2, %subreg.sub1, %4.sub1, %subreg.sub2, %4.sub3, %subreg.sub3
 
     S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
     S_BRANCH %bb.2
 
   bb.2:
-    S_NOP 0, implicit %4:sub0
-    S_NOP 0, implicit %4:sub3
+    S_NOP 0, implicit %4.sub0
+    S_NOP 0, implicit %4.sub3
 ...
 ---
 # Check a loop that needs to be traversed multiple times to reach the fixpoint
 # for the used lanes. The example reads sub3 lane at the end, however with each
 # loop iteration we should get 1 more lane marked as we cycles the sublanes
 # along. Sublanes sub0, sub1 and sub3 are rotate in the loop so only sub2
 # should be dead.
 # CHECK-LABEL: name: loop1
 # CHECK: bb.0:
 # CHECK: S_NOP 0, implicit-def %0
 # CHECK: S_NOP 0, implicit-def %1
 # CHECK: S_NOP 0, implicit-def dead %2
 # CHECK: S_NOP 0, implicit-def %3
 # CHECK: %4 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}}, %3, {{[0-9]+}}
 
 # CHECK: bb.1:
 # CHECK: %5 = PHI %4, %bb.0, %6, %bb.1
 
-# CHECK: %6 = REG_SEQUENCE %5:sub1, {{[0-9]+}}, %5:sub3, {{[0-9]+}}, undef %5:sub2, {{[0-9]+}}, %5:sub0, {{[0-9]+}}
+# CHECK: %6 = REG_SEQUENCE %5.sub1, {{[0-9]+}}, %5.sub3, {{[0-9]+}}, undef %5.sub2, {{[0-9]+}}, %5.sub0, {{[0-9]+}}
 
 # CHECK: bb.2:
-# CHECK:   S_NOP 0, implicit %6:sub3
+# CHECK:   S_NOP 0, implicit %6.sub3
 name: loop1
 isSSA: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: sreg_32 }
   - { id: 1, class: sreg_32 }
   - { id: 2, class: sreg_32 }
   - { id: 3, class: sreg_32 }
bb.0:
     %4 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
     S_BRANCH %bb.1
 
   bb.1:
     successors: %bb.1, %bb.2
     %5 = PHI %4, %bb.0, %6, %bb.1
 
     ; rotate lanes, but skip sub2 lane...
-    %6 = REG_SEQUENCE %5:sub1, %subreg.sub0, %5:sub3, %subreg.sub1, %5:sub2, %subreg.sub2, %5:sub0, %subreg.sub3
+    %6 = REG_SEQUENCE %5.sub1, %subreg.sub0, %5.sub3, %subreg.sub1, %5.sub2, %subreg.sub2, %5.sub0, %subreg.sub3
 
     S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
     S_BRANCH %bb.2
 
   bb.2:
-    S_NOP 0, implicit %6:sub3
+    S_NOP 0, implicit %6.sub3
 ...
 ---
 # Similar to loop1 test, but check for fixpoint of defined lanes.
 # Lanes are rotate between sub0, sub2, sub3 so only sub1 should be dead/undef.
 # CHECK-LABEL: name: loop2
 # CHECK: bb.0:
 # CHECK: S_NOP 0, implicit-def %0
 # CHECK: %1 = REG_SEQUENCE %0, {{[0-9]+}}
 
 # CHECK: bb.1:
 # CHECK: %2 = PHI %1, %bb.0, %3, %bb.1
 
-# CHECK: %3 = REG_SEQUENCE %2:sub3, {{[0-9]+}}, undef %2:sub1, {{[0-9]+}}, %2:sub0, {{[0-9]+}}, %2:sub2, {{[0-9]+}}
+# CHECK: %3 = REG_SEQUENCE %2.sub3, {{[0-9]+}}, undef %2.sub1, {{[0-9]+}}, %2.sub0, {{[0-9]+}}, %2.sub2, {{[0-9]+}}
 
 # CHECK: bb.2:
-# CHECK:   S_NOP 0, implicit %2:sub0
-# CHECK:   S_NOP 0, implicit undef %2:sub1
-# CHECK:   S_NOP 0, implicit %2:sub2
-# CHECK:   S_NOP 0, implicit %2:sub3
+# CHECK:   S_NOP 0, implicit %2.sub0
+# CHECK:   S_NOP 0, implicit undef %2.sub1
+# CHECK:   S_NOP 0, implicit %2.sub2
+# CHECK:   S_NOP 0, implicit %2.sub3
 name: loop2
 isSSA: true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: sreg_32 }
   - { id: 1, class: sreg_128 }
   - { id: 2, class: sreg_128 }
   - { id: 3, class: sreg_128 }
 body: |
   bb.0:
     successors: %bb.1
     S_NOP 0, implicit-def %0
     %1 = REG_SEQUENCE %0, %subreg.sub0
     S_BRANCH %bb.1
 
   bb.1:
     successors: %bb.1, %bb.2
     %2 = PHI %1, %bb.0, %3, %bb.1
 
     ; rotate subreg lanes, skipping sub1
-    %3 = REG_SEQUENCE %2:sub3, %subreg.sub0, %2:sub1, %subreg.sub1, %2:sub0, %subreg.sub2, %2:sub2, %subreg.sub3
+    %3 = REG_SEQUENCE %2.sub3, %subreg.sub0, %2.sub1, %subreg.sub1, %2.sub0, %subreg.sub2, %2.sub2, %subreg.sub3
 
     S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
     S_BRANCH %bb.2
 
   bb.2:
-    S_NOP 0, implicit %2:sub0
-    S_NOP 0, implicit undef %2:sub1
-    S_NOP 0, implicit %2:sub2
-    S_NOP 0, implicit %2:sub3
+    S_NOP 0, implicit %2.sub0
+    S_NOP 0, implicit undef %2.sub1
+    S_NOP 0, implicit %2.sub2
+    S_NOP 0, implicit %2.sub3
 ...

llvm/trunk/test/CodeGen/AMDGPU/liveness.mir

 ...
 ---
 name: test0
 registers:
   - { id: 0, class: sreg_64 }
 body: |
   bb.0:
     successors: %bb.1, %bb.2
-    S_NOP 0, implicit-def undef %0:sub0
+    S_NOP 0, implicit-def undef %0.sub0
     S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
     S_BRANCH %bb.2
 
   bb.1:
     successors: %bb.2
-    S_NOP 0, implicit-def %0:sub1
-    S_NOP 0, implicit %0:sub1
+    S_NOP 0, implicit-def %0.sub1
+    S_NOP 0, implicit %0.sub1
     S_BRANCH %bb.2
 
   bb.2:
-    S_NOP 0, implicit %0:sub0
+    S_NOP 0, implicit %0.sub0
 ...

llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs.mir

 # RUN: llc -march=amdgcn -run-pass rename-independent-subregs -o - %s | FileCheck %s
 --- |
   define void @test0() { ret void }
 ...
 ---
 # In the test below we have two independent def+use pairs of subregister1 which
 # can be moved to a new virtual register. The third def of sub1 however is used
 # in combination with sub0 and needs to stay with the original vreg.
 # CHECK-LABEL: name: test0
-# CHECK: S_NOP 0, implicit-def undef %0:sub0
-# CHECK: S_NOP 0, implicit-def undef %2:sub1
-# CHECK: S_NOP 0, implicit %2:sub1
-# CHECK: S_NOP 0, implicit-def undef %1:sub1
-# CHECK: S_NOP 0, implicit %1:sub1
-# CHECK: S_NOP 0, implicit-def %0:sub1
+# CHECK: S_NOP 0, implicit-def undef %0.sub0
+# CHECK: S_NOP 0, implicit-def undef %2.sub1
+# CHECK: S_NOP 0, implicit %2.sub1
+# CHECK: S_NOP 0, implicit-def undef %1.sub1
+# CHECK: S_NOP 0, implicit %1.sub1
+# CHECK: S_NOP 0, implicit-def %0.sub1
 # CHECK: S_NOP 0, implicit %0
 name: test0
 isSSA: true
 registers:
   - { id: 0, class: sreg_128 }
 body: |
   bb.0:
-    S_NOP 0, implicit-def undef %0:sub0
-    S_NOP 0, implicit-def %0:sub1
-    S_NOP 0, implicit %0:sub1
-    S_NOP 0, implicit-def %0:sub1
-    S_NOP 0, implicit %0:sub1
-    S_NOP 0, implicit-def %0:sub1
+    S_NOP 0, implicit-def undef %0.sub0
+    S_NOP 0, implicit-def %0.sub1
+    S_NOP 0, implicit %0.sub1
+    S_NOP 0, implicit-def %0.sub1
+    S_NOP 0, implicit %0.sub1
+    S_NOP 0, implicit-def %0.sub1
     S_NOP 0, implicit %0
 ...

llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir

 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr8 }
   - { id: 2, class: gr8 }
 body: |
   bb.0.entry:
     %0 = COPY %edi
-    ; CHECK: [[@LINE+1]]:20: expected a subregister index after ':'
-    %1 = COPY %0 : 42
+    ; CHECK: [[@LINE+1]]:20: expected a subregister index after '.'
+    %1 = COPY %0 . 42
     %2 = AND8ri %1, 1, implicit-def %eflags
     %al = COPY %2
     RETQ %al
 ...

llvm/trunk/test/CodeGen/MIR/X86/subreg-on-physreg.mir

 # RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
 # This test ensures that an error is reported for subreg index on a physreg.
 --- |
   define void @t() { ret void }
 ...
 ---
 name: t
 body: |
   bb.0:
     ; CHECK: [[@LINE+1]]:19: subregister index expects a virtual register
-    %eax:sub_8bit = COPY %bl
+    %eax.sub_8bit = COPY %bl
 ...

llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir

 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr8 }
   - { id: 2, class: gr8 }
 body: |
   bb.0.entry:
     liveins: %edi
     ; CHECK:      %0 = COPY %edi
-    ; CHECK-NEXT: %1 = COPY %0:sub_8bit
+    ; CHECK-NEXT: %1 = COPY %0.sub_8bit
     %0 = COPY %edi
-    %1 = COPY %0:sub_8bit
+    %1 = COPY %0.sub_8bit
     %2 = AND8ri %1, 1, implicit-def %eflags
     %al = COPY %2
     RETQ %al
 ...
 

llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir

 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr8 }
   - { id: 2, class: gr8 }
 body: |
   bb.0.entry:
     %0 = COPY %edi
     ; CHECK: [[@LINE+1]]:18: use of unknown subregister index 'bit8'
-    %1 = COPY %0:bit8
+    %1 = COPY %0.bit8
     %2 = AND8ri %1, 1, implicit-def %eflags
     %al = COPY %2
     RETQ %al
 ...

llvm/trunk/unittests/MI/LiveIntervalTest.cpp

TEST(LiveIntervalTest, SubRegMoveDown) {
   // movement of the form 32->150 in a liverange [16, 32) [100,200).
   liveIntervalTest(
 "    successors: %bb.1, %bb.2\n"
 "    %0 = IMPLICIT_DEF\n"
 "    S_CBRANCH_VCCNZ %bb.2, implicit undef %vcc\n"
 "    S_BRANCH %bb.1\n"
 "  bb.2:\n"
 "    successors: %bb.1\n"
-"    S_NOP 0, implicit %0:sub0\n"
-"    S_NOP 0, implicit %0:sub1\n"
+"    S_NOP 0, implicit %0.sub0\n"
+"    S_NOP 0, implicit %0.sub1\n"
 "    S_NOP 0\n"
-"    undef %0:sub0 = IMPLICIT_DEF\n"
-"    %0:sub1 = IMPLICIT_DEF\n"
+"    undef %0.sub0 = IMPLICIT_DEF\n"
+"    %0.sub1 = IMPLICIT_DEF\n"
 "  bb.1:\n"
 "    S_NOP 0, implicit %0\n",
   [](MachineFunction &MF, LiveIntervals &LIS) {
     // Scheduler behaviour: Clear def,read-undef flag and move.
     MachineInstr &MI = getMI(MF, 3, /*BlockNum=*/1);
     MI.getOperand(0).setIsUndef(false);
     testHandleMove(MF, LIS, 1, 4, /*BlockNum=*/1);
   });
 }
 
 int main(int argc, char **argv) {
   ::testing::InitGoogleTest(&argc, argv);
   initLLVM();
   return RUN_ALL_TESTS();
 }