MIRParser: Use dot instead of colon to mark subregisters

[MatzeB]

Summary

Change the syntax to use %0.sub8 to denote a subregister.

This seems like a more natural fit to denote subregisters; I also plan
to introduce a new ":classname" syntax in upcoming patches to denote the
register class of a vreg.

Note that this commit disallows plain identifiers to start with a '.'
character. This shouldn't affect anything as external names/IR
references are all prefixed with '$'/'%', plain identifiers are only
used for instruction names, register mask names and subreg indexes which should not start with a dot.

[qcolombet]

LGTM.

lib/CodeGen/MIRParser/MILexer.h

enum TokenKind {
     Newline,
 
     // Tokens with no info.
     comma,
     equal,
     underscore,
     colon,
     coloncolon,
+    dot,
     exclaim,
     lparen,
     rparen,
     lbrace,
     rbrace,
     plus,
     minus,
     less,

lib/CodeGen/MIRParser/MILexer.cpp

return StringSwitch<MIToken::TokenKind>(Identifier)
       .Case("address-taken", MIToken::kw_address_taken)
       .Case("landing-pad", MIToken::kw_landing_pad)
       .Case("liveins", MIToken::kw_liveins)
       .Case("successors", MIToken::kw_successors)
       .Default(MIToken::Identifier);
 }
 
 static Cursor maybeLexIdentifier(Cursor C, MIToken &Token) {
-  if (!isalpha(C.peek()) && C.peek() != '_' && C.peek() != '.')
+  if (!isalpha(C.peek()) && C.peek() != '_')
     return None;
   auto Range = C;
   while (isIdentifierChar(C.peek()))
     C.advance();
   auto Identifier = Range.upto(C);
   Token.reset(getIdentifierKind(Identifier), Identifier)
       .setStringValue(Identifier);
   return C;
static Cursor lexVirtualRegister(Cursor C, MIToken &Token) {
   auto NumberRange = C;
   while (isdigit(C.peek()))
     C.advance();
   Token.reset(MIToken::VirtualRegister, Range.upto(C))
       .setIntegerValue(APSInt(NumberRange.upto(C)));
   return C;
 }
 
+/// Returns true for a character allowed in a register name.
+static bool isRegisterChar(char C) {
+  return isIdentifierChar(C) && C != '.';
+}
+
 static Cursor maybeLexRegister(Cursor C, MIToken &Token) {
   if (C.peek() != '%')
     return None;
   if (isdigit(C.peek(1)))
     return lexVirtualRegister(C, Token);
   auto Range = C;
   C.advance(); // Skip '%'
-  while (isIdentifierChar(C.peek()))
+  while (isRegisterChar(C.peek()))
     C.advance();
   Token.reset(MIToken::NamedRegister, Range.upto(C))
       .setStringValue(Range.upto(C).drop_front(1)); // Drop the '%'
   return C;
 }
 
 static Cursor maybeLexGlobalValue(Cursor C, MIToken &Token,
                                   ErrorCallbackType ErrorCallback) {
ErrorCallback(Token.location(),
                   "use of unknown metadata keyword '" + StrVal + "'");
   return C;
 }
 
 static MIToken::TokenKind symbolToken(char C) {
   switch (C) {
   case ',':
     return MIToken::comma;
+  case '.':
+    return MIToken::dot;
   case '=':
     return MIToken::equal;
   case ':':
     return MIToken::colon;
   case '(':
     return MIToken::lparen;
   case ')':
     return MIToken::rparen;

lib/CodeGen/MIRParser/MIParser.cpp

if (OldFlags == Flags)
     // We know that the same flag is specified more than once when the flags
     // weren't modified.
     return error("duplicate '" + Token.stringValue() + "' register flag");
   lex();
   return false;
 }
 
 bool MIParser::parseSubRegisterIndex(unsigned &SubReg) {
-  assert(Token.is(MIToken::colon));
+  assert(Token.is(MIToken::dot));
   lex();
   if (Token.isNot(MIToken::Identifier))
-    return error("expected a subregister index after ':'");
+    return error("expected a subregister index after '.'");
   auto Name = Token.stringValue();
   SubReg = getSubRegIndex(Name);
   if (!SubReg)
     return error(Twine("use of unknown subregister index '") + Name + "'");
   lex();
   return false;
 }
 
if (parseRegisterFlag(Flags))
       return true;
   }
   if (!Token.isRegister())
     return error("expected a register after register flags");
   if (parseRegister(Reg))
     return true;
   lex();
   unsigned SubReg = 0;
-  if (Token.is(MIToken::colon)) {
+  if (Token.is(MIToken::dot)) {
     if (parseSubRegisterIndex(SubReg))
       return true;
   }
   if ((Flags & RegState::Define) == 0) {
     if (consumeIfPresent(MIToken::lparen)) {
       unsigned Idx;
       if (parseRegisterTiedDefIndex(Idx))
         return true;

lib/CodeGen/MIRPrinter.cpp

if (Op.isUndef())
       OS << "undef ";
     if (Op.isEarlyClobber())
       OS << "early-clobber ";
     if (Op.isDebug())
       OS << "debug-use ";
     printReg(Op.getReg(), OS, TRI);
     // Print the sub register.
     if (Op.getSubReg() != 0)
-      OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());
+      OS << '.' << TRI->getSubRegIndexName(Op.getSubReg());
     if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
       OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(I) << ")";
     assert((!IsDef || MRI) && "for IsDef, MRI must be provided");
     if (IsDef && MRI->getSize(Op.getReg()))
       OS << '(' << MRI->getSize(Op.getReg()) << ')';
     break;
   case MachineOperand::MO_Immediate:
     OS << Op.getImm();

test/CodeGen/MIR/X86/expected-subregister-after-colon.mir

 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr8 }
   - { id: 2, class: gr8 }
 body: |
   bb.0.entry:
     %0 = COPY %edi
-    ; CHECK: [[@LINE+1]]:20: expected a subregister index after ':'
-    %1 = COPY %0 : 42
+    ; CHECK: [[@LINE+1]]:20: expected a subregister index after '.'
+    %1 = COPY %0 . 42
     %2 = AND8ri %1, 1, implicit-def %eflags
     %al = COPY %2
     RETQ %al
 ...

test/CodeGen/MIR/X86/subregister-operands.mir

 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr8 }
   - { id: 2, class: gr8 }
 body: |
   bb.0.entry:
     liveins: %edi
     ; CHECK:      %0 = COPY %edi
-    ; CHECK-NEXT: %1 = COPY %0:sub_8bit
+    ; CHECK-NEXT: %1 = COPY %0.sub_8bit
     %0 = COPY %edi
-    %1 = COPY %0:sub_8bit
+    %1 = COPY %0.sub_8bit
     %2 = AND8ri %1, 1, implicit-def %eflags
     %al = COPY %2
     RETQ %al
 ...
 

test/CodeGen/MIR/X86/unknown-subregister-index.mir

 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr8 }
   - { id: 2, class: gr8 }
 body: |
   bb.0.entry:
     %0 = COPY %edi
     ; CHECK: [[@LINE+1]]:18: use of unknown subregister index 'bit8'
-    %1 = COPY %0:bit8
+    %1 = COPY %0.bit8
     %2 = AND8ri %1, 1, implicit-def %eflags
     %al = COPY %2
     RETQ %al
 ...