This is an archive of the discontinued LLVM Phabricator instance.

[ARM] Enable "PC" be access via named register intrinsic
Needs ReviewPublic

Authored by weimingz on Jul 11 2016, 6:41 PM.

Reviewers

mgrang
t.p.northover

Summary

Enable register "pc" be accessed via named register intrinsics

weimingz retitled this revision from to Let "PC" be access via named register intrinsic.

weimingz updated this object.

weimingz set the repository for this revision to rL LLVM.

weimingz added a subscriber: llvm-commits.

Path

Size

lib/

Target/

ARM/

1 line

test/

CodeGen/

ARM/

21 lines

	Show First 20 Lines • Show All 4,359 Lines • ▼ Show 20 Lines
	}			}

	// FIXME? Maybe this could be a TableGen attribute on some registers and			// FIXME? Maybe this could be a TableGen attribute on some registers and
	// this table could be generated automatically from RegInfo.			// this table could be generated automatically from RegInfo.
	unsigned ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,			unsigned ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
	SelectionDAG &DAG) const {			SelectionDAG &DAG) const {
	unsigned Reg = StringSwitch<unsigned>(RegName)			unsigned Reg = StringSwitch<unsigned>(RegName)
	.Case("sp", ARM::SP)			.Case("sp", ARM::SP)
				.Case("pc", ARM::PC)
	.Default(0);			.Default(0);
	if (Reg)			if (Reg)
	return Reg;			return Reg;
	report_fatal_error(Twine("Invalid register name \""			report_fatal_error(Twine("Invalid register name \""
	+ StringRef(RegName) + "\"."));			+ StringRef(RegName) + "\"."));
	}			}

	// Result is 64 bit value so split into two 32 bit values and return as a			// Result is 64 bit value so split into two 32 bit values and return as a
	▲ Show 20 Lines • Show All 8,484 Lines • Show Last 20 Lines

				; RUN: llc < %s -mtriple=arm-apple-darwin 2>&1 \| FileCheck %s
				; RUN: llc < %s -mtriple=arm-linux-gnueabi 2>&1 \| FileCheck %s

				define i32 @get_stack() nounwind {
				entry:
				; CHECK: mov r0, sp
				%sp = call i32 @llvm.read_register.i32(metadata !0)
				ret i32 %sp
				}

				define i32 @get_pc() nounwind {
				entry:
				; CHECK: mov r0, pc
				%sp = call i32 @llvm.read_register.i32(metadata !1)
				ret i32 %sp
				}

				declare i32 @llvm.read_register.i32(metadata) nounwind

				!0 = !{!"sp\00"}
				!1 = !{!"pc\00"}