[ARM, AArch64] Adds builtins to get current SP and PC

[weimingz]

Summary

This patch implements builtin_arm_current_sp and builtin_arm_current_pc.
__builtin_arm_current_sp is also implemented for AArch64

[weimingz]

Needs http://reviews.llvm.org/D22253

[rengolin]

Hi Weiming,

We've discussed about creating builtins when I added support for named registers and the consensus was that, since there is already a way to access them, there is no point in adding a new builtin.

cheers,
--renato

[t.p.northover]

I agree with Renato too.

It seems like, as a compiler, we can provide virtually no guarantees about the value of __builtin_arm_current_pc: it's not necessarily in the PC-range of the dynamically innermost frame (inlining); it's not necessarily even in the callstack at all (you actually get PC+8 or PC+4).

About the only feasible use-case is a some kind of panic/abort implementation best-effort. And at that point you'll want r0-r14 as well.

Tim.

[mgrang]

Hi Tim/Renato,

On a similar note, I have a patch which adds the breakpoint intrinsic (for ARM and Thumb):
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0491c/CJAHBCFH.html

Could you please let me know if this is something which the community would like to support. I can then push my patch.

Here are two other intrinsics which I wanted to implement:
enable_irq: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0472m/chr1359124996163.html
disable_irq: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0472m/chr1359125001077.html

The use case for these intrinsics is a customer who makes calls to __builtin_arm_breakpoint (and others) in their code base. Currently they compile with ARMCC, but LLVM does not have these intrinsics. So porting the code to build with LLVM becomes a hassle.
To facilitate customers to switch to LLVM we wanted to implement these intrinsics.

Thanks,
Mandeep

[rengolin]

In D22254#481972, @mgrang wrote:

Hi Tim/Renato,

On a similar note, I have a patch which adds the breakpoint intrinsic (for ARM and Thumb):
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0491c/CJAHBCFH.html

Hi Mandeep,

I don't think we should be implementing old ARMCC intrinsics either. GCC doesn't, especially since most of them are easy to do with one line inline assembly snippets.

Those intrinsics are not covered by the ACLE (mentioned, but not defined), which reinforces the notion that we shouldn't be doing anyway.

cheers,
--renato

[mgrang]

Thanks Renato for your comments. I guess I will not upstream my patches then.

--Mandeep

include/clang/Basic/BuiltinsAArch64.def

 // System Registers
 BUILTIN(__builtin_arm_rsr, "UicC*", "nc")
 BUILTIN(__builtin_arm_rsr64, "LUicC*", "nc")
 BUILTIN(__builtin_arm_rsrp, "v*cC*", "nc")
 BUILTIN(__builtin_arm_wsr, "vcC*Ui", "nc")
 BUILTIN(__builtin_arm_wsr64, "vcC*LUi", "nc")
 BUILTIN(__builtin_arm_wsrp, "vcC*vC*", "nc")
 
+// Special registers
+BUILTIN(__builtin_arm_current_sp, "LUi", "nc")
+
 #undef BUILTIN

include/clang/Basic/BuiltinsARM.def

 // System registers (ACLE)
 BUILTIN(__builtin_arm_rsr, "UicC*", "nc")
 BUILTIN(__builtin_arm_rsr64, "LLUicC*", "nc")
 BUILTIN(__builtin_arm_rsrp, "v*cC*", "nc")
 BUILTIN(__builtin_arm_wsr, "vcC*Ui", "nc")
 BUILTIN(__builtin_arm_wsr64, "vcC*LLUi", "nc")
 BUILTIN(__builtin_arm_wsrp, "vcC*vC*", "nc")
 
+// Special registers
+BUILTIN(__builtin_arm_current_sp, "Ui", "nc")
+BUILTIN(__builtin_arm_current_pc, "Ui", "nc")
+
 // MSVC
 LANGBUILTIN(__emit, "vIUiC", "", ALL_MS_LANGUAGES)
 
 LANGBUILTIN(__yield, "v", "", ALL_MS_LANGUAGES)
 LANGBUILTIN(__wfe, "v", "", ALL_MS_LANGUAGES)
 LANGBUILTIN(__wfi, "v", "", ALL_MS_LANGUAGES)
 LANGBUILTIN(__sev, "v", "", ALL_MS_LANGUAGES)
 LANGBUILTIN(__sevl, "v", "", ALL_MS_LANGUAGES)

lib/CodeGen/CGBuiltin.cpp

if (CRCIntrinsicID != Intrinsic::not_intrinsic) {
     }
   }
 
   if (BuiltinID == ARM::BI__builtin_arm_rsr ||
       BuiltinID == ARM::BI__builtin_arm_rsr64 ||
       BuiltinID == ARM::BI__builtin_arm_rsrp ||
       BuiltinID == ARM::BI__builtin_arm_wsr ||
       BuiltinID == ARM::BI__builtin_arm_wsr64 ||
-      BuiltinID == ARM::BI__builtin_arm_wsrp) {
+      BuiltinID == ARM::BI__builtin_arm_wsrp ||
+      BuiltinID == ARM::BI__builtin_arm_current_sp ||
+      BuiltinID == ARM::BI__builtin_arm_current_pc) {
 
     bool IsRead = BuiltinID == ARM::BI__builtin_arm_rsr ||
                   BuiltinID == ARM::BI__builtin_arm_rsr64 ||
-                  BuiltinID == ARM::BI__builtin_arm_rsrp;
+                  BuiltinID == ARM::BI__builtin_arm_rsrp ||
+                  BuiltinID == ARM::BI__builtin_arm_current_sp ||
+                  BuiltinID == ARM::BI__builtin_arm_current_pc;
 
     bool IsPointerBuiltin = BuiltinID == ARM::BI__builtin_arm_rsrp ||
                             BuiltinID == ARM::BI__builtin_arm_wsrp;
 
     bool Is64Bit = BuiltinID == ARM::BI__builtin_arm_rsr64 ||
                    BuiltinID == ARM::BI__builtin_arm_wsr64;
 
     llvm::Type *ValueType;
     llvm::Type *RegisterType;
     if (IsPointerBuiltin) {
       ValueType = VoidPtrTy;
       RegisterType = Int32Ty;
     } else if (Is64Bit) {
       ValueType = RegisterType = Int64Ty;
     } else {
       ValueType = RegisterType = Int32Ty;
     }
-
-    return EmitSpecialRegisterBuiltin(*this, E, RegisterType, ValueType, IsRead);
+    std::string SysReg = "";
+    if (BuiltinID == ARM::BI__builtin_arm_current_sp)
+      SysReg = "sp";
+    else if (BuiltinID == ARM::BI__builtin_arm_current_pc)
+      SysReg = "pc";
+    return EmitSpecialRegisterBuiltin(*this, E, RegisterType, ValueType, IsRead,
+                                      SysReg);
   }
 
   // Find out if any arguments are required to be integer constant
   // expressions.
   unsigned ICEArguments = 0;
   ASTContext::GetBuiltinTypeError Error;
   getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
   assert(Error == ASTContext::GE_None && "Should not codegen an error");
if (CRCIntrinsicID != Intrinsic::not_intrinsic) {
     return Builder.CreateCall(F, {Arg0, Arg1});
   }
 
   if (BuiltinID == AArch64::BI__builtin_arm_rsr ||
       BuiltinID == AArch64::BI__builtin_arm_rsr64 ||
       BuiltinID == AArch64::BI__builtin_arm_rsrp ||
       BuiltinID == AArch64::BI__builtin_arm_wsr ||
       BuiltinID == AArch64::BI__builtin_arm_wsr64 ||
-      BuiltinID == AArch64::BI__builtin_arm_wsrp) {
+      BuiltinID == AArch64::BI__builtin_arm_wsrp ||
+      BuiltinID == AArch64::BI__builtin_arm_current_sp) {
 
     bool IsRead = BuiltinID == AArch64::BI__builtin_arm_rsr ||
                   BuiltinID == AArch64::BI__builtin_arm_rsr64 ||
-                  BuiltinID == AArch64::BI__builtin_arm_rsrp;
+                  BuiltinID == AArch64::BI__builtin_arm_rsrp ||
+                  BuiltinID == AArch64::BI__builtin_arm_current_sp;
 
     bool IsPointerBuiltin = BuiltinID == AArch64::BI__builtin_arm_rsrp ||
                             BuiltinID == AArch64::BI__builtin_arm_wsrp;
 
     bool Is64Bit = BuiltinID != AArch64::BI__builtin_arm_rsr &&
                    BuiltinID != AArch64::BI__builtin_arm_wsr;
 
     llvm::Type *ValueType;
     llvm::Type *RegisterType = Int64Ty;
     if (IsPointerBuiltin) {
       ValueType = VoidPtrTy;
     } else if (Is64Bit) {
       ValueType = Int64Ty;
     } else {
       ValueType = Int32Ty;
     }
-
-    return EmitSpecialRegisterBuiltin(*this, E, RegisterType, ValueType, IsRead);
+    std::string SysReg = "";
+    if (BuiltinID == AArch64::BI__builtin_arm_current_sp)
+      SysReg = "sp";
+    return EmitSpecialRegisterBuiltin(*this, E, RegisterType, ValueType, IsRead,
+                                      SysReg);
   }
 
   // Find out if any arguments are required to be integer constant
   // expressions.
   unsigned ICEArguments = 0;
   ASTContext::GetBuiltinTypeError Error;
   getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
   assert(Error == ASTContext::GE_None && "Should not codegen an error");

test/CodeGen/builtins-arm.c

 
 void *rsrp() {
   // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i32 @llvm.read_register.i32(metadata ![[M2:.*]])
   // CHECK-NEXT: [[V1:[%A-Za-z0-9.]+]] = inttoptr i32 [[V0]] to i8*
   // CHECK-NEXT: ret i8* [[V1]]
   return __builtin_arm_rsrp("sysreg");
 }
 
+unsigned __current_sp() {
+  // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i32 @llvm.read_register.i32(metadata ![[M3:.*]])
+  // CHECK-NEXT: ret i32 [[V0]]
+  return __builtin_arm_current_sp();
+}
+
+unsigned __current_pc() {
+  // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i32 @llvm.read_register.i32(metadata ![[M4:.*]])
+  // CHECK-NEXT: ret i32 [[V0]]
+  return __builtin_arm_current_pc();
+}
+
 void wsr(unsigned v) {
   // CHECK: call void @llvm.write_register.i32(metadata ![[M0]], i32 %v)
   __builtin_arm_wsr("cp1:2:c3:c4:5", v);
 }
 
 void wsr64(unsigned long long v) {
   // CHECK: call void @llvm.write_register.i64(metadata ![[M1]], i64 %v)
   __builtin_arm_wsr64("cp1:2:c3", v);
 }
 
 void wsrp(void *v) {
   // CHECK: [[V0:[%A-Za-z0-9.]+]] = ptrtoint i8* %v to i32
   // CHECK-NEXT: call void @llvm.write_register.i32(metadata ![[M2]], i32 [[V0]])
   __builtin_arm_wsrp("sysreg", v);
 }
 
 // CHECK: ![[M0]] = !{!"cp1:2:c3:c4:5"}
 // CHECK: ![[M1]] = !{!"cp1:2:c3"}
 // CHECK: ![[M2]] = !{!"sysreg"}
+// CHECK: ![[M3]] = !{!"sp"}
+// CHECK: ![[M4]] = !{!"pc"}

test/CodeGen/builtins-arm64.c

 }
 
 void wsrp(void *v) {
   // CHECK: [[V0:[%A-Za-z0-9.]+]] = ptrtoint i8* %v to i64
   // CHECK-NEXT: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 [[V0]])
   __builtin_arm_wsrp("1:2:3:4:5", v);
 }
 
+unsigned long __current_sp() {
+  // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i64 @llvm.read_register.i64(metadata ![[M1:.*]])
+  // CHECK-NEXT: ret i64 [[V0]]
+  return __builtin_arm_current_sp();
+}
 // CHECK: ![[M0]] = !{!"1:2:3:4:5"}
+// CHECK: ![[M1]] = !{!"sp"}