AMDGPU: Move si_mask_branch register operand to be a use

[nhaehnle]

LGTM

[arsenm]

r274818

lib/Target/AMDGPU/AMDGPUMCInstLower.cpp

void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
   } else {
     // We don't want SI_MASK_BRANCH/SI_RETURN encoded. They are placeholder
     // terminator instructions and should only be printed as comments.
     if (MI->getOpcode() == AMDGPU::SI_MASK_BRANCH) {
       if (isVerbose()) {
         SmallVector<char, 16> BBStr;
         raw_svector_ostream Str(BBStr);
 
-        const MachineBasicBlock *MBB = MI->getOperand(1).getMBB();
+        const MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
         const MCSymbolRefExpr *Expr
           = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
         Expr->print(Str, MAI);
         OutStreamer->emitRawComment(" mask branch " + BBStr);
       }
 
       return;
     }

lib/Target/AMDGPU/SIInstructions.td

 // SI pseudo instructions. These are used by the CFG structurizer pass
 // and should be lowered to ISA instructions prior to codegen.
 
 let hasSideEffects = 1, isPseudo = 1, isCodeGenOnly = 1 in {
 
 // Dummy terminator instruction to use after control flow instructions
 // replaced with exec mask operations.
 def SI_MASK_BRANCH : InstSI <
-  (outs SReg_64:$dst), (ins brtarget:$target)> {
+  (outs), (ins brtarget:$target, SReg_64:$dst)> {
   let isBranch = 1;
   let isTerminator = 1;
   let isBarrier = 1;
   let SALU = 1;
 }
 
 let Uses = [EXEC], Defs = [EXEC] in {
 

lib/Target/AMDGPU/SILowerControlFlow.cpp

void SILowerControlFlow::If(MachineInstr &MI) {
 
   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
           .addReg(AMDGPU::EXEC)
           .addReg(Reg);
 
   Skip(MI, MI.getOperand(2));
 
   // Insert a pseudo terminator to help keep the verifier happy.
-  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH), Reg)
-    .addOperand(MI.getOperand(2));
+  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
+    .addOperand(MI.getOperand(2))
+    .addReg(Reg);
 
   MI.eraseFromParent();
 }
 
 void SILowerControlFlow::Else(MachineInstr &MI, bool ExecModified) {
   MachineBasicBlock &MBB = *MI.getParent();
   DebugLoc DL = MI.getDebugLoc();
   unsigned Dst = MI.getOperand(0).getReg();
void SILowerControlFlow::Else(MachineInstr &MI, bool ExecModified) {
 
   BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
           .addReg(AMDGPU::EXEC)
           .addReg(Dst);
 
   Skip(MI, MI.getOperand(2));
 
   // Insert a pseudo terminator to help keep the verifier happy.
-  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH), Dst)
-    .addOperand(MI.getOperand(2));
+  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
+    .addOperand(MI.getOperand(2))
+    .addReg(Dst);
 
   MI.eraseFromParent();
 }
 
 void SILowerControlFlow::Break(MachineInstr &MI) {
   MachineBasicBlock &MBB = *MI.getParent();
   DebugLoc DL = MI.getDebugLoc();