[AMDGPU] Assembler: Fix parsing error with floating-point literals passed to integer instructions

[SamWot]

Summary

Previous changes for sext() modifier introduced regression: when you pass fp literal to integer instruction assembler was returning error. Now it just converts that float to binary representation.

[SamWot]

Removed strange X86 changes from previous diff.

[vpykhtin]

LGTM.

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

if (getLexer().getKind() == AsmToken::Identifier && Parser.getTok().getString() == "sext") {
     Parser.Lex();
   }
 
   auto Res = parseRegOrImm(Operands);
   if (Res != MatchOperand_Success) {
     return Res;
   }
 
-  AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
-  if (Op.isImm() && Op.Imm.IsFPImm) {
-    Error(Parser.getTok().getLoc(), "floating point operands not allowed with sext() modifier");
-    return MatchOperand_ParseFail;
-  }
-
   AMDGPUOperand::Modifiers Mods = {false, false, false};
   if (Sext) {
     if (getLexer().isNot(AsmToken::RParen)) {
       Error(Parser.getTok().getLoc(), "expected closing parentheses");
       return MatchOperand_ParseFail;
     }
     Parser.Lex();
     Mods.Sext = true;
   }
   
   if (Mods.hasIntModifiers()) {
+    AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
     Op.setModifiers(Mods);
   }
   return MatchOperand_Success;
 }
 
 unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
 
   uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;

test/MC/AMDGPU/vop1.s

 // NOSICI: v_sin_f16 v1, v2
 // VI: v_sin_f16_e32 v1, v2 ; encoding: [0x02,0x93,0x02,0x7e]
 v_sin_f16 v1, v2
 
 // NOSICI: error: instruction not supported on this GPU
 // NOSICI: v_cos_f16 v1, v2
 // VI: v_cos_f16_e32 v1, v2 ; encoding: [0x02,0x95,0x02,0x7e]
 v_cos_f16 v1, v2
+
+//===----------------------------------------------------------------------===//
+// Floating point literals
+//===----------------------------------------------------------------------===//
+
+// GCN: v_mov_b32_e32 v0, 0.5 ; encoding: [0xf0,0x02,0x00,0x7e]
+v_mov_b32 v0, 0.5
+
+// GCN: v_mov_b32_e32 v0, 0x40480000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x00,0x48,0x40]
+v_mov_b32 v0, 3.125
 No newline at end of file

test/MC/AMDGPU/vop2.s

 // src0 sgpr, src1 inline
 // SICI: v_mul_i32_i24_e64 v1, s2, 3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x06,0x01,0x00]
 v_mul_i32_i24 v1, s2, 3
 
 // src0 inline src1 sgpr
 // SICI: v_mul_i32_i24_e64 v1, 3, s3 ; encoding: [0x01,0x00,0x12,0xd2,0x83,0x06,0x00,0x00]
 v_mul_i32_i24 v1, 3, s3
 
+// SICI: v_add_i32_e32 v0, vcc, 0.5, v0 ; encoding: [0xf0,0x00,0x00,0x4a]
+// VI: v_add_i32_e32 v0, vcc, 0.5, v0 ; encoding: [0xf0,0x00,0x00,0x32]
+v_add_i32 v0, vcc, 0.5, v0
+
+// SICI: v_add_i32_e32 v0, vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0x00,0x4a,0x00,0x00,0x48,0x40]
+// VI: v_add_i32_e32 v0, vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0x00,0x32,0x00,0x00,0x48,0x40]
+v_add_i32 v0, vcc, 3.125, v0
+
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
 // GCN: v_cndmask_b32_e32 v1, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x00]
 v_cndmask_b32 v1, v2, v3, vcc
 
 // GCN: v_cndmask_b32_e32 v1, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x00]