AMDGPU: Set isConvergent on v_cmpx* instructions

[arsenm]

Summary

No test since these aren't used now, except for one place in a pre-emit pass.

[• tstellarAMD]

lib/Target/AMDGPU/SIInstrInfo.td

2294

Why do we need to set hasSideEffects here?

[arsenm]

lib/Target/AMDGPU/SIInstrInfo.td

2294

It seems like writing to exec should count as a side effect, although currently the realgar bit instruction manipulations will not have this set

[nhaehnle]

lib/Target/AMDGPU/SIInstrInfo.td

2294

I see that this is the case in some other places already, but I also doubt that it makes sense. As long as all instructions set (implicit) uses of exec correctly, hasSideEffects shouldn't be needed. Perhaps there's some fragility left with the control-flow annotation instructions, but then IMHO the right approach would be to fix that fragility.

Just my 2c...

[arsenm]

Don't set hasSideEffects

[nhaehnle]

LGTM

[arsenm]

r275200

lib/Target/AMDGPU/SIInstrInfo.td

multiclass VOPC_m <vopc op, dag ins, string op_asm, list<dag> pattern,
                    string opName, bit DefExec, VOPProfile p,
                    list<SchedReadWrite> sched,
                    string revOpName = "", string asm = opName#"_e32 "#op_asm,
                    string alias_asm = opName#" "#op_asm> {
   def "" : VOPC_Pseudo <ins, pattern, opName>,
            VOP2_REV<revOpName#"_e32", !eq(revOpName, opName)> {
     let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
     let SchedRW = sched;
+    let hasSideEffects = DefExec;
+    let isConvergent = DefExec;
   }
 
   let AssemblerPredicates = [isSICI] in {
     def _si : VOPC<op.SI, ins, asm, []>,
               SIMCInstr <opName#"_e32", SIEncodingFamily.SI> {
       let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
       let hasSideEffects = DefExec;
+      let isConvergent = DefExec;
       let SchedRW = sched;
       let DecoderNamespace = "SICI";
       let DisableDecoder = DisableSIDecoder;
     }
 
   } // End AssemblerPredicates = [isSICI]
 
   let AssemblerPredicates = [isVI] in {
     def _vi : VOPC<op.VI, ins, asm, []>,
               SIMCInstr <opName#"_e32", SIEncodingFamily.VI> {
       let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
       let hasSideEffects = DefExec;
+      let isConvergent = DefExec;
       let SchedRW = sched;
       let DecoderNamespace = "VI";
       let DisableDecoder = DisableVIDecoder;
     }
 
   } // End AssemblerPredicates = [isVI]
 
   defm : SIInstAliasBuilder<alias_asm, p>;