AMDGPU/SI: Add support for R_AMDGPU_ABS32

[kzhuravl]

Rebase

[• tstellarAMD]

test/MC/AMDGPU/relocs-abs32.s

131–145 ↗

(On Diff #61700)

These comment sections should be dropped.

[kzhuravl]

Rebase and update test

[kzhuravl]

Update test

[kzhuravl]

Ping

[• tstellarAMD]

test/MC/AMDGPU/elf64-dwarf-relocs.s

1–4 ↗

(On Diff #63264)

This test case should be minimal like the one you add for lld.

[kzhuravl]

Update test

[kzhuravl]

Update test

[• tstellarAMD]

LGTM.

include/llvm/Object/RelocVisitor.h

if (ObjToVisit.getBytesInAddress() == 8) { // 64-bit object file
           return visitELF_SPARCV9_32(R, Value);
         case llvm::ELF::R_SPARC_64:
         case llvm::ELF::R_SPARC_UA64:
           return visitELF_SPARCV9_64(R, Value);
         default:
           HasError = true;
           return RelocToApply();
         }
+      case Triple::amdgcn:
+        switch (RelocType) {
+        case llvm::ELF::R_AMDGPU_ABS32:
+          return visitELF_AMDGPU_ABS32(R, Value);
+        default:
+          HasError = true;
+          return RelocToApply();
+        }
       default:
         HasError = true;
         return RelocToApply();
       }
     } else if (ObjToVisit.getBytesInAddress() == 4) { // 32-bit object file
       switch (ObjToVisit.getArch()) {
       case Triple::x86:
         switch (RelocType) {
RelocToApply visitELF_ARM_ABS32(RelocationRef R, uint64_t Value) {
 
     // Overflow check allows for both signed and unsigned interpretation.
     if (Res < INT32_MIN || Res > UINT32_MAX)
       HasError = true;
 
     return RelocToApply(static_cast<uint32_t>(Res), 4);
   }
 
+  RelocToApply visitELF_AMDGPU_ABS32(RelocationRef R, uint64_t Value) {
+    int64_t Addend = getELFAddend(R);
+    return RelocToApply(Value + Addend, 4);
+  }
+
   /// I386 COFF
   RelocToApply visitCOFF_I386_SECREL(RelocationRef R, uint64_t Value) {
     return RelocToApply(static_cast<uint32_t>(Value), /*Width=*/4);
   }
 
   RelocToApply visitCOFF_I386_DIR32(RelocationRef R, uint64_t Value) {
     return RelocToApply(static_cast<uint32_t>(Value), /*Width=*/4);
   }

lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp

unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx,
   case MCSymbolRefExpr::VK_GOTPCREL:
     return ELF::R_AMDGPU_GOTPCREL;
   }
 
   switch (Fixup.getKind()) {
   default: break;
   case FK_PCRel_4:
     return ELF::R_AMDGPU_REL32;
+  case FK_Data_4:
   case FK_SecRel_4:
     return ELF::R_AMDGPU_ABS32;
   }
 
   llvm_unreachable("unhandled relocation type");
 }
 
 
 MCObjectWriter *llvm::createAMDGPUELFObjectWriter(bool Is64Bit,
                                                   bool HasRelocationAddend,
                                                   raw_pwrite_stream &OS) {
   MCELFObjectTargetWriter *MOTW =
       new AMDGPUELFObjectWriter(Is64Bit, HasRelocationAddend);
   return createELFObjectWriter(MOTW, OS, true);
 }

test/MC/AMDGPU/reloc.s

 // RUN: llvm-mc -filetype=obj -triple amdgcn-- -mcpu=kaveri -show-encoding %s | llvm-readobj -relocations | FileCheck %s
 
 // CHECK: Relocations [
 // CHECK: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0 0x0
 // CHECK: R_AMDGPU_ABS32_HI SCRATCH_RSRC_DWORD1 0x0
 // CHECK: R_AMDGPU_GOTPCREL global_var 0x0
+// CHECK: R_AMDGPU_ABS32 var 0x0
 // CHECK: ]
 
 kernel:
   s_mov_b32 s0, SCRATCH_RSRC_DWORD0
   s_mov_b32 s1, SCRATCH_RSRC_DWORD1
   s_mov_b32 s2, global_var@GOTPCREL
 
 .globl global_var
 
 .globl SCRATCH_RSRC_DWORD0
+
+.section nonalloc, "w", @progbits
+  .long var, common_var