[mips] Fix aui/daui/dahi/dati for MIPSR6

[sdardis]

Summary

For compatiblity with binutils, define these instructions to take
two registers with a 16bit unsigned immediate. Both of the registers
have to be same for dahi and dati.

[sdardis]

Ping.

[dsanders]

lib/Target/Mips/MicroMips64r6InstrInfo.td

93–97

I think we need to split this out into a separate issue. I'm not very keen on the idea of working around a bug in the way tablegen handles tied operands, especially given that the workaround will prevent us from adding CodeGen support.

As you mention in the comment, the issue is that CVT_Tied is implemented such that it copies the MCOperand that this operand is tied to without checking if the current operand would render to the same thing. As a result, the matcher silently ignores bad input and emits a valid instruction that isn't what the user specified. It should error out instead.

I'll see if I can find a way to fix tablegen.

[dsanders]

I've posted a possible solution to the constraint problem as D21994.

[dsanders]

This will need reworking to account for D21994 having been committed. I'll review this once it's been rebased.

[sdardis]

Rebased on account of D21994 being committed.

[sdardis]

Ping.

[dsanders]

I have a couple minor comments, the main one is the dubious disassembler test.

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

601–604

GPR32 -> GPR64

lib/Target/Mips/Mips32r6InstrInfo.td

319

It feels wrong to have a simm16 immediate in the instruction but only accept uimm16 inputs in the assembly but I agree that this is the intended behaviour.

I think we should render it to the instruction as a simm16 so that the MCInst's are consistent though.

test/MC/Disassembler/Mips/micromips64r6/valid.txt

38–40

This doesn't look correct to me. I haven't double-checked the encodings but there's only one bit different between the two instructions yet two things are different in the assembly (dahi->dati, and $16 -> $17)

Also, could you comment on why it isn't $3 any more?

[sdardis]

Addressed review comments.

[sdardis]

test/MC/Disassembler/Mips/micromips64r6/valid.txt

38–40

The change was due to a bug in the decoder, it was reading the minor opcode as the register for microMIPS64r6. MIPSR6 has the fields swapped in comparison.

[sdardis]

Zoran, would you be able to take a look at this? Thanks.

[zoran.jovanovic]

LGTM.

[sdardis]

Daniel, can you accept this revision?

[dsanders]

In D21473#544807, @sdardis wrote:

Daniel, can you accept this revision?

Sorry for the delay, I thought I'd redirected this temporary email address to my new one but apparently not

[sdardis]

No problem. Committed as r284218.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

 unsigned
 MipsAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst,
                                               const OperandVector &Operands) {
   switch (Inst.getOpcode()) {
   default:
     return Match_Success;
   case Mips::DATI:
   case Mips::DAHI:
+  case Mips::DATI_MM64R6:
+  case Mips::DAHI_MM64R6:
     if (static_cast<MipsOperand &>(*Operands[1])
             .isValidForTie(static_cast<MipsOperand &>(*Operands[2])))
       return Match_Success;
     return Match_RequiresSameSrcAndDst;
   }
 }
 unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
   switch (Inst.getOpcode()) {
+  // As described by the MIPSR6 spec, daui must not use the zero operand for
+  // its source operand.
+  case Mips::DAUI:
+  case Mips::DAUI_MM64R6:
+    if (Inst.getOperand(1).getReg() == Mips::ZERO ||
+        Inst.getOperand(1).getReg() == Mips::ZERO_64)
+      return Match_RequiresNoZeroRegister;
+    return Match_Success;
   // As described by the Mips32r2 spec, the registers Rd and Rs for
   // jalr.hb must be different.
   // It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction
   // and registers Rd and Base for microMIPS lwp instruction
   case Mips::JALR_HB:
   case Mips::JALRC_HB_MMR6:
   case Mips::JALRC_MMR6:
     if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

 
 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 /// handle.
 template <typename InsnType>
 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
                                    const void *Decoder);
 
 template <typename InsnType>
+static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
+                                   const void *Decoder);
+
+template <typename InsnType>
+static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
+                                   const void *Decoder);
+
+template <typename InsnType>
 static DecodeStatus
 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
                       const void *Decoder);
 
 template <typename InsnType>
 static DecodeStatus
 DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
                            const void *Decoder);
if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
     return MCDisassembler::Fail;
   // $n2
   MI.addOperand(MCOperand::createImm(0));
 
   return MCDisassembler::Success;
 }
 
 template <typename InsnType>
+static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
+                               const void *Decoder) {
+  InsnType Rt = fieldFromInstruction(insn, 16, 5);
+  InsnType Imm = fieldFromInstruction(insn, 0, 16);
+  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
+                                       Rt)));
+  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
+                                       Rt)));
+  MI.addOperand(MCOperand::createImm(Imm));
+
+  return MCDisassembler::Success;
+}
+
+template <typename InsnType>
+static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
+                               const void *Decoder) {
+  InsnType Rt = fieldFromInstruction(insn, 21, 5);
+  InsnType Imm = fieldFromInstruction(insn, 0, 16);
+  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
+                                       Rt)));
+  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
+                                       Rt)));
+  MI.addOperand(MCOperand::createImm(Imm));
+
+  return MCDisassembler::Success;
+}
+
+template <typename InsnType>
 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
                                           uint64_t Address,
                                           const void *Decoder) {
   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
   // (otherwise we would have matched the ADDI instruction from the earlier
   // ISA's instead).
   //
   // We have:

lib/Target/Mips/MicroMips32r6InstrInfo.td

class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
   list<dag> Pattern = [];
 }
 
 class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
 
 class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
     : MMR6Arch<instr_asm> {
   dag OutOperandList = (outs GPROpnd:$rt);
-  dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
+  dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);
   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
   list<dag> Pattern = [];
 }
 
 class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
 
 class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>;
 class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>;

lib/Target/Mips/MicroMips64r6InstrInfo.td

 //
 // Instruction Descriptions
 //
 //===----------------------------------------------------------------------===//
 
 class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
     : MMR6Arch<instr_asm>, MipsR6Inst {
   dag OutOperandList = (outs GPROpnd:$rt);
-  dag InOperandList = (ins GPROpnd:$rs, simm16:$imm);
+  dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);
   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
   list<dag> Pattern = [];
 }
 class DAUI_MMR6_DESC : DAUI_MMR6_DESC_BASE<"daui", GPR64Opnd>;
 
 class DAHI_DATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
     : MMR6Arch<instr_asm>, MipsR6Inst {
   dag OutOperandList = (outs GPROpnd:$rs);
-  dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
-  string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
+  dag InOperandList = (ins GPROpnd:$rt, uimm16:$imm);
+  string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
   string Constraints = "$rs = $rt";
 }
+
 class DAHI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dahi", GPR64Opnd>;
 class DATI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dati", GPR64Opnd>;
 
 class EXTBITS_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
                         Operand SizeOpnd, SDPatternOperator Op = null_frag>
     : MMR6Arch<instr_asm>, MipsR6Inst {
   dag OutOperandList = (outs RO:$rt);
   dag InOperandList = (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size);
   string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $pos, $size");
   list<dag> Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))];
   InstrItinClass Itinerary = II_EXT;
   Format Form = FrmR;

 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 let DecoderNamespace = "MicroMipsR6" in {
   def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6;
+  let DecoderMethod = "DecodeDAHIDATIMMR6" in {
     def DAHI_MM64R6 : StdMMR6Rel, DAHI_MMR6_DESC, DAHI_MMR6_ENC, ISA_MICROMIPS64R6;
     def DATI_MM64R6 : StdMMR6Rel, DATI_MMR6_DESC, DATI_MMR6_ENC, ISA_MICROMIPS64R6;
+  }
   def DEXT_MM64R6 : StdMMR6Rel, DEXT_MMR6_DESC, DEXT_MMR6_ENC,
                     ISA_MICROMIPS64R6;
   def DEXTM_MM64R6 : StdMMR6Rel, DEXTM_MMR6_DESC, DEXTM_MMR6_ENC,
                      ISA_MICROMIPS64R6;
   def DEXTU_MM64R6 : StdMMR6Rel, DEXTU_MMR6_DESC, DEXTU_MMR6_ENC,
                      ISA_MICROMIPS64R6;
   def DALIGN_MM64R6 : StdMMR6Rel, DALIGN_MMR6_DESC, DALIGN_MMR6_ENC,
                       ISA_MICROMIPS64R6;

lib/Target/Mips/Mips32r6InstrInfo.td

 
 class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>;
 class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>;
 
 class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
                     InstrItinClass itin = NoItinerary>
       : MipsR6Arch<instr_asm> {
   dag OutOperandList = (outs GPROpnd:$rs);
-  dag InOperandList = (ins GPROpnd:$rt, simm16:$imm);
+  dag InOperandList = (ins GPROpnd:$rt, uimm16:$imm);
   string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
   list<dag> Pattern = [];
   InstrItinClass Itinerary = itin;
 }
 
 class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd, II_AUI>;
 
 class BRANCH_DESC_BASE {

lib/Target/Mips/Mips64r6InstrInfo.td

 //===----------------------------------------------------------------------===//
 //
 // Instruction Descriptions
 //
 //===----------------------------------------------------------------------===//
 
 class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, InstrItinClass itin> {
   dag OutOperandList = (outs GPROpnd:$rs);
-  dag InOperandList = (ins GPROpnd:$rt, simm16_relaxed:$imm);
-  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
+  dag InOperandList = (ins GPROpnd:$rt, uimm16_altrelaxed:$imm);
+  string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
   string Constraints = "$rs = $rt";
   InstrItinClass Itinerary = itin;
 }
 
 class DALIGN_DESC  : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3, II_DALIGN>;
 class DAHI_DESC    : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd, II_DAHI>;
 class DATI_DESC    : AHI_ATI_DESC_BASE<"dati", GPR64Opnd, II_DATI>;
 class DAUI_DESC    : AUI_DESC_BASE<"daui", GPR64Opnd, II_DAUI>;

 class SC64_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>;
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 let AdditionalPredicates = [NotInMicroMips] in {
+  let DecoderMethod = "DecodeDAHIDATI" in {
     def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6;
     def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6;
+  }
   def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6;
   def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6;
 }
 def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6;
 let AdditionalPredicates = [NotInMicroMips] in {
   def DCLO_R6 : R6MMR6Rel, DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6;
   def DCLZ_R6 : R6MMR6Rel, DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6;
   def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6;

lib/Target/Mips/MipsInstrInfo.td

 def ConstantUImm20AsmOperandClass
     : ConstantUImmAsmOperandClass<20, [ConstantUImm26AsmOperandClass]>;
 def UImm16RelaxedAsmOperandClass
     : UImmAsmOperandClass<16, [ConstantUImm20AsmOperandClass]> {
   let Name = "UImm16_Relaxed";
   let PredicateMethod = "isAnyImm<16>";
   let DiagnosticType = "UImm16_Relaxed";
 }
+// Similar to the relaxed classes which take an SImm and render it as
+// an UImm, this takes a UImm and renders it as an SImm.
+def UImm16AltRelaxedAsmOperandClass
+    : SImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]> {
+  let Name = "UImm16_AltRelaxed";
+  let PredicateMethod = "isUImm<16>";
+  let DiagnosticType = "UImm16_AltRelaxed";
+}
 def UImm16AsmOperandClass
     : UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>;
 def SImm16RelaxedAsmOperandClass
     : SImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]> {
   let Name = "SImm16_Relaxed";
   let PredicateMethod = "isAnyImm<16>";
   let DiagnosticType = "SImm16_Relaxed";
 }
+
 def SImm16AsmOperandClass
     : SImmAsmOperandClass<16, [SImm16RelaxedAsmOperandClass]>;
 def ConstantSImm10Lsl3AsmOperandClass : AsmOperandClass {
   let Name = "SImm10Lsl3";
   let RenderMethod = "addImmOperands";
   let PredicateMethod = "isScaledSImm<10, 3>";
   let SuperClasses = [SImm16AsmOperandClass];
   let DiagnosticType = "SImm10_Lsl3";

 
 // Like uimm16_64 but coerces simm16 to uimm16.
 def uimm16_64_relaxed : Operand<i64> {
   let PrintMethod = "printUImm<16>";
   let ParserMatchClass =
       !cast<AsmOperandClass>("UImm16RelaxedAsmOperandClass");
 }
 
+def uimm16_altrelaxed : Operand<i32> {
+  let PrintMethod = "printUImm<16>";
+  let ParserMatchClass =
+      !cast<AsmOperandClass>("UImm16AltRelaxedAsmOperandClass");
+}
 // Like uimm5 but reports a less confusing error for 32-63 when
 // an instruction alias permits that.
 def uimm5_report_uimm6 : Operand<i32> {
   let PrintMethod = "printUImm<5>";
   let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass;
 }
 
 // Like uimm5_64 but reports a less confusing error for 32-63 when

test/MC/Disassembler/Mips/micromips32r6/valid.txt

 0x30 0x64 0x04 0xd2 # CHECK: addiu $3, $4, 1234
 0x00 0xa4 0x19 0x50 # CHECK: addu $3, $4, $5
 0x78 0x80 0x00 0x19 # CHECK: addiupc $4, 100
 0x78 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
 0x78 0x7e 0xff 0xff # CHECK: auipc $3, -1
 0x00 0x43 0x24 0x1f # CHECK: align $4, $2, $3, 2
 0x00 0xa4 0x1a 0x50 # CHECK: and $3, $4, $5
 0xd0 0x64 0x04 0xd2 # CHECK: andi $3, $4, 1234
-0x10 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23
+0x10 0x62 0xff 0xe9 # CHECK: aui $3, $2, 65513
 0x74 0x83 0x00 0x08 # CHECK: beqc $3, $4, 16
 0xe4 0x83 0x00 0x08 # CHECK: bgec $3, $4, 16
 0xc0 0x83 0x00 0x08 # CHECK: bgeuc $3, $4, 16
 0xc4 0x83 0x00 0x08 # CHECK: bltc $3, $4, 16
 0xe0 0x83 0x00 0x08 # CHECK: bltuc $3, $4, 16
 0x7c 0x83 0x00 0x08 # CHECK: bnec $3, $4, 16
 0x74 0x40 0x02 0x9a # CHECK: beqzalc $2, 1332
 0x7c 0x40 0x02 0x9a # CHECK: bnezalc $2, 1332

test/MC/Disassembler/Mips/micromips64r6/valid.txt

 0x21 0x3b 0x59 0x84 # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27)
 0x01 0x26 0x38 0xc0 # CHECK: rotr $9, $6, 7
 0x00 0xc7 0x48 0xd0 # CHECK: rotrv $9, $6, $7
 0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4)
 0x20 0x44 0xd0 0x08 # CHECK: swm32 $16, $17, 8($4)
 0x00 0x00 0x8b 0x7c # CHECK: syscall
 0x01 0x8c 0x8b 0x7c # CHECK: syscall 396
 0xf0 0x64 0x00 0x05 # CHECK: daui $3, $4, 5
-0x42 0x23 0x00 0x04 # CHECK: dahi $3, 4
-0x42 0x03 0x00 0x04 # CHECK: dati $3, 4
+0x42 0x23 0x00 0x04 # CHECK: dahi $3, $3, 4
+0x42 0x03 0x00 0x04 # CHECK: dati $3, $3, 4
 0x59 0x26 0x30 0xec # CHECK: dext $9, $6, 3, 7
 0x59 0x26 0x30 0xe4 # CHECK: dextm $9, $6, 3, 39
 0x59 0x26 0x30 0xd4 # CHECK: dextu $9, $6, 35, 7
 0x58 0x43 0x25 0x1c # CHECK: dalign $4, $2, $3, 5
 0x58 0xa4 0x19 0x18 # CHECK: ddiv $3, $4, $5
 0x58 0xa4 0x19 0x58 # CHECK: dmod $3, $4, $5
 0x58 0xa4 0x19 0x98 # CHECK: ddivu $3, $4, $5
 0x58 0xa4 0x19 0xd8 # CHECK: dmodu $3, $4, $5
 0x54 0xa4 0x18 0x30 # CHECK: add.s $f3, $f4, $f5

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt

 # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r6 | FileCheck %s
 0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4
 0x19 0x00 0x80 0xec # CHECK: addiupc $4, 100
 0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10
 0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2
 0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56
-0xe9 0xff 0x62 0x3c # CHECK: aui $3, $2, -23
+0xe9 0xff 0x62 0x3c # CHECK: aui $3, $2, 65513
 0xff 0xff 0x7e 0xec # CHECK: auipc $3, -1
 0x9b 0x14 0x11 0x04 # CHECK: bal 21104
 0xb8 0x96 0x37 0xe8 # CHECK: balc 14572260
 0xb8 0x96 0x37 0xc8 # CHECK: bc 14572260
 0x01 0x00 0x20 0x45 # CHECK: bc1eqz $f0, 8
 0x01 0x00 0x3f 0x45 # CHECK: bc1eqz $f31, 8
 0x01 0x00 0xa0 0x45 # CHECK: bc1nez $f0, 8
 0x01 0x00 0xbf 0x45 # CHECK: bc1nez $f31, 8

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt

 # The encode/decode functions are not inverses of each other in the immediate case.
 0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, 1336
 0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 8
 0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 8
 0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 260
 0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10
 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4
 0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4
-0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23
+0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, 65513
 0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x40 0x08 0x80 0x03 # CHECK: mfc0 $8, $16, 3
 0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x41 0x60 0x60 0x00 # CHECK: di
 0x41 0x60 0x60 0x20 # CHECK: ei
 0x41 0x6e 0x60 0x20 # CHECK: ei $14
 0x41 0x7e 0x60 0x00 # CHECK: di $fp
 # FIXME: The encode/decode functions are not inverses of each other.

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt

 # RUN: llvm-mc %s -disassemble -triple=mipsel-unknown-linux -mcpu=mips64r6 | FileCheck %s
 0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10
 0x19 0x00 0x80 0xec # CHECK: addiupc $4, 100
 0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2
 0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56
 0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4
-0xe9 0xff 0x62 0x3c # CHECK: aui $3, $2, -23
+0xe9 0xff 0x62 0x3c # CHECK: aui $3, $2, 65513
 0xff 0xff 0x7e 0xec # CHECK: auipc $3, -1
 0x9b 0x14 0x11 0x04 # CHECK: bal 21104
 0xb8 0x96 0x37 0xe8 # CHECK: balc 14572260
 0xb8 0x96 0x37 0xc8 # CHECK: bc 14572260
 0x01 0x00 0x20 0x45 # CHECK: bc1eqz $f0, 8
 0x01 0x00 0x3f 0x45 # CHECK: bc1eqz $f31, 8
 0x01 0x00 0xa0 0x45 # CHECK: bc1nez $f0, 8
 0x01 0x00 0xbf 0x45 # CHECK: bc1nez $f31, 8

 0x83 0x18 0x84 0x46 # CHECK: cmp.ueq.s $f2, $f3, $f4
 0x87 0x18 0xa4 0x46 # CHECK: cmp.ule.d $f2, $f3, $f4
 0x87 0x18 0x84 0x46 # CHECK: cmp.ule.s $f2, $f3, $f4
 0x85 0x18 0xa4 0x46 # CHECK: cmp.ult.d $f2, $f3, $f4
 0x85 0x18 0x84 0x46 # CHECK: cmp.ult.s $f2, $f3, $f4
 0x81 0x18 0xa4 0x46 # CHECK: cmp.un.d $f2, $f3, $f4
 0x81 0x18 0x84 0x46 # CHECK: cmp.un.s $f2, $f3, $f4
 0x78 0x56 0x66 0x04 # CHECK: dahi $3, $3, 22136
+0xcd 0xab 0x7e 0x04 # CHECK: dati $3, $3, 43981
 0x64 0x23 0x43 0x7c # CHECK: dalign $4, $2, $3, 5
 0x34 0x12 0x62 0x74 # CHECK: daui $3, $2, 4660
 0x24 0x20 0x02 0x7c # CHECK: dbitswap $4, $2
 0x53 0x90 0xc0 0x00 # CHECK: dclo $18, $6
 0x52 0x80 0x20 0x03 # CHECK: dclz $16, $25
 0x9e 0x10 0x64 0x00 # CHECK: ddiv $2, $3, $4
 0x9f 0x10 0x64 0x00 # CHECK: ddivu $2, $3, $4
 0x00 0x60 0x60 0x41 # CHECK: di

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt

 0x02 0x8e 0x5e 0xf1 # CHECK: tgeu $20, $14, 379
 0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp
 0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25
 0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
 0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra
 0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra
 0x04 0x11 0x14 0x9b # CHECK: bal 21104
 0x04 0x66 0x56 0x78 # CHECK: dahi $3, $3, 22136
-0x04 0x7e 0xab 0xcd # CHECK: dati $3, $3, -21555
+0x04 0x7e 0xab 0xcd # CHECK: dati $3, $3, 43981
 # The encode/decode functions are not inverses of each other in the immediate case.
 0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1336
 0x18 0x02 0xff 0xfa # CHECk: blezalc $2, -20
 # The encode/decode functions are not inverses of each other in the immediate case.
 0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1336
 0x18 0x42 0xff 0xfa # CHECK: bgezalc $2, -20
 0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 260
 0x18 0x43 0xff 0xfa # CHECK: bgeuc $2, $3, -20

 # The encode/decode functions are not inverses of each other in the immediate case.
 0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, 1336
 0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 8
 0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 8
 0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 260
 0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10
 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4
 0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4
-0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23
+0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, 65513
 0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
 0x40 0x08 0x80 0x03 # CHECK: mfc0 $8, $16, 3
 0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
 0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
 0x40 0xa4 0x50 0x00 # CHECK: dmtc0 $4, $10, 0
 0x41 0x60 0x60 0x00 # CHECK: di
 0x41 0x60 0x60 0x20 # CHECK: ei
 0x41 0x6e 0x60 0x20 # CHECK: ei $14

test/MC/Mips/micromips32r6/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
   addiusp 1024             # CHECK: addiusp 1024        # encoding: [0x4c,0x01]
   addiusp 1028             # CHECK: addiusp 1028        # encoding: [0x4c,0x03]
   addiusp -16              # CHECK: addiusp -16         # encoding: [0x4f,0xf9]
   aluipc $3, 56            # CHECK: aluipc $3, 56       # encoding: [0x78,0x7f,0x00,0x38]
   and $3, $4, $5           # CHECK: and $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0x50]
   andi $3, $4, 1234        # CHECK: andi $3, $4, 1234   # encoding: [0xd0,0x64,0x04,0xd2]
   auipc $3, -1             # CHECK: auipc $3, -1        # encoding: [0x78,0x7e,0xff,0xff]
   align $4, $2, $3, 2      # CHECK: align $4, $2, $3, 2 # encoding: [0x00,0x43,0x24,0x1f]
-  aui $3,$2,-23            # CHECK: aui $3, $2, -23     # encoding: [0x10,0x62,0xff,0xe9]
+  aui $3, $2, 23           # CHECK: aui $3, $2, 23      # encoding: [0x10,0x62,0x00,0x17]
   beqc $3,$4, 16           # CHECK: beqc    $3, $4, 16  # encoding: [0x74,0x83,0x00,0x08]
   bgec $3,$4, 16           # CHECK: bgec    $3, $4, 16  # encoding: [0xe4,0x83,0x00,0x08]
   bgeuc $3,$4, 16          # CHECK: bgeuc   $3, $4, 16  # encoding: [0xc0,0x83,0x00,0x08]
   bltc $3,$4, 16           # CHECK: bltc    $3, $4, 16  # encoding: [0xc4,0x83,0x00,0x08]
   bltuc $3,$4, 16          # CHECK: bltuc   $3, $4, 16  # encoding: [0xe0,0x83,0x00,0x08]
   bnec $3,$4, 16           # CHECK: bnec    $3, $4, 16  # encoding: [0x7c,0x83,0x00,0x08]
   beqzalc $2, 1332         # CHECK: beqzalc $2, 1332    # encoding: [0x74,0x40,0x02,0x9a]
   bnezalc $2, 1332         # CHECK: bnezalc $2, 1332    # encoding: [0x7c,0x40,0x02,0x9a]

test/MC/Mips/micromips64r6/invalid.s

# RUN: FileCheck %s < %t1
   beqzc16 $9, 20           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   beqzc16 $6, 31           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
   beqzc16 $6, 130          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
   bnezc16 $9, 20           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   bnezc16 $6, 31           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
   bnezc16 $6, 130          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
   cache -1, 255($7)        # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
   cache 32, 255($7)        # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
+  dahi    $4, $4, 65536    # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate
+  dahi    $4, $4, -1       # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate
+  dahi    $4, $5, 1        # CHECK: :[[@LINE]]:3: error: source and destination must match
+  dati    $4, $4, 65536    # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate
+  dati    $4, $4, -1       # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate
+  dati    $4, $5, 1        # CHECK: :[[@LINE]]:3: error: source and destination must match
+  daui    $4, $0, 1        # CHECK: :[[@LINE]]:3: error: invalid operand ($zero) for instruction
+  daui    $4, $4, 65536    # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate
+  daui    $4, $4, -1       # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate
+  dati    $4, $4, -1       # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate
+  dati    $4, $5, 1        # CHECK: :[[@LINE]]:3: error: source and destination must match
   # FIXME: Check various 'pos + size' constraints on dext*
   dext $2, $3, -1, 1   # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
   dext $2, $3, 64, 1   # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
   dext $2, $3, 1, 0    # CHECK: :[[@LINE]]:19: error: expected immediate in range 1 .. 32
   dext $2, $3, 1, 33   # CHECK: :[[@LINE]]:19: error: expected immediate in range 1 .. 32
   dextm $2, $3, -1, 1  # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
   dextm $2, $3, 32, 1  # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
   dextm $2, $3, -1, 33 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate

test/MC/Mips/micromips64r6/valid.s

a:
         addiusp 1028             # CHECK: addiusp 1028        # encoding: [0x4c,0x03]
         addiusp -16              # CHECK: addiusp -16         # encoding: [0x4f,0xf9]
         and16 $16, $2            # CHECK: and16 $16, $2       # encoding: [0x44,0x21]
         andi16 $4, $5, 8         # CHECK: andi16 $4, $5, 8    # encoding: [0x2e,0x56]
         b 132                    # CHECK: bc16 132            # encoding: [0xcc,0x42]
         bc16 132                 # CHECK: bc16 132            # encoding: [0xcc,0x42]
         beqzc16 $6, 20           # CHECK: beqzc16 $6, 20      # encoding: [0x8f,0x0a]
         bnezc16 $6, 20           # CHECK: bnezc16 $6, 20      # encoding: [0xaf,0x0a]
+        aui $4, $5, 1            # CHECK: aui $4, $5, 1       # encoding: [0x10,0x85,0x00,0x01]
         daui $3, $4, 5           # CHECK: daui $3, $4, 5      # encoding: [0xf0,0x64,0x00,0x05]
-        dahi $3, 4               # CHECK: dahi $3, 4          # encoding: [0x42,0x23,0x00,0x04]
-        dati $3, 4               # CHECK: dati $3, 4          # encoding: [0x42,0x03,0x00,0x04]
+        dahi $3, $3, 4           # CHECK: dahi $3, $3, 4      # encoding: [0x42,0x23,0x00,0x04]
+        dati $3, $3, 4           # CHECK: dati $3, $3, 4      # encoding: [0x42,0x03,0x00,0x04]
         dext $9, $6, 3, 7        # CHECK: dext $9, $6, 3, 7   # encoding: [0x59,0x26,0x30,0xec]
         dextm $9, $6, 3, 39      # CHECK: dextm $9, $6, 3, 39 # encoding: [0x59,0x26,0x30,0xe4]
         dextu $9, $6, 35, 7      # CHECK: dextu $9, $6, 35, 7  # encoding: [0x59,0x26,0x30,0xd4]
         dalign $4, $2, $3, 5     # CHECK: dalign $4, $2, $3, 5  # encoding: [0x58,0x43,0x25,0x1c]
         ldpc $2, 16              # CHECK: ldpc $2, 16           # encoding: [0x78,0x58,0x00,0x02]
         lw $3, 32($gp)           # CHECK: lw $3, 32($gp)        # encoding: [0x65,0x88]
         lw $3, 24($sp)           # CHECK: lw $3, 24($sp)        # encoding: [0x48,0x66]
         lw16 $4, 8($17)          # CHECK: lw16 $4, 8($17)       # encoding: [0x6a,0x12]

test/MC/Mips/mips32r6/invalid.s

 # Instructions that are available for the current ISA but should be rejected by
 # the assembler (e.g. invalid set of operands or operand's restrictions not met).
 
 # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r6 2>%t1
 # RUN: FileCheck %s < %t1
 
         .text
 local_label:
         .set noreorder
         .set noat
         align   $4, $2, $3, -1    # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate
         align   $4, $2, $3, 4     # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate
+        aui     $4, $4, 65536     # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate
+        aui     $4, $4, -1        # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate
         jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
         jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
         swc2    $25,24880($s0)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         break -1          # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
         break 1024        # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
         break -1, 5       # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
         break 1024, 5     # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
         break 7, -1       # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate

test/MC/Mips/mips32r6/valid.s

 a:
         .set noat
         # FIXME: Add the instructions carried forward from older ISA's
         and     $2,4             # CHECK: andi $2, $2, 4      # encoding: [0x30,0x42,0x00,0x04]
         addiupc $4, 100          # CHECK: addiupc $4, 100     # encoding: [0xec,0x80,0x00,0x19]
         addu    $9,10            # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         align   $4, $2, $3, 2    # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0]
         aluipc  $3, 56           # CHECK: aluipc $3, 56       # encoding: [0xec,0x7f,0x00,0x38]
-        aui     $3,$2,-23        # CHECK: aui $3, $2, -23     # encoding: [0x3c,0x62,0xff,0xe9]
+        aui     $3, $2, 23       # CHECK: aui $3, $2, 23      # encoding: [0x3c,0x62,0x00,0x17]
         auipc   $3, -1           # CHECK: auipc $3, -1        # encoding: [0xec,0x7e,0xff,0xff]
         bal     21100            # CHECK: bal 21100           # encoding: [0x04,0x11,0x14,0x9b]
         balc 14572256            # CHECK: balc 14572256       # encoding: [0xe8,0x37,0x96,0xb8]
         bc 14572256              # CHECK: bc 14572256         # encoding: [0xc8,0x37,0x96,0xb8]
         bc1eqz  $f0,4            # CHECK: bc1eqz $f0, 4       # encoding: [0x45,0x20,0x00,0x01]
         bc1eqz  $f31,4           # CHECK: bc1eqz $f31, 4      # encoding: [0x45,0x3f,0x00,0x01]
         bc1nez  $f0,4            # CHECK: bc1nez $f0, 4       # encoding: [0x45,0xa0,0x00,0x01]
         bc1nez  $f31,4           # CHECK: bc1nez $f31, 4      # encoding: [0x45,0xbf,0x00,0x01]

test/MC/Mips/mips64r6/invalid.s

 # Instructions that are available for the current ISA but should be rejected by
 # the assembler (e.g. invalid set of operands or operand's restrictions not met).
 
 # RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r6 2>%t1
 # RUN: FileCheck %s < %t1
 
         .text
 local_label:
         .set noreorder
   .set noat
         align   $4, $2, $3, -1    # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate
         align   $4, $2, $3, 4     # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate
+        aui     $4, $4, 65536     # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate
+        aui     $4, $4, -1        # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate
         jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
         jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different
         ldc2    $8,-21181($at)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         break -1          # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
         break 1024        # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
         break -1, 5       # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
         break 1024, 5     # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
         break 7, -1       # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
.set noat
         blezc $0, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
         bgezc $0, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
         bgtzc $0, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
         bltzc $0, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
         beqzc $0, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
         bnezc $0, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
         cache -1, 255($7)    # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
         cache 32, 255($7)    # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+        dahi    $4, $4, 65536     # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate
+        dahi    $4, $4, -1        # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate
+        dahi    $4, $5, 1         # CHECK: :[[@LINE]]:9: error: source and destination must match
         dalign  $4, $2, $3, -1    # CHECK: :[[@LINE]]:29: error: expected 3-bit unsigned immediate
         dalign  $4, $2, $3, 8     # CHECK: :[[@LINE]]:29: error: expected 3-bit unsigned immediate
+        dati    $4, $4, 65536     # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate
+        dati    $4, $4, -1        # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate
+        dati    $4, $5, 1         # CHECK: :[[@LINE]]:9: error: source and destination must match
+        daui    $4, $0, 1         # CHECK: :[[@LINE]]:9: error: invalid operand ($zero) for instruction
+        daui    $4, $4, 65536     # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate
+        daui    $4, $4, -1        # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate
+        dati    $4, $4, -1        # CHECK: :[[@LINE]]:25: error: expected 16-bit unsigned immediate
+        dati    $4, $5, 1         # CHECK: :[[@LINE]]:9: error: source and destination must match
         dlsa    $2, $3, $4, 0     # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4
         dlsa    $2, $3, $4, 5     # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4
         drotr32 $2, $3, -1   # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
         drotr32 $2, $3, 32   # CHECK: :[[@LINE]]:25: error: expected 5-bit unsigned immediate
         jalr.hb $31          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
         jalr.hb $31, $31     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
         lsa     $2, $3, $4, 0     # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4
         lsa     $2, $3, $4, 5     # CHECK: :[[@LINE]]:29: error: expected immediate in range 1 .. 4

test/MC/Mips/mips64r6/valid.s

 a:
         .set noat
         # FIXME: Add the instructions carried forward from older ISA's
         addiupc $4, 100          # CHECK: addiupc $4, 100     # encoding: [0xec,0x80,0x00,0x19]
         addu    $9,10            # CHECK: addiu $9, $9, 10    # encoding: [0x25,0x29,0x00,0x0a]
         align   $4, $2, $3, 2    # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0]
         aluipc  $3, 56           # CHECK: aluipc $3, 56       # encoding: [0xec,0x7f,0x00,0x38]
         and     $2,4             # CHECK: andi $2, $2, 4      # encoding: [0x30,0x42,0x00,0x04]
-        aui     $3,$2,-23        # CHECK: aui $3, $2, -23     # encoding: [0x3c,0x62,0xff,0xe9]
+        aui     $3, $2, 23       # CHECK: aui $3, $2, 23      # encoding: [0x3c,0x62,0x00,0x17]
         auipc   $3, -1           # CHECK: auipc $3, -1        # encoding: [0xec,0x7e,0xff,0xff]
         bal     21100            # CHECK: bal 21100           # encoding: [0x04,0x11,0x14,0x9b]
         balc 14572256            # CHECK: balc 14572256       # encoding: [0xe8,0x37,0x96,0xb8]
         bc 14572256              # CHECK: bc 14572256         # encoding: [0xc8,0x37,0x96,0xb8]
         bc1eqz  $f0,4            # CHECK: bc1eqz $f0, 4       # encoding: [0x45,0x20,0x00,0x01]
         bc1eqz  $f31,4           # CHECK: bc1eqz $f31, 4      # encoding: [0x45,0x3f,0x00,0x01]
         bc1nez  $f0,4            # CHECK: bc1nez $f0, 4       # encoding: [0x45,0xa0,0x00,0x01]
         bc1nez  $f31,4           # CHECK: bc1nez $f31, 4      # encoding: [0x45,0xbf,0x00,0x01]
a:
         cmp.ueq.d  $f2,$f3,$f4      # CHECK: cmp.ueq.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x83]
         cmp.ueq.s  $f2,$f3,$f4      # CHECK: cmp.ueq.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x83]
         cmp.ule.d  $f2,$f3,$f4      # CHECK: cmp.ule.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x87]
         cmp.ule.s  $f2,$f3,$f4      # CHECK: cmp.ule.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x87]
         cmp.ult.d  $f2,$f3,$f4      # CHECK: cmp.ult.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x85]
         cmp.ult.s  $f2,$f3,$f4      # CHECK: cmp.ult.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x85]
         cmp.un.d   $f2,$f3,$f4      # CHECK: cmp.un.d $f2, $f3, $f4  # encoding: [0x46,0xa4,0x18,0x81]
         cmp.un.s   $f2,$f3,$f4      # CHECK: cmp.un.s $f2, $f3, $f4  # encoding: [0x46,0x84,0x18,0x81]
-        daddu   $19,26943           # CHECK: daddiu $19, $19, 26943  # encoding: [0x66,0x73,0x69,0x3f]
-        daddu   $24,$2,18079        # CHECK: daddiu $24, $2, 18079   # encoding: [0x64,0x58,0x46,0x9f]
-        dahi    $3,$3,0x5678        # CHECK: dahi $3, $3, 22136      # encoding: [0x04,0x66,0x56,0x78]
-        dalign  $4,$2,$3,5          # CHECK: dalign $4, $2, $3, 5    # encoding: [0x7c,0x43,0x23,0x64]
-        dati    $3,$3,0xabcd        # CHECK: dati $3, $3, -21555     # encoding: [0x04,0x7e,0xab,0xcd]
-        daui    $3,$2,0x1234        # CHECK: daui $3, $2, 4660       # encoding: [0x74,0x62,0x12,0x34]
+        daddu   $19,26943        # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f]
+        daddu   $24,$2,18079     # CHECK: daddiu $24, $2, 18079  # encoding: [0x64,0x58,0x46,0x9f]
+        dahi    $3, $3, 0x5678   # CHECK: dahi $3, $3, 22136     # encoding: [0x04,0x66,0x56,0x78]
+        dalign  $4,$2,$3,5       # CHECK: dalign $4, $2, $3, 5 # encoding: [0x7c,0x43,0x23,0x64]
+        dati     $3, $3, 0xabcd  # CHECK: dati $3, $3, 43981   # encoding: [0x04,0x7e,0xab,0xcd]
+        daui     $3, $2, 0x1234  # CHECK: daui $3, $2, 4660    # encoding: [0x74,0x62,0x12,0x34]
         dbitswap $4, $2          # CHECK: dbitswap $4, $2    # encoding: [0x7c,0x02,0x20,0x24]
         dclo    $s2,$a2          # CHECK: dclo $18, $6           # encoding: [0x00,0xc0,0x90,0x53]
         dclz    $s0,$25          # CHECK: dclz $16, $25          # encoding: [0x03,0x20,0x80,0x52]
         ddiv    $2,$3,$4         # CHECK: ddiv $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9e]
         ddivu   $2,$3,$4         # CHECK: ddivu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9f]
         di                       # CHECK: di               # encoding: [0x41,0x60,0x60,0x00]
         di      $s8              # CHECK: di  $fp          # encoding: [0x41,0x7e,0x60,0x00]
         div     $2,$3,$4         # CHECK: div $2, $3, $4   # encoding: [0x00,0x64,0x10,0x9a]