[IPRA] Interprocedural Register Allocation - Transformation Pass

[vivekvpandya]

Summary

This commit adds required transformation pass for IPRA and a simple testcase to verify it.

  1) lib/Target/X86/X86RegUsageInfoPropagate.cpp (Target Specific MachineFunction Pass) to update RegMasks of call instr in caller function based on the RegMask returned by immutable pass, scheduled at Pre-RegAlloc.

[mcrosier]

Two very basic questions:
1.) Do we plan on supporting IPRA on other targets? My assumption is yes (please).
2.) Can the RegUsageInfoPropagate pass be written in a target-independent way and add target specific hooks as necessary?

[mehdi_amini]

I don't know why the pass is still X86 specific, I thought our conclusion before splitting the patch was that it is not and should be a generic pass?

The only reason it is X86 was that we thought we would have to handle calls in a target specific way, but it turned out we should be able to get away with that.

[vivekvpandya]

This commit makes IPRA transformation a target independent pass.

[mehdi_amini]

test/CodeGen/Generic/ipra-transform.ll

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(On Diff #60313)

trailing whitespace

[mehdi_amini]

lib/CodeGen/RegUsageInfoPropagate.cpp

109 ↗

(On Diff #60313)

Take a Function * as argument here, and adapt call sites.

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(On Diff #60313)

no braces

test/CodeGen/Generic/ipra-transform.ll

11 ↗

(On Diff #60313)

Add some comment in the test describing what you're checking in both cases.

[vivekvpandya]

Simple comment added in test case.

[mcrosier]

lib/CodeGen/RegUsageInfoPropagate.cpp

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(On Diff #60346)

This doesn't appear to be 80-column.

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(On Diff #60346)

MachineInstrs in a given

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(On Diff #60346)

RegisterUsageInfo.cpp -> RegisterUsageInfo

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(On Diff #60346)

of the callee

Perhaps something like:
if the RegMask information is available then this pass will update the RegMask of the call instruction.

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(On Diff #60346)

used by the register allocator while allocating the current MachineFunction.

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(On Diff #60346)

I've seen this style in the past:

#define RUIP_NAME "Register Usage Information Propagation"

and then replace the strings with the #define.

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(On Diff #60346)

return  RUIP_NAME;

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(On Diff #60346)

"Register Usage Information Propagation" -> RUIP_NAME

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(On Diff #60346)

"Register Usage Information Propagation" -> RUIP_NAME

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(On Diff #60346)

I'm not sure this comment is necessary, but I don't have any strong feelings for or against it. However, if you do decide to keep it, please write all comments using proper English prose (capitalization, puncuation, etc.).

http://llvm.org/docs/CodingStandards.html#commenting

103 ↗

(On Diff #60346)

You can reduce the indent by changing this check to:

if (!MI.isCall())
  continue;

I tend to think it also improves readability.

[mcrosier]

lib/CodeGen/RegUsageInfoPropagate.cpp

74 ↗

(On Diff #60346)

The second argument to INITIALIZE_PASS_BEGIN/END is used to specify the name of the command-line option passed to llc/opt to enable this pass. Generally, this is all lower case with dashes are used for spacing (e.g., "peephole-opt", "machine-sink", "if-converter"). We should decide upon a name that uses this convention (e.g., "reg-usage-propagation").

[vivekvpandya]

changes as suggested by @mcrosier.

[mehdi_amini]

lib/CodeGen/RegUsageInfoPropagate.cpp

118 ↗

(On Diff #60359)

No: Operand.getGlobal() already returns the Function *....
(you'll need a cast)

[mehdi_amini]

lib/CodeGen/RegUsageInfoPropagate.cpp

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(On Diff #60365)

if (!RegMask)
  return;

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(On Diff #60365)

No unsafe C-like cast, use the llvm style of casting please: cast<Function>

[mehdi_amini]

LGTM.

lib/Target/X86/CMakeLists.txt

set(sources
   X86FrameLowering.cpp
   X86ISelDAGToDAG.cpp
   X86ISelLowering.cpp
   X86InstrInfo.cpp
   X86MCInstLower.cpp
   X86MachineFunctionInfo.cpp
   X86PadShortFunction.cpp
   X86RegisterInfo.cpp
+  X86RegUsageInfoPropagate.cpp
   X86SelectionDAGInfo.cpp
   X86ShuffleDecodeConstantPool.cpp
   X86Subtarget.cpp
   X86TargetMachine.cpp
   X86TargetObjectFile.cpp
   X86TargetTransformInfo.cpp
   X86VZeroUpper.cpp
   X86FixupLEAs.cpp

lib/Target/X86/X86.h

 FunctionPass *createX86ExpandPseudoPass();
 
 /// Return a Machine IR pass that selectively replaces
 /// certain byte and word instructions by equivalent 32 bit instructions,
 /// in order to eliminate partial register usage, false dependences on
 /// the upper portions of registers, and to save code size.
 FunctionPass *createX86FixupBWInsts();
 
+/// Return a MachineFunction pass that identifies call sites
+/// and propagates register usage information of callee to caller
+/// if available with PysicalRegisterUsageInfo pass.
+FunctionPass *createRegUsageInfoPropPass();
+
 void initializeFixupBWInstPassPass(PassRegistry &);
 } // End llvm namespace
 
 #endif

lib/Target/X86/X86RegUsageInfoPropagate.cpp

+//=- X86RegUsageInfoPropagate.cpp - Register Usage Informartion Propagation -=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+///
+/// This pass is required to take advantage of the interprocedural register
+/// allocation infrastructure.
+///
+/// This pass iterates through MachineInstr in given MachineFunction and at each
+/// callsite queries RegisterUsageInfo.cpp for RegMask (calculated based on
+/// actual register allocation) of callee function, if such details found then
+/// pass will update RegMask in call instruction. This updated RegMask will be
+/// used by RegAllocators while allocating current MachineFunction.
+///
+//===----------------------------------------------------------------------===//
+
+#include "X86.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/RegisterUsageInfo.h"
+#include "llvm/IR/Module.h"
+#include "llvm/PassAnalysisSupport.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetMachine.h"
+#include <map>
+#include <string>
+
+namespace llvm {
+void initializeRegUsageInfoPropagationPassPass(PassRegistry &);
+}
+
+using namespace llvm;
+
+#define DEBUG_TYPE "ip-regalloc"
+
+namespace {
+class RegUsageInfoPropagationPass : public MachineFunctionPass {
+
+public:
+  RegUsageInfoPropagationPass() : MachineFunctionPass(ID) {
+    PassRegistry &Registry = *PassRegistry::getPassRegistry();
+    initializeRegUsageInfoPropagationPassPass(Registry);
+  }
+
+  const char *getPassName() const override {
+    return "X86 Register Usage Information Propagation";
+  }
+
+  bool runOnMachineFunction(MachineFunction &MF) override;
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override;
+
+  static char ID;
+
+private:
+  static void setRegMask(MachineInstr &MI, const uint32_t *RegMask) {
+    for (MachineOperand &MO : MI.operands()) {
+      if (MO.isRegMask())
+        MO.setRegMask(RegMask);
+    }
+  }
+};
+} // end of anonymous namespace
+char RegUsageInfoPropagationPass::ID = 0;
+
+INITIALIZE_PASS_BEGIN(RegUsageInfoPropagationPass,
+                      "RegUsageInfoPropagationPass",
+                      "X86 Register Usage Information Propagation", false,
+                      false)
+INITIALIZE_PASS_DEPENDENCY(PhysicalRegisterUsageInfo)
+INITIALIZE_PASS_END(RegUsageInfoPropagationPass, "RegUsageInfoPropagationPass",
+                    "X86 Register Usage Information Propagation", false, false)
+
+FunctionPass *llvm::createRegUsageInfoPropPass() {
+  return new RegUsageInfoPropagationPass();
+}
+
+void RegUsageInfoPropagationPass::getAnalysisUsage(AnalysisUsage &AU) const {
+  AU.addRequired<PhysicalRegisterUsageInfo>();
+  AU.setPreservesAll();
+  MachineFunctionPass::getAnalysisUsage(AU);
+}
+
+bool RegUsageInfoPropagationPass::runOnMachineFunction(MachineFunction &MF) {
+  const Module *M = MF.getFunction()->getParent();
+  PhysicalRegisterUsageInfo *PRUI = &getAnalysis<PhysicalRegisterUsageInfo>();
+
+  DEBUG(dbgs() << " ++++++++++++++++++++ " << getPassName()
+               << " ++++++++++++++++++++  \n");
+  DEBUG(dbgs() << "MachineFunction : " << MF.getName() << "\n");
+
+  bool Changed = false;
+
+  for (MachineBasicBlock &MBB : MF) {
+    for (MachineInstr &MI : MBB) {
+      // is it a call instr ?
+      if (MI.isCall()) {
+        DEBUG(dbgs()
+            << "Call Instruction Before Register Usage Info Propagation : \n");
+        DEBUG(dbgs() << MI << "\n");
+
+        auto UpdateRegMask = [&](StringRef FuncName) {
+          const auto *RegMask = PRUI->getRegUsageInfo(M->getFunction(FuncName));
+          if (RegMask) { // else skip optimization
+            setRegMask(MI, &(*RegMask)[0]);
+            Changed = true;
+          }
+        };
+
+        MachineOperand &Operand = MI.getOperand(0);
+        if (Operand.isGlobal()) {
+          UpdateRegMask(Operand.getGlobal()->getName());
+        } else if (Operand.isSymbol()) {
+          UpdateRegMask(Operand.getSymbolName());
+        }
+
+        DEBUG(dbgs()
+              << "Call Instruction After Register Usage Info Propagation : \n");
+        DEBUG(dbgs() << MI << "\n");
+      }
+    }
+  }
+
+  DEBUG(dbgs() << " +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"
+                  "++++++ \n");
+  return Changed;
+}

lib/Target/X86/X86TargetMachine.cpp

 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Target/TargetOptions.h"
 using namespace llvm;
 
 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
                                cl::desc("Enable the machine combiner pass"),
                                cl::init(true), cl::Hidden);
-
+extern cl::opt<bool> UseIPRA;
 namespace llvm {
 void initializeWinEHStatePassPass(PassRegistry &);
 }
 
 extern "C" void LLVMInitializeX86Target() {
   // Register the target.
   RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
   RegisterTargetMachine<X86TargetMachine> Y(TheX86_64Target);
void X86PassConfig::addIRPasses() {
 
   TargetPassConfig::addIRPasses();
 }
 
 bool X86PassConfig::addInstSelector() {
   // Install an instruction selector.
   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
 
+  if (UseIPRA)
+    addPass(createRegUsageInfoPropPass());
+
   // For ELF, cleanup any local-dynamic TLS accesses.
   if (TM->getTargetTriple().isOSBinFormatELF() &&
       getOptLevel() != CodeGenOpt::None)
     addPass(createCleanupLocalDynamicTLSPass());
 
   addPass(createX86GlobalBaseRegPass());
 
   return false;

test/CodeGen/Generic/ip-regalloc-simple.ll

+;;;;; ip-regallco-simple.ll
+; RUN: llc < %s | FileCheck %s -check-prefix=NOIPRA
+; RUN: llc -enable-ipra < %s | FileCheck %s
+
+
+target triple = "x86_64-unknown-unknown"
+define void @bar1() {
+  ret void
+}
+define preserve_allcc void @foo()#0 {
+; NOIPRA-LABEL: foo:
+; NOIPRA: pushq %r10
+; NOIPRA-NEXT: pushq  %r9
+; NOIPRA-NEXT: pushq  %r8 
+; NOIPRA: callq bar1
+; CHECK: foo:
+; CHECK-NOT: pushq %r10
+; CHECK-NOT: pushq %r9
+; CHECK-NOT: pushq %r8
+; CHECK: callq bar1
+  call void @bar1()
+  call void @bar2()
+  ret void
+}
+define void @bar2() {
+  ret void
+}
+attributes #0 = {nounwind}