[cpu-detection] Naming convention

[asbirlea]

Summary

Follow-up to D20926 (committed as r271595, r271596).
This patch is in preparation for a substantial refactoring of the code.

No functionality changed.

Update comment after clang format

[echristo]

One inline comment.

-eric

lib/Support/Host.cpp

189–190

Why are you changing the references to pointers?

[asbirlea]

lib/Support/Host.cpp

189–190

1. Consistency withe the above methods.
2. Planning to port the same code into compiler-rt/ as ***.c (it will address Bug 25510).

[echristo]

lib/Support/Host.cpp

189–190

I'd almost rather change the other methods :)

And I believe we can use c++ in compiler-rt - at least the sanitizers do.

[asbirlea]

lib/Support/Host.cpp

189–190

Planning to add to lib/builtins, which appears C only.
Keeping the code close to what will go in compiler-rt seemed a good idea.

[echristo]

LGTM.

Thanks!

lib/Support/Host.cpp

189–190

That seems like a good idea for now.

lib/Support/Host.cpp

static ssize_t LLVM_ATTRIBUTE_UNUSED readCpuInfo(void *Buf, size_t Size) {
   return Ret;
 }
 #endif
 
 #if defined(i386) || defined(__i386__) || defined(__x86__) ||                  \
     defined(_M_IX86) || defined(__x86_64__) || defined(_M_AMD64) ||            \
     defined(_M_X64)
 
-/// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
+/// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
 /// the specified arguments.  If we can't run cpuid on the host, return true.
-static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
+static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
                                unsigned *rECX, unsigned *rEDX) {
 #if defined(__GNUC__) || defined(__clang__)
 #if defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64)
   // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
   asm("movq\t%%rbx, %%rsi\n\t"
       "cpuid\n\t"
       "xchgq\t%%rbx, %%rsi\n\t"
       : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX)
#elif defined(_MSC_VER)
   *rECX = registers[2];
   *rEDX = registers[3];
   return false;
 #else
   return true;
 #endif
 }
 
-/// GetX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
-/// the
-/// 4 values in the specified arguments.  If we can't run cpuid on the host,
+/// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
+/// the 4 values in the specified arguments.  If we can't run cpuid on the host,
 /// return true.
-static bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
+static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
                                  unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
                                  unsigned *rEDX) {
 #if defined(__x86_64__) || defined(_M_AMD64) || defined(_M_X64)
 #if defined(__GNUC__)
   // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
   asm("movq\t%%rbx, %%rsi\n\t"
       "cpuid\n\t"
       "xchgq\t%%rbx, %%rsi\n\t"

 #else
   return true;
 #endif
 #else
   return true;
 #endif
 }
 
-static bool GetX86XCR0(unsigned *rEAX, unsigned *rEDX) {
+static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) {
 #if defined(__GNUC__)
   // Check xgetbv; this uses a .byte sequence instead of the instruction
   // directly because older assemblers do not include support for xgetbv and
   // there is no easy way to conditionally compile based on the assembler used.
   __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0));
   return false;
 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
   unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
   *rEAX = Result;
   *rEDX = Result >> 32;
   return false;
 #else
   return true;
 #endif
 }
 
-static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
-                                 unsigned &Model) {
-  Family = (EAX >> 8) & 0xf; // Bits 8 - 11
-  Model = (EAX >> 4) & 0xf;  // Bits 4 - 7
-  if (Family == 6 || Family == 0xf) {
-    if (Family == 0xf)
+static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
+                                 unsigned *Model) {
+  *Family = (EAX >> 8) & 0xf; // Bits 8 - 11
+  *Model = (EAX >> 4) & 0xf;  // Bits 4 - 7
+  if (*Family == 6 || *Family == 0xf) {
+    if (*Family == 0xf)
       // Examine extended family ID if family ID is F.
-      Family += (EAX >> 20) & 0xff; // Bits 20 - 27
+      *Family += (EAX >> 20) & 0xff; // Bits 20 - 27
     // Examine extended model ID if family ID is 6 or F.
-    Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
+    *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
   }
 }
 
 StringRef sys::getHostCPUName() {
   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
-  if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
+  if (getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
     return "generic";
   unsigned Family = 0;
   unsigned Model = 0;
-  DetectX86FamilyModel(EAX, Family, Model);
+  detectX86FamilyModel(EAX, &Family, &Model);
 
   union {
     unsigned u[3];
     char c[12];
   } text;
 
   unsigned MaxLeaf;
-  GetX86CpuIDAndInfo(0, &MaxLeaf, text.u + 0, text.u + 2, text.u + 1);
+  getX86CpuIDAndInfo(0, &MaxLeaf, text.u + 0, text.u + 2, text.u + 1);
 
   bool HasMMX = (EDX >> 23) & 1;
   bool HasSSE = (EDX >> 25) & 1;
   bool HasSSE2 = (EDX >> 26) & 1;
   bool HasSSE3 = (ECX >> 0) & 1;
   bool HasSSSE3 = (ECX >> 9) & 1;
   bool HasSSE41 = (ECX >> 19) & 1;
   bool HasSSE42 = (ECX >> 20) & 1;
   bool HasMOVBE = (ECX >> 22) & 1;
   // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
   // indicates that the AVX registers will be saved and restored on context
   // switch, then we have full AVX support.
   const unsigned AVXBits = (1 << 27) | (1 << 28);
-  bool HasAVX = ((ECX & AVXBits) == AVXBits) && !GetX86XCR0(&EAX, &EDX) &&
+  bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
                 ((EAX & 0x6) == 0x6);
   bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
   bool HasLeaf7 =
-      MaxLeaf >= 0x7 && !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
+      MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
   bool HasADX = HasLeaf7 && ((EBX >> 19) & 1);
   bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20);
   bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1);
 
-  GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
+  getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
   bool Em64T = (EDX >> 29) & 0x1;
   bool HasTBM = (ECX >> 21) & 0x1;
 
   if (memcmp(text.c, "GenuineIntel", 12) == 0) {
     switch (Family) {
     case 3:
       return "i386";
     case 4:

 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
   unsigned MaxLevel;
   union {
     unsigned u[3];
     char c[12];
   } text;
 
-  if (GetX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) ||
+  if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) ||
       MaxLevel < 1)
     return false;
 
-  GetX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
+  getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX);
 
   Features["cmov"] = (EDX >> 15) & 1;
   Features["mmx"] = (EDX >> 23) & 1;
   Features["sse"] = (EDX >> 25) & 1;
   Features["sse2"] = (EDX >> 26) & 1;
   Features["sse3"] = (ECX >> 0) & 1;
   Features["ssse3"] = (ECX >> 9) & 1;
   Features["sse4.1"] = (ECX >> 19) & 1;
   Features["sse4.2"] = (ECX >> 20) & 1;
 
   Features["pclmul"] = (ECX >> 1) & 1;
   Features["cx16"] = (ECX >> 13) & 1;
   Features["movbe"] = (ECX >> 22) & 1;
   Features["popcnt"] = (ECX >> 23) & 1;
   Features["aes"] = (ECX >> 25) & 1;
   Features["rdrnd"] = (ECX >> 30) & 1;
 
   // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
   // indicates that the AVX registers will be saved and restored on context
   // switch, then we have full AVX support.
   bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) &&
-                    !GetX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
+                    !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6);
   Features["avx"] = HasAVXSave;
   Features["fma"] = HasAVXSave && (ECX >> 12) & 1;
   Features["f16c"] = HasAVXSave && (ECX >> 29) & 1;
 
   // Only enable XSAVE if OS has enabled support for saving YMM state.
   Features["xsave"] = HasAVXSave && (ECX >> 26) & 1;
 
   // AVX512 requires additional context to be saved by the OS.
   bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0);
 
   unsigned MaxExtLevel;
-  GetX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
+  getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
 
   bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
-                     !GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
+                     !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
   Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1);
   Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1);
   Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1);
   Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave;
   Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave;
   Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
   Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
 
   bool HasLeaf7 =
-      MaxLevel >= 7 && !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
+      MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
 
   // AVX2 is only supported if we have the OS save support from AVX.
   Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1);
 
   Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1);
   Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1);
   Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1);
   Features["hle"] = HasLeaf7 && ((EBX >> 4) & 1);
bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
   Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
 
   Features["prefetchwt1"] = HasLeaf7 && (ECX & 1);
   Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
   // Enable protection keys
   Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);
 
   bool HasLeafD = MaxLevel >= 0xd &&
-                  !GetX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
+                  !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
 
   // Only enable XSAVE if OS has enabled support for saving YMM state.
   Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1);
   Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1);
   Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1);
 
   return true;
 }