[IPRA] Interprocedural Register Allocation - Analysis Passes

[vivekvpandya]

Summary

 This commit addes pass to change CodeGen order to be bottom up order on Call Graph. The patch for the same has been provided by dear Mehdi Amini.
 
	This commit added required analysis passes for IPRA.
 
 1) lib/CodeGen/RegUsageInfoCollector.cpp (MachineFunction Pass) to create RegMask based on actual register usage, scheduled at POST-RA
 2) lib/CodeGen/RegisterUsageInfo.cpp (Immutable Pass) to store RegMask details for functions which has been processed in bottom up order on Call Graph, Scheduled before RegAllocation.
   
 This commit also adds a method setRegMask() to MachineOperand class.
 This commit also adds command line option to enable IPRA -enable-ipra and debug type "ip-regalloc".
 Changes to adher to coding standards, correction for ownership of RegMask vector in related functions.

[mehdi_amini]

include/llvm/CodeGen/MachineOperand.h

537

Take a const ptr.

include/llvm/CodeGen/PhysicalRegisterUsageInfo.h

37

You need to do the same in RegUsageInfoPropagationPass

44

Take RegMasks by value here.

46

const std::vector<uint32_t> *getRegUsageInfo(StringRef MFName);

lib/CodeGen/PhysicalRegisterUsageInfo.cpp

33

RegMasks[MFName] = std::move(RegMask);

lib/CodeGen/RegUsageInfoCollector.cpp

100

PRUI->storeUpdateRegUsageInfo(MF.getName(), std::move(RegMask));

lib/CodeGen/TargetPassConfig.cpp

587

remove

603

Remove this, it is useless.

lib/Target/X86/X86RegUsageInfoPropagate.cpp

57

Take a const ptr

93

C++11 for-range:

for(auto &MBB : MF) {
  for(auto &MI : MBB) {

114

auto updateRegMask = [&](StringRef FuncName) {
  const auto *RegMask = PRUI->getRegUsageInfo(FuncName);
  if (RegMask) { // else skip optimization
    setRegMask(MI, &(*RegMask)[0]);
    changed = true;
  }
};
MachineOperand &Operand = MI.getOperand(0);
if (Operand.isGlobal()) {
  updateRegMask(Operand.getGlobal()->getName());
} else if (Operand.isSymbol()) {
  updateRegMask(Operand.getGlobal()->getName());
}

lib/Target/X86/X86TargetMachine.cpp

316

This is not the right place, it should be added right after createX86ISelDag

[vivekvpandya]

Changes to adher to coding standards, correction for ownership of RegMask vector in related functions.

[mehdi_amini]

include/llvm/CodeGen/PhysicalRegisterUsageInfo.h

29

This is not clang-formatted, can you please format it?

[vivekvpandya]

Files have been formatted with clang-format.

[mehdi_amini]

include/llvm/CodeGen/MachineOperand.h

146

It is not good practice to clang-format the whole file as part of your patch. You should only format the patch of the file you changed (git clang-format handles it automatically, some text editor as well, or you can give a range on the command line, or even copy paster on stdin the range you want to format).

[mehdi_amini]

lib/CodeGen/TargetPassConfig.cpp

514

Looks like we'll need a home for this pass, can't really leave it there. I'm not sure where to put it yet.

529

Are these dependency required?

[vivekvpandya]

Fix that makes RegUsageInfoCollector Calling Convention aware so that it does not mark CalleeSaved register as clobbered if it is not used.

[qcolombet]

Hi Vivek,

A couple of minor comments, the main logic looks reasonable.

Cheers,
-Quentin

include/llvm/CodeGen/MachineOperand.h

535

I would say in a comment to double check MachineOperand::CreateRegMask for the characteristic of RegMaskPtr.

The reason why I think it is important is because that method clearly states the expected life time of the pointer and if we get it wrong we may end with nasty bug. Therefore, we should do our best to have the API clearly documented.

include/llvm/CodeGen/Passes.h

205

Typo: machine

include/llvm/CodeGen/PhysicalRegisterUsageInfo.h

2

.cpp => .h

3

Wrapped line.

52

Period.

52

Please use doxygen style comment: ///

53

Typo: function

54

Period

include/llvm/InitializePasses.h

342

I don’t know why this is not the case for last one, but we usually sort the initializers by name.

lib/CodeGen/CMakeLists.txt

104

Looks like this patch could be split:

• One patch for RegisterUsageInfo.
• One patch for InfoCollector.

lib/CodeGen/PhysicalRegisterUsageInfo.cpp

28

ip-regalloc

46

Remove the else per the coding convention.

lib/CodeGen/RegUsageInfoCollector.cpp

17

Wrapping is strange here.
We split in the middle of a sentence without hitting the 80-col limit.

82

Call getPassName.

88

That is a bit strange to state the comment like that.
What about: Compute the size of the bit vector to represent all the registers. The bit vector is broken into 32-bit chunks, thus takes the ceil of the number of registers divided by 32 for the size.

95

&& instead of nested ifs.

96

Period.

98

Encapsulate that loop into a setRegister thing.

107

Capital letter at the beginning, period at the end of the sentence.

lib/Target/X86/X86RegUsageInfoPropagate.cpp

3

Why is that pass X86 specific?
It should be generic, right?

13

Use doxygen comments: ///

17

queries

[mehdi_amini]

Somehow I had unsubmitted comments on phab, some are still relevant.

lib/CodeGen/PhysicalRegisterUsageInfo.cpp

3

This should be on one line (and fits within 80 chars).

lib/CodeGen/RegUsageInfoCollector.cpp

3

same

38

Doesn't this need to be in a header and be called somewhere?
It's not clear to me how is this pass registered?

110

Why not initializing RegMask with 0xFFFFFFFF in resize() and having the loop setting the bit to zero instead?

116

comment

lib/CodeGen/TargetPassConfig.cpp

539

No capital letters here.

621

s/register/registers/

622

Comment could be simply: Collect register usage information and produce a register mask of clobbered registers, to be used to optimize call sites.

lib/Target/X86/X86.h

86

s/call site/call sites/

lib/Target/X86/X86RegUsageInfoPropagate.cpp

3

When we first looked at it, is seemed to me that we would have to switch over the various possible calls. But it was a mistake on my side, and now that it is implemented it does not seem to need any target specific bit indeed.

[MatzeB]

The general approach seems fine at a first glance. I haven't reviewed this in-depth for correctness yet though, as I first have a bunch of nit-picks and coding style issues:

include/llvm/CodeGen/MachineOperand.h

535

+1

include/llvm/CodeGen/PhysicalRegisterUsageInfo.h

2

Does all of this need to be exposed in a public header anyway? Wouldn't it be enough to have the initialization stuff in Passes.h and keep the actual pass definitions private to the .cpp file in this case?

(if we decide no, then I'd rename this to something shorter like RegisterUsageInfo...)

12–18

Should use doxygen style comment here (see coding convention). It may also be wise not to mention specific filenames here as those could be moved or renamed in the future and people generally do not catch comment like this when doing so.

55

@Mehdi: I've seen you arguing for a stringmap here before, but I would argue that a reference to a compiler internal object would be more stable here, avoid string comparisons and also work with unnamed functions (not sure if that actually allowed in llvm, but I could see this happening for JITs...).

As to what object to use: MachineFunction* would be nice but I am not sure that would well as long as the MachineFunction gets created in the MachineFunctionAnalysisPass. So maybe tie it to the Functions GlobalObject for now and change it to MachineFunction* later when we switch to the new pass manager and hopefully can deal with MachineFunctions as a first-class object rather than an analysis.

59

Check your editor settings so the newline at the end of file is added.

lib/CodeGen/PhysicalRegisterUsageInfo.cpp

2–3

strange linebreak. I think in .cpp we also don't need those magic markers for the emacs users (my understanding is that they are just used in the .h files so emacs knows they contain C++ code and not just C code).

12–18

Use doxygen comments.

lib/CodeGen/RegUsageInfoCollector.cpp

2–3

strange linebreak.

12–20

doxygen comments.

56

add "end of anonymous namespace" comment (see coding conventions).

61

It is clear that this is about a pass so no need for the " Pass" suffix in the explanation.

77

This is always false anyway, just use return false; instead of a variable.

88

We could make the code here and in MachineOperand more robust by having a "typedef uint32_t RegMaskType" and then using sizeof(RegMaskType) * CHAR_BIT instead of hardcoding 32...
Though as that also hits existing code in MachineOperand a separate patch would be warranted.

89

how about uint32_t RegMask[regMaskSize] instead of using a std::vector here so we get a stack allocation instead of an unnecessary heap allocation of the vector?

93

We tend to introduce a new variable (like PRegE = TRI->getNumRegs()) in loops like this and compare with it to avoid getNumRegs() getting called in every iteration of the loop (see coding conventions).

112

No space after the *

lib/CodeGen/TargetPassConfig.cpp

138

I feel like this comment is just stating the very obvious and can be left out.

140

I think we can should add cl::Hidden for now until this is proven and stable.

514

Looks like we'll need a home for this pass, can't really leave it there. I'm not sure where to put it yet.

Just put the pass into CallGraphSCCPass.h as it is not specific to codegen (just happens to be used
there)?

lib/Target/X86/X86RegUsageInfoPropagate.cpp

94

for(auto &MBB : MF) {
for(auto &MI : MBB) {

Please do not use auto in contexts where it is not obvious what type it represents. It is friendlier for the readers to use MachineBasicBlock &MBB and MachineInstr &MI here.

102

We start local variables with uppercase letters (coding convention).

104–105

same comment as above.

115

This does not seem complicated enough to me to warrant a lambda. What about:

const char *FuncName = nullptr;
if (Operand.isGlobal()) {
  Name = Operand.getGlobal()->getName();
} else if (Operand.isSymbol()) {
  Name = Operand.getGlobal()->getName();
}
if (FuncName != nullptr && RegMask) {
  setRegMask(MI, &(*RegMask)[0]);
  changed = true;
}

129–130

odd line break (clang-format may be confused because of the macro...)

132–133

`DEBUG(dbgs() << MI << '\n');

[MatzeB]

@Mehdi: explicit ping so you do not miss my comment about the register mask map modeling among all the nitpicks.

[mehdi_amini]

include/llvm/CodeGen/PhysicalRegisterUsageInfo.h

55

I pointed a StringMap in order to not have the backend depends on the IR, now if you and Quentin thinks it is fine to go through a GlobalVariable *, I don't have strong feeling about it.
(and yes, unnamed global function are allowed)

[mehdi_amini]

lib/Target/X86/X86RegUsageInfoPropagate.cpp

94

I feel that it is clearly obvious that MI is a MachineInstr when reading for(auto &MI : MBB) {, I'll be explicit if it was something else. But I won't pick this fight :)

115

I guess it is a matter of personal style, I'd try to avoid this construct when possible, but I don't really care here.

[llvm-commits]

I know some of the issues are more a matter of personal preference than there being one true way. I just felt I should point out how I feel about them before people start writing them down as the one true way in the coding conventions :) I will of course not block the patches if we end up with a different style here.

[hfinkel]

lib/CodeGen/PhysicalRegisterUsageInfo.cpp

12

No need to duplicate this comment in both the source file and the header.

lib/CodeGen/RegUsageInfoCollector.cpp

89

regMaskSize is not a constant, and we can't use VLAs. We could use SmallVector with a reasonable default, however.

lib/CodeGen/TargetPassConfig.cpp

620

Why here? It seems much too early. Backends can use the register scavenger to use otherwise-unused registers until the very end. I think this needs to be after the call below to:

addPreEmitPass();

if not at the very end.

lib/Target/X86/X86TargetMachine.cpp

284

Does this need to be here so that targets can opt-in? Could we reasonably schedule this early in TargetPassConfig::addMachinePasses?

[hfinkel]

include/llvm/CodeGen/PhysicalRegisterUsageInfo.h

11–12

How about:

// This pass is required to take advantage of the interprocedural-register-allocation infrastructure.

16

If you change from using a StringMap, update this comment.

55

I'd also prefer a GlobalVariable * here, as that currently establishes our canonical function identify. If we work to further separate the MI level from the IR level, I suspect we'd establish some other function object which would have pointer-based identify, and we can always then update this code to use that instead.

[mehdi_amini]

include/llvm/CodeGen/PhysicalRegisterUsageInfo.h

55

Since MatzeB commented about the allocation in std::vector in the MachineFunctionPass, it seems equally important to override doInitialization(Module &M) in order to reserve the size of the map with the number of functions defined in the module, and doFinalization to clear the map.
(clearing the map is actually a correctness issue)

lib/CodeGen/RegUsageInfoCollector.cpp

89

What is regMaskSize on ARM and X86?
Before moving on with stack allocation here, I think we have to consider that:

• First this is ran once per function, so having one malloc per function during codegen does not make it an expensive analysis.
• Second the vector will be moved in the immutable pass map. So having a SmallVector makes it less inefficient to move and store (we may not want to have a DenseMap anymore, and thus we'd have to make an extra malloc there!).

[vivekvpandya]

include/llvm/CodeGen/MachineOperand.h

146

I will consider it, do we required to revert those changes ? If yes then please suggest easy way, I am using git.

include/llvm/CodeGen/PhysicalRegisterUsageInfo.h

29

Actually I run git clang-format , but that was after committing my changes so it did not changed any thing. I have applied clang-format on each file.

lib/CodeGen/CMakeLists.txt

104

@qcolombet Could you please explain why is that required?

lib/CodeGen/PhysicalRegisterUsageInfo.cpp

2–3

oh yes this is already mentioned in coding standards but I really didn't check for it.
Sorry.

lib/CodeGen/RegUsageInfoCollector.cpp

38

Isn't this will be called by method generated due to macroINITIALIZE_PASS_BEGIN ?

lib/CodeGen/TargetPassConfig.cpp

514

Have thought of any thing for this?

529

I believe CallGraphWrapperPass is required, though I have not look at this code closely as it was given by you :D

529

No these dependencies are not required, I am yet to find why not technically but I just removed it and compiled llvm again and things are working.

lib/Target/X86/X86RegUsageInfoPropagate.cpp

102

I thought it is not for primitive type. I will change it.

[mehdi_amini]

include/llvm/CodeGen/PhysicalRegisterUsageInfo.h

31

git clang-format takes a commit range, so you can format patches that are already committed.
(i.e, git clang-format HEAD~ formats the last commit, you can just amend it afterward)

lib/CodeGen/RegUsageInfoCollector.cpp

38

If there is something in the macro expansion that makes you think it is called, please elaborate.

[vivekvpandya]

lib/CodeGen/RegUsageInfoCollector.cpp

38

No, I look carefully at that macro it provides definition for initialize.. method but yes some where we need to call that method. Also I haven't mentioned this pass as dependency for any other pass with INITIALIZE_PASS_DEPENDENCY other wise it can call that function. Now I am also having same question as you.

[vivekvpandya]

lib/Target/X86/X86TargetMachine.cpp

284

@hfinkel X86RegUsageInfoPropagate.cpp will be generic pass soon then I will do this change too.

[vivekvpandya]

Correction in typos , more adhering to coding standards.
PhysicalRegisterUsageInfo.cpp -> RegisterUsageInfo.cpp
DenseMap of GlobelVariable * to RegMask is used instead of StringMap.
DummyCGSCCPass moved to CallGraphSCCPass.h and .cpp

[mehdi_amini]

We're getting there, the patch is looking really good now! :)

Still a little bit of work ahead, see inline comments.

include/llvm/Analysis/CallGraphSCCPass.h

115 ↗

(On Diff #59263)

Describe the class with a doxygen comment.

include/llvm/CodeGen/MachineOperand.h

535

Do not repeat the name of the function in the doxygen comment (other places that do it are outdated).

include/llvm/CodeGen/Passes.h

205

s/used/preserved/

include/llvm/CodeGen/RegisterUsageInfo.h

13 ↗

(On Diff #59263)

You shouldn't introduce implementation details in high-level description.

lib/CodeGen/CMakeLists.txt

103–105

It is a good practice to decoupled software component. Having separate patches helps to make sure we indeed have correctly separated the components.
It also forces to make sure the component are individually testable, and make sure we actually test them.

So I agree with Quentin on the principle, and I think it is also a good exercise for you to split the patch an submit the analysis alone and tested. Have a look at "CostModelAnalysis::print()" in lib/Analysis/CostModel.cpp and see how it is tested in test/Analysis/CostModel/X86/cast.ll

lib/CodeGen/RegUsageInfoCollector.cpp

12

Wrapping

lib/CodeGen/TargetPassConfig.cpp

140

Why "compile time"? I'd just write "Enable inter-procedural register allocation"

528

You forgot to remove this hunk

[vivekvpandya]

lib/CodeGen/CMakeLists.txt

103–105

@mehdi_amini I understand what you explain above but here I think RegisterUsageInfo is not tastable alone because it just holds RegMasks, RegisterInfoCollector is a trigger to IP regalloc and both of them can be tested together. Also to test X86RegUsageInfoPropagate it requires both of the above mentioned passes. But we can separate patches for RegisterUsageInfo + InfoCollector and X86RegUsageInfoPropagate ( condition that first patch is required to test second one) .
Is there any better plan in your mind?

[mehdi_amini]

lib/CodeGen/CMakeLists.txt

103–105

Splitting in two is what I had in mind: the analysis part on one side, the transformation part on another.

[vivekvpandya]

lib/CodeGen/CMakeLists.txt

103–105

Just to make sure RegisterUsageInfo.cpp and RegUsageInfoCollector.cpp both are part of analysis so there is not need of separate patch for them but I will separate changes related to X86RegUsageInfoPropagate.cpp in other patch.

[vivekvpandya]

@mehdi_amini I have made all suggested changes , I am writing a simple test for RegUsageInfoCollector so that next review you can also look at that. Thanks for your patience.

[vivekvpandya]

patch is splited into analysis and optimization pass. Simple test cases has been added.

[mehdi_amini]

include/llvm/CodeGen/RegisterUsageInfo.h

49 ↗

(On Diff #59669)

add a method print() like other analysis, and call it here behind a flag.

54 ↗

(On Diff #59669)

Doxygen

57 ↗

(On Diff #59669)

Doxygen

test/CodeGen/Generic/reg-usage-info.ll

2 ↗

(On Diff #59669)

I don't like that we can't pass the test in release mode. I suggested that the dump occurs in doFinalization() for the analysis pass (i.e. PhysicalRegisterUsageInfo). You need to implement a proper cl::opt that controls a dump there, that could be used in release mode.

4 ↗

(On Diff #59669)

I'm worried that we don't provide any stability guarantee on the numbers printed here.
Having a nicer textual form would be better.
I just don't see how to do it other than keep a pointer to the TRI in the DenseMap in the immutable pass to be able to get the register name.

[vivekvpandya]

test/CodeGen/Generic/reg-usage-info.ll

2 ↗

(On Diff #59669)

Aren't we refering

RegUsageInfoCollector

as analysis pass,

RegisterUsageInfo

is there for keeping data around.

4 ↗

(On Diff #59669)

If RegUsageInfoCollector is considered as analysis pass then we can add cl::opt into that file and have analysis printed from that.

[mehdi_amini]

test/CodeGen/Generic/reg-usage-info.ll

2 ↗

(On Diff #59669)

Technically in LLVM the analysis is the pass that you require and query the result from (i.e. a pass you're using as getAnalysis()). But yeah terminology can be fuzzy.

[vivekvpandya]

test/CodeGen/Generic/reg-usage-info.ll

2 ↗

(On Diff #59669)

SO What is your suggestion? Which file should be changed?

[mehdi_amini]

test/CodeGen/Generic/reg-usage-info.ll

2 ↗

(On Diff #59669)

I think I already told you: the way analysis are tested at the IR level is using the -analyze flag in opt. Since we don't have -analyze in llc, the closest I can imagine is to implement the analysis (in the LLVM sense) with the "print(...)" method as other analyses, and call it in doFinalization() when a cl::opt flag is set.

[vivekvpandya]

test/CodeGen/Generic/reg-usage-info.ll

4 ↗

(On Diff #59669)

Will TRI pointer assigned a value by the MachineFunction pass ? Or Is there any way to get TargetMachine or TargetRegisterInfo from Module object? Also if PReg name is required to be printed then MCRegisterInfo will be required.

[vivekvpandya]

a new command line option dump-regusage has been added so that reg usage information can be printed in release build. The test case is also changed accordingly.

[mehdi_amini]

include/llvm/CodeGen/RegisterUsageInfo.h

51 ↗

(On Diff #59753)

Is the TRI dependent on the Target or the SubTarget?
If it is the latter, it can change on each function and thus needs to be in the map (at which point we better have a dedicated class for the map value)

56 ↗

(On Diff #59753)

Same question.

lib/CodeGen/RegisterUsageInfo.cpp

24 ↗

(On Diff #59753)

I'm not sure the name of the option is great, but I'll leave the naming to Quentin/Matthias.

49 ↗

(On Diff #59753)

Can you implement the print in a separate print method with the same signature as the other analyses for consistency?
And call it from here being the DumpRegUsage flag?

[mehdi_amini]

lib/CodeGen/RegUsageInfoCollector.cpp

129

Mdl is not usual, M alone is more common (or sometimes Mod)

[vivekvpandya]

lib/CodeGen/RegUsageInfoCollector.cpp

129

Ok I will take care for naming , but that would be not required if we are going with Function * , because MF.getFunction() would be enough.

[mehdi_amini]

lib/CodeGen/RegUsageInfoCollector.cpp

131

This is not the right API: getNamedGlobal is for global *variables*, not function.

lib/CodeGen/RegisterUsageInfo.cpp

56 ↗

(On Diff #59753)

Add an assertion that MFGlobalVar is not null (and the name isn't very explicit)

[vivekvpandya]

lib/CodeGen/RegisterUsageInfo.cpp

56 ↗

(On Diff #59753)

now I think such assertion wold be for Function *, right ?

[vivekvpandya]

lib/CodeGen/RegUsageInfoCollector.cpp

131

I tried out

PRUI->storeUpdateRegUsageInfo(Mdl->getGlobalVariable(MF.getFunction()->getName(),true), std::move(RegMask));

and

PRUI->storeUpdateRegUsageInfo(Mdl->getGlobalVariable(MF.getFunction()->getName()), std::move(RegMask));

but both returns nullptr for some functions.

[mehdi_amini]

lib/CodeGen/RegUsageInfoCollector.cpp

131

My previous comment called out the fact that you were using an API for global *variables* instead of function, and you replaced with a call to getGlobalVariable?

There is a getFunction() API on the module that returns only functions, or there is a getNamedValue() that will return any symbol.

However you have MF.getFunction(), so you should not call any of these.

[vivekvpandya]

RegMasks uses Function * as key, print method and TargetMachine * have added to RegisterUsageInfo. Command line option -dump-regusage has been renamed to -print-regusage, test case is also updated to reflect the changes.

[mehdi_amini]

lib/CodeGen/RegisterUsageInfo.cpp

65 ↗

(On Diff #59909)

pair is not coding-convention friendly.

Also you are iterating on a map that is keyed on pointer values, which does not provided any ordering guarantee. Even with names as keys, the map is unordered anyway.
You need to generate a vector and sort it first.

test/CodeGen/Generic/reg-usage-info.ll

39 ↗

(On Diff #59909)

This test is not OK, for the reasons I explained when I provided the other test (stability).

[vivekvpandya]

Test case changed to simple test case which is originally provided by Mehdi Amini, print() now sorts analysis details before printing in RegisterUsageInfo.cpp

[mehdi_amini]

lib/CodeGen/RegUsageInfoCollector.cpp

93

I think MatzeB mentioned that TRI is a subclass of MCRI, so I'm not sure why you're using MCRI at all while you have TRI.

124

Why aren't you using MachineOperand::clobbersPhysReg here?

test/CodeGen/Generic/reg-usage-info.ll

8 ↗

(On Diff #60003)

What will be printed for bar1 and bar2?
Add the CHECK lines here.

[vivekvpandya]

git clang-formated , test case changes, MCRI is not required , clobberedReg expression removed.

[mehdi_amini]

include/llvm/CodeGen/RegisterUsageInfo.h

58–59 ↗

(On Diff #60158)

Doxygen the two public API above.

lib/CodeGen/RegUsageInfoCollector.cpp

80

No braces

lib/CodeGen/RegisterUsageInfo.cpp

72 ↗

(On Diff #60158)

No braces.

lib/CodeGen/TargetPassConfig.cpp

541

No braces

676

No braces

[mehdi_amini]

test/CodeGen/Generic/reg-usage-info.ll

15 ↗

(On Diff #60158)

trailing whitespace here.

[qcolombet]

Hi Vivek,

I was thinking about debug ability and usability of the produced code.
Something to consider in a following patch would be to add in the assembly output comments at the beginning of the function and/or related call site of the function listing what are the register preserved by the function.

The rationale is that now if we play with assembly files produced by different optimization phase, we want a quick way to check if two functions are equivalent.
E.g.,
Let say we have two assembly files produced for the same application:

• bad.s which fails, produced with ipra
• good.s which works, produced without ipra

When bisecting which function causes the failure, it is important to know if it is fine to take a function foo from good.s and replace it into bad.s. This may not be possible if the preserve register are not compatible.

Cheers,
-Quentin

[vivekvpandya]

@qcolombet. It will be very help full, I will look into that. Do we need to keep it default or a separate switch to get those comments ?

[mehdi_amini]

LGTM, with one inline comment.

include/llvm/CodeGen/RegisterUsageInfo.h

59 ↗

(On Diff #60189)

Strip the "this method is provided to" everywhere.
And here add that it will return null if the function is not known.

[vivekvpandya]

inline-asm related test case added Thanks to Mehdi Amini, and previous test case modified so that it do not fail due to transformation pass for IPRA.

[mehdi_amini]

Do you have commit access?

[vivekvpandya]

No I do not have commit access.

include/llvm/CodeGen/MachineOperand.h

private:
   /// not a real instruction.  Such uses should be ignored during codegen.
   bool IsDebug : 1;
 
   /// SmallContents - This really should be part of the Contents union, but
   /// lives out here so we can get a better packed struct.
   /// MO_Register: Register number.
   /// OffsetedInfo: Low bits of offset.
   union {
-    unsigned RegNo;           // For MO_Register.
-    unsigned OffsetLo;        // Matches Contents.OffsetedInfo.OffsetHi.
+    unsigned RegNo;    // For MO_Register.
+    unsigned OffsetLo; // Matches Contents.OffsetedInfo.OffsetHi.
   } SmallContents;
 
   /// ParentMI - This is the instruction that this operand is embedded into.
   /// This is valid for all operand types, when the operand is in an instr.
   MachineInstr *ParentMI;
 
   /// Contents union - This contains the payload for the various operand types.
   union {
     MachineBasicBlock *MBB;  // For MO_MachineBasicBlock.
     const ConstantFP *CFP;   // For MO_FPImmediate.
     const ConstantInt *CI;   // For MO_CImmediate. Integers > 64bit.
     int64_t ImmVal;          // For MO_Immediate.
     const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
     const MDNode *MD;        // For MO_Metadata.
     MCSymbol *Sym;           // For MO_MCSymbol.
     unsigned CFIIndex;       // For MO_CFI.
 
-    struct {                  // For MO_Register.
+    struct { // For MO_Register.
       // Register number is in SmallContents.RegNo.
-      MachineOperand *Prev;   // Access list for register. See MRI.
+      MachineOperand *Prev; // Access list for register. See MRI.
       MachineOperand *Next;
     } Reg;
 
     /// OffsetedInfo - This struct contains the offset and an object identifier.
     /// this represent the object as with an optional offset from it.
     struct {
       union {
-        int Index;                // For MO_*Index - The index itself.
-        const char *SymbolName;   // For MO_ExternalSymbol.
-        const GlobalValue *GV;    // For MO_GlobalAddress.
-        const BlockAddress *BA;   // For MO_BlockAddress.
+        int Index;              // For MO_*Index - The index itself.
+        const char *SymbolName; // For MO_ExternalSymbol.
+        const GlobalValue *GV;  // For MO_GlobalAddress.
+        const BlockAddress *BA; // For MO_BlockAddress.
       } Val;
       // Low bits of offset are in SmallContents.OffsetLo.
-      int OffsetHi;               // An offset from the object, high 32 bits.
+      int OffsetHi; // An offset from the object, high 32 bits.
     } OffsetedInfo;
   } Contents;
 
   explicit MachineOperand(MachineOperandType K)
       : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {}
+
 public:
   /// getType - Returns the MachineOperandType for this operand.
   ///
   MachineOperandType getType() const { return (MachineOperandType)OpKind; }
 
-  unsigned getTargetFlags() const {
-    return isReg() ? 0 : SubReg_TargetFlags;
-  }
+  unsigned getTargetFlags() const { return isReg() ? 0 : SubReg_TargetFlags; }
   void setTargetFlags(unsigned F) {
     assert(!isReg() && "Register operands can't have target flags");
     SubReg_TargetFlags = F;
     assert(SubReg_TargetFlags == F && "Target flags out of range");
   }
   void addTargetFlag(unsigned F) {
     assert(!isReg() && "Register operands can't have target flags");
     SubReg_TargetFlags |= F;
     assert((SubReg_TargetFlags & F) && "Target flags out of range");
   }
 
-
   /// getParent - Return the instruction that this operand belongs to.
   ///
   MachineInstr *getParent() { return ParentMI; }
   const MachineInstr *getParent() const { return ParentMI; }
 
   /// clearParent - Reset the parent pointer.
   ///
   /// The MachineOperand copy constructor also copies ParentMI, expecting the
void setSubReg(unsigned subReg) {
     assert(SubReg_TargetFlags == subReg && "SubReg out of range");
   }
 
   /// substVirtReg - Substitute the current register with the virtual
   /// subregister Reg:SubReg. Take any existing SubReg index into account,
   /// using TargetRegisterInfo to compose the subreg indices if necessary.
   /// Reg must be a virtual register, SubIdx can be 0.
   ///
-  void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&);
+  void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo &);
 
   /// substPhysReg - Substitute the current register with the physical register
   /// Reg, taking any existing SubReg into account. For instance,
   /// substPhysReg(%EAX) will change %reg1024:sub_8bit to %AL.
   ///
-  void substPhysReg(unsigned Reg, const TargetRegisterInfo&);
+  void substPhysReg(unsigned Reg, const TargetRegisterInfo &);
 
   void setIsUse(bool Val = true) { setIsDef(!Val); }
 
   void setIsDef(bool Val = true);
 
   void setImplicit(bool Val = true) {
     assert(isReg() && "Wrong MachineOperand accessor");
     IsImp = Val;
public:
   static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
     // See TargetRegisterInfo.h.
     assert(PhysReg < (1u << 30) && "Not a physical register");
     return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
   }
 
   /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
   bool clobbersPhysReg(unsigned PhysReg) const {
-     return clobbersPhysReg(getRegMask(), PhysReg);
   }
 
   /// getRegMask - Returns a bit mask of registers preserved by this RegMask
   /// operand.
   const uint32_t *getRegMask() const {
     assert(isRegMask() && "Wrong MachineOperand accessor");
     return Contents.RegMask;
   }
void setIndex(int Idx) {
     Contents.OffsetedInfo.Val.Index = Idx;
   }
 
   void setMBB(MachineBasicBlock *MBB) {
     assert(isMBB() && "Wrong MachineOperand accessor");
     Contents.MBB = MBB;
   }
 
+  void setRegMask(const uint32_t *RegMaskPtr) {
+    assert(isRegMask() && "Wrong MachineOperand mutator");
+    Contents.RegMask = RegMaskPtr;
+  }
+
   //===--------------------------------------------------------------------===//
   // Other methods.
   //===--------------------------------------------------------------------===//
 
   /// isIdenticalTo - Return true if this operand is identical to the specified
   /// operand. Note: This method ignores isKill and isDead properties.
   bool isIdenticalTo(const MachineOperand &Other) const;
 
static MachineOperand CreateFPImm(const ConstantFP *CFP) {
     Op.Contents.CFP = CFP;
     return Op;
   }
 
   static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
                                   bool isKill = false, bool isDead = false,
                                   bool isUndef = false,
                                   bool isEarlyClobber = false,
-                                  unsigned SubReg = 0,
-                                  bool isDebug = false,
+                                  unsigned SubReg = 0, bool isDebug = false,
                                   bool isInternalRead = false) {
     assert(!(isDead && !isDef) && "Dead flag on non-def");
     assert(!(isKill && isDef) && "Kill flag on def");
     MachineOperand Op(MachineOperand::MO_Register);
     Op.IsDef = isDef;
     Op.IsImp = isImp;
     Op.IsKill = isKill;
     Op.IsDead = isDead;
public:
   static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
                                           unsigned char TargetFlags = 0) {
     MachineOperand Op(MachineOperand::MO_TargetIndex);
     Op.setIndex(Idx);
     Op.setOffset(Offset);
     Op.setTargetFlags(TargetFlags);
     return Op;
   }
-  static MachineOperand CreateJTI(unsigned Idx,
-                                  unsigned char TargetFlags = 0) {
+  static MachineOperand CreateJTI(unsigned Idx, unsigned char TargetFlags = 0) {
     MachineOperand Op(MachineOperand::MO_JumpTableIndex);
     Op.setIndex(Idx);
     Op.setTargetFlags(TargetFlags);
     return Op;
   }
   static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
                                  unsigned char TargetFlags = 0) {
     MachineOperand Op(MachineOperand::MO_GlobalAddress);
public:
   static MachineOperand CreateCFIIndex(unsigned CFIIndex) {
     MachineOperand Op(MachineOperand::MO_CFIIndex);
     Op.Contents.CFIIndex = CFIIndex;
     return Op;
   }
 
   friend class MachineInstr;
   friend class MachineRegisterInfo;
+
 private:
   void removeRegFromUses();
 
   //===--------------------------------------------------------------------===//
   // Methods for handling register use/def lists.
   //===--------------------------------------------------------------------===//
 
   /// isOnRegUseList - Return true if this operand is on a register use/def list
   /// or false if not.  This can only be called for register operands that are
   /// part of a machine instruction.
   bool isOnRegUseList() const {
     assert(isReg() && "Can only add reg operand to use lists");
     return Contents.Reg.Prev != nullptr;
   }
 };
 
-inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand& MO) {
+inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand &MO) {
   MO.print(OS, nullptr);
   return OS;
 }
 
-  // See friend declaration above. This additional declaration is required in
-  // order to compile LLVM with IBM xlC compiler.
-  hash_code hash_value(const MachineOperand &MO);
 } // End llvm namespace
 
 #endif

include/llvm/CodeGen/Passes.h

 class TargetMachine;
 class TargetRegisterClass;
 class raw_ostream;
 
 } // End llvm namespace
 
 /// List of target independent CodeGen pass IDs.
 namespace llvm {
-  FunctionPass *createAtomicExpandPass(const TargetMachine *TM);
 
-  /// createUnreachableBlockEliminationPass - The LLVM code generator does not
-  /// work well with unreachable basic blocks (what live ranges make sense for a
-  /// block that cannot be reached?).  As such, a code generator should either
-  /// not instruction select unreachable blocks, or run this pass as its
-  /// last LLVM modifying pass to clean up blocks that are not reachable from
-  /// the entry block.
-  FunctionPass *createUnreachableBlockEliminationPass();
 
-  /// MachineFunctionPrinter pass - This pass prints out the machine function to
-  /// the given stream as a debugging tool.
-  MachineFunctionPass *
-  createMachineFunctionPrinterPass(raw_ostream &OS,
-                                   const std::string &Banner ="");
+                                 const std::string &Banner = "");
 
-  /// MIRPrinting pass - this pass prints out the LLVM IR into the given stream
-  /// using the MIR serialization format.
-  MachineFunctionPass *createPrintMIRPass(raw_ostream &OS);
 
-  /// createCodeGenPreparePass - Transform the code to expose more pattern
-  /// matching during instruction selection.
-  FunctionPass *createCodeGenPreparePass(const TargetMachine *TM = nullptr);
 
-  /// AtomicExpandID -- Lowers atomic operations in terms of either cmpxchg
-  /// load-linked/store-conditional loops.
-  extern char &AtomicExpandID;
 
-  /// MachineLoopInfo - This pass is a loop analysis pass.
-  extern char &MachineLoopInfoID;
 
-  /// MachineDominators - This pass is a machine dominators analysis pass.
-  extern char &MachineDominatorsID;
 
 /// MachineDominanaceFrontier - This pass is a machine dominators analysis pass.
-  extern char &MachineDominanceFrontierID;
 
-  /// EdgeBundles analysis - Bundle machine CFG edges.
-  extern char &EdgeBundlesID;
 
-  /// LiveVariables pass - This pass computes the set of blocks in which each
-  /// variable is life and sets machine operand kill flags.
-  extern char &LiveVariablesID;
 
-  /// PHIElimination - This pass eliminates machine instruction PHI nodes
-  /// by inserting copy instructions.  This destroys SSA information, but is the
-  /// desired input for some register allocators.  This pass is "required" by
-  /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
-  extern char &PHIEliminationID;
 
-  /// LiveIntervals - This analysis keeps track of the live ranges of virtual
-  /// and physical registers.
-  extern char &LiveIntervalsID;
 
-  /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
-  extern char &LiveStacksID;
 
-  /// TwoAddressInstruction - This pass reduces two-address instructions to
-  /// use two operands. This destroys SSA information but it is desired by
-  /// register allocators.
-  extern char &TwoAddressInstructionPassID;
 
-  /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
-  extern char &ProcessImplicitDefsID;
 
-  /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
-  extern char &RegisterCoalescerID;
 
-  /// MachineScheduler - This pass schedules machine instructions.
-  extern char &MachineSchedulerID;
 
-  /// PostMachineScheduler - This pass schedules machine instructions postRA.
-  extern char &PostMachineSchedulerID;
 
-  /// SpillPlacement analysis. Suggest optimal placement of spill code between
-  /// basic blocks.
-  extern char &SpillPlacementID;
 
-  /// ShrinkWrap pass. Look for the best place to insert save and restore
-  // instruction and update the MachineFunctionInfo with that information.
-  extern char &ShrinkWrapID;
 
-  /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
-  /// assigned in VirtRegMap.
-  extern char &VirtRegRewriterID;
 
-  /// UnreachableMachineBlockElimination - This pass removes unreachable
-  /// machine basic blocks.
-  extern char &UnreachableMachineBlockElimID;
 
-  /// DeadMachineInstructionElim - This pass removes dead machine instructions.
-  extern char &DeadMachineInstructionElimID;
 
-  /// This pass adds dead/undef flags after analyzing subregister lanes.
-  extern char &DetectDeadLanesID;
 
-  /// FastRegisterAllocation Pass - This pass register allocates as fast as
-  /// possible. It is best suited for debug code where live ranges are short.
-  ///
-  FunctionPass *createFastRegisterAllocator();
 
-  /// BasicRegisterAllocation Pass - This pass implements a degenerate global
-  /// register allocator using the basic regalloc framework.
-  ///
-  FunctionPass *createBasicRegisterAllocator();
 
-  /// Greedy register allocation pass - This pass implements a global register
-  /// allocator for optimized builds.
-  ///
-  FunctionPass *createGreedyRegisterAllocator();
 
-  /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
-  /// Quadratic Prograaming (PBQP) based register allocator.
-  ///
-  FunctionPass *createDefaultPBQPRegisterAllocator();
 
-  /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
-  /// and eliminates abstract frame references.
-  extern char &PrologEpilogCodeInserterID;
-  MachineFunctionPass *createPrologEpilogInserterPass(const TargetMachine *TM);
 
-  /// ExpandPostRAPseudos - This pass expands pseudo instructions after
-  /// register allocation.
-  extern char &ExpandPostRAPseudosID;
 
-  /// createPostRAHazardRecognizer - This pass runs the post-ra hazard
-  /// recognizer.
-  extern char &PostRAHazardRecognizerID;
 
-  /// createPostRAScheduler - This pass performs post register allocation
-  /// scheduling.
-  extern char &PostRASchedulerID;
 
-  /// BranchFolding - This pass performs machine code CFG based
-  /// optimizations to delete branches to branches, eliminate branches to
-  /// successor blocks (creating fall throughs), and eliminating branches over
-  /// branches.
-  extern char &BranchFolderPassID;
 
-  /// MachineFunctionPrinterPass - This pass prints out MachineInstr's.
-  extern char &MachineFunctionPrinterPassID;
 
-  /// MIRPrintingPass - this pass prints out the LLVM IR using the MIR
-  /// serialization format.
-  extern char &MIRPrintingPassID;
 
-  /// TailDuplicate - Duplicate blocks with unconditional branches
-  /// into tails of their predecessors.
-  extern char &TailDuplicateID;
 
-  /// MachineTraceMetrics - This pass computes critical path and CPU resource
-  /// usage in an ensemble of traces.
-  extern char &MachineTraceMetricsID;
 
-  /// EarlyIfConverter - This pass performs if-conversion on SSA form by
-  /// inserting cmov instructions.
-  extern char &EarlyIfConverterID;
 
-  /// This pass performs instruction combining using trace metrics to estimate
-  /// critical-path and resource depth.
-  extern char &MachineCombinerID;
 
-  /// StackSlotColoring - This pass performs stack coloring and merging.
-  /// It merges disjoint allocas to reduce the stack size.
-  extern char &StackColoringID;
 
-  /// IfConverter - This pass performs machine code if conversion.
-  extern char &IfConverterID;
 
-  FunctionPass *createIfConverter(std::function<bool(const Function &)> Ftor);
 
-  /// MachineBlockPlacement - This pass places basic blocks based on branch
-  /// probabilities.
-  extern char &MachineBlockPlacementID;
 
-  /// MachineBlockPlacementStats - This pass collects statistics about the
-  /// basic block placement using branch probabilities and block frequency
-  /// information.
-  extern char &MachineBlockPlacementStatsID;
 
-  /// GCLowering Pass - Used by gc.root to perform its default lowering
-  /// operations.
-  FunctionPass *createGCLoweringPass();
 
-  /// ShadowStackGCLowering - Implements the custom lowering mechanism
-  /// used by the shadow stack GC.  Only runs on functions which opt in to
-  /// the shadow stack collector.
-  FunctionPass *createShadowStackGCLoweringPass();
 
-  /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
-  /// in machine code. Must be added very late during code generation, just
-  /// prior to output, and importantly after all CFG transformations (such as
-  /// branch folding).
-  extern char &GCMachineCodeAnalysisID;
 
-  /// Creates a pass to print GC metadata.
-  ///
-  FunctionPass *createGCInfoPrinter(raw_ostream &OS);
 
-  /// MachineCSE - This pass performs global CSE on machine instructions.
-  extern char &MachineCSEID;
 
-  /// ImplicitNullChecks - This pass folds null pointer checks into nearby
-  /// memory operations.
-  extern char &ImplicitNullChecksID;
 
-  /// MachineLICM - This pass performs LICM on machine instructions.
-  extern char &MachineLICMID;
 
-  /// MachineSinking - This pass performs sinking on machine instructions.
-  extern char &MachineSinkingID;
 
-  /// MachineCopyPropagation - This pass performs copy propagation on
-  /// machine instructions.
-  extern char &MachineCopyPropagationID;
 
-  /// PeepholeOptimizer - This pass performs peephole optimizations -
-  /// like extension and comparison eliminations.
-  extern char &PeepholeOptimizerID;
 
-  /// OptimizePHIs - This pass optimizes machine instruction PHIs
-  /// to take advantage of opportunities created during DAG legalization.
-  extern char &OptimizePHIsID;
 
-  /// StackSlotColoring - This pass performs stack slot coloring.
-  extern char &StackSlotColoringID;
 
-  /// \brief This pass lays out funclets contiguously.
-  extern char &FuncletLayoutID;
 
-  /// \brief This pass implements the "patchable-function" attribute.
-  extern char &PatchableFunctionID;
 
-  /// createStackProtectorPass - This pass adds stack protectors to functions.
-  ///
-  FunctionPass *createStackProtectorPass(const TargetMachine *TM);
 
-  /// createMachineVerifierPass - This pass verifies cenerated machine code
-  /// instructions for correctness.
-  ///
-  FunctionPass *createMachineVerifierPass(const std::string& Banner);
+FunctionPass *createMachineVerifierPass(const std::string &Banner);
 
-  /// createDwarfEHPass - This pass mulches exception handling code into a form
-  /// adapted to code generation.  Required if using dwarf exception handling.
-  FunctionPass *createDwarfEHPass(const TargetMachine *TM);
 
-  /// createWinEHPass - Prepares personality functions used by MSVC on Windows,
-  /// in addition to the Itanium LSDA based personalities.
-  FunctionPass *createWinEHPass(const TargetMachine *TM);
 
-  /// createSjLjEHPreparePass - This pass adapts exception handling code to use
-  /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
-  ///
-  FunctionPass *createSjLjEHPreparePass();
 
-  /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
-  /// slots relative to one another and allocates base registers to access them
-  /// when it is estimated by the target to be out of range of normal frame
-  /// pointer or stack pointer index addressing.
-  extern char &LocalStackSlotAllocationID;
 
-  /// ExpandISelPseudos - This pass expands pseudo-instructions.
-  extern char &ExpandISelPseudosID;
 
-  /// createExecutionDependencyFixPass - This pass fixes execution time
-  /// problems with dependent instructions, such as switching execution
-  /// domains to match.
-  ///
-  /// The pass will examine instructions using and defining registers in RC.
-  ///
-  FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
 
-  /// UnpackMachineBundles - This pass unpack machine instruction bundles.
-  extern char &UnpackMachineBundlesID;
 
-  FunctionPass *
-  createUnpackMachineBundles(std::function<bool(const Function &)> Ftor);
 
-  /// FinalizeMachineBundles - This pass finalize machine instruction
-  /// bundles (created earlier, e.g. during pre-RA scheduling).
-  extern char &FinalizeMachineBundlesID;
 
-  /// StackMapLiveness - This pass analyses the register live-out set of
-  /// stackmap/patchpoint intrinsics and attaches the calculated information to
-  /// the intrinsic for later emission to the StackMap.
-  extern char &StackMapLivenessID;
 
-  /// LiveDebugValues pass
-  extern char &LiveDebugValuesID;
 
-  /// createJumpInstrTables - This pass creates jump-instruction tables.
-  ModulePass *createJumpInstrTablesPass();
 
-  /// createForwardControlFlowIntegrityPass - This pass adds control-flow
-  /// integrity.
-  ModulePass *createForwardControlFlowIntegrityPass();
 
-  /// InterleavedAccess Pass - This pass identifies and matches interleaved
-  /// memory accesses to target specific intrinsics.
-  ///
-  FunctionPass *createInterleavedAccessPass(const TargetMachine *TM);
 
-  /// LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all
-  /// TLS variables for the emulated TLS model.
-  ///
-  ModulePass *createLowerEmuTLSPass(const TargetMachine *TM);
 
-  /// This pass lowers the @llvm.load.relative intrinsic to instructions.
-  /// This is unsafe to do earlier because a pass may combine the constant
-  /// initializer into the load, which may result in an overflowing evaluation.
-  ModulePass *createPreISelIntrinsicLoweringPass();
 
-  /// GlobalMerge - This pass merges internal (by default) globals into structs
-  /// to enable reuse of a base pointer by indexed addressing modes.
-  /// It can also be configured to focus on size optimizations only.
-  ///
-  Pass *createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset,
-                              bool OnlyOptimizeForSize = false,
-                              bool MergeExternalByDefault = false);
 
-  /// This pass splits the stack into a safe stack and an unsafe stack to
-  /// protect against stack-based overflow vulnerabilities.
-  FunctionPass *createSafeStackPass(const TargetMachine *TM = nullptr);
+
+/// This pass is executed POST-RA to collect which physical registers are
+/// used by given machien function.
+FunctionPass *createRegUsageInfoCollector();
 } // End llvm namespace
 
 /// Target machine pass initializer for passes with dependencies. Use with
 /// INITIALIZE_TM_PASS_END.
 #define INITIALIZE_TM_PASS_BEGIN INITIALIZE_PASS_BEGIN
 
 /// Target machine pass initializer for passes with dependencies. Use with
 /// INITIALIZE_TM_PASS_BEGIN.
-#define INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis) \
-    PassInfo *PI = new PassInfo(name, arg, & passName ::ID, \
-      PassInfo::NormalCtor_t(callDefaultCtor< passName >), cfg, analysis, \
-      PassInfo::TargetMachineCtor_t(callTargetMachineCtor< passName >)); \
-    Registry.registerPass(*PI, true); \
-    return PI; \
-  } \
-  void llvm::initialize##passName##Pass(PassRegistry &Registry) { \
-    CALL_ONCE_INITIALIZATION(initialize##passName##PassOnce) \
+#define INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis)             \
+  PassInfo *PI = new PassInfo(                                                 \
+      name, arg, &passName::ID,                                                \
+      PassInfo::NormalCtor_t(callDefaultCtor<passName>), cfg, analysis,        \
+      PassInfo::TargetMachineCtor_t(callTargetMachineCtor<passName>));         \
+  Registry.registerPass(*PI, true);                                            \
+  return PI;                                                                   \
+  }                                                                            \
+  void llvm::initialize##passName##Pass(PassRegistry &Registry) {              \
+    CALL_ONCE_INITIALIZATION(initialize##passName##PassOnce)                   \
   }
 
 /// This initializer registers TargetMachine constructor, so the pass being
 /// initialized can use target dependent interfaces. Please do not move this
 /// macro to be together with INITIALIZE_PASS, which is a complete target
 /// independent initializer, and we don't want to make libScalarOpts depend
 /// on libCodeGen.
-#define INITIALIZE_TM_PASS(passName, arg, name, cfg, analysis) \
-    INITIALIZE_TM_PASS_BEGIN(passName, arg, name, cfg, analysis) \
-    INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis)
+#define INITIALIZE_TM_PASS(passName, arg, name, cfg, analysis)                 \
+  INITIALIZE_TM_PASS_BEGIN(passName, arg, name, cfg, analysis)                 \
 
 #endif

include/llvm/CodeGen/PhysicalRegisterUsageInfo.h

+//=- PhysicalRegisterUsageInfo.cpp - Register Usage Informartion Storage -*- C++
+//-*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This pass is required to get Interprocedural Register Allocation effect.
+// See other two passes at lib/Target/X86/X86RegUsageInfoPropagate.cpp and
+// lib/CodeGen/RegUsageInfoCollector.cpp
+//
+// This pass is simple immutable pass which keeps StringMap of
+// function name to RegMask (calculated based on actual register allocation) and
+// provides simple API to query this information.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_PHYSICALREGISTERUSAGEINFO_H
+#define LLVM_CODEGEN_PHYSICALREGISTERUSAGEINFO_H
+
+#include "llvm/Pass.h"
+
+namespace llvm {
+
+class StringRef;
+
+class PhysicalRegisterUsageInfo : public ImmutablePass {
+  virtual void anchor();
+
+public:
+  static char ID;
+
+  PhysicalRegisterUsageInfo() : ImmutablePass(ID) {
+    PassRegistry &Registry = *PassRegistry::getPassRegistry();
+    initializePhysicalRegisterUsageInfoPass(Registry);
+  }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesAll();
+  }
+
+  void storeUpdateRegUsageInfo(StringRef MFName,
+                               std::vector<uint32_t> RegMasks);
+
+  const std::vector<uint32_t> *getRegUsageInfo(StringRef MFName);
+
+private:
+  // A simple map from function name to RegMask
+  // In RegMask 0 means register used (clobbered) by funciton
+  // and 1 means content of register will be preserved around function call
+  StringMap<std::vector<uint32_t>> RegMasks;
+};
+}
+
+#endif
 No newline at end of file

include/llvm/InitializePasses.h

 #define LLVM_INITIALIZEPASSES_H
 
 namespace llvm {
 
 class PassRegistry;
 
 /// initializeCore - Initialize all passes linked into the
 /// TransformUtils library.
-void initializeCore(PassRegistry&);
+void initializeCore(PassRegistry &);
 
 /// initializeTransformUtils - Initialize all passes linked into the
 /// TransformUtils library.
-void initializeTransformUtils(PassRegistry&);
+void initializeTransformUtils(PassRegistry &);
 
 /// initializeScalarOpts - Initialize all passes linked into the
 /// ScalarOpts library.
-void initializeScalarOpts(PassRegistry&);
+void initializeScalarOpts(PassRegistry &);
 
 /// initializeObjCARCOpts - Initialize all passes linked into the ObjCARCOpts
 /// library.
-void initializeObjCARCOpts(PassRegistry&);
+void initializeObjCARCOpts(PassRegistry &);
 
 /// initializeVectorization - Initialize all passes linked into the
 /// Vectorize library.
-void initializeVectorization(PassRegistry&);
+void initializeVectorization(PassRegistry &);
 
 /// initializeInstCombine - Initialize all passes linked into the
 /// InstCombine library.
-void initializeInstCombine(PassRegistry&);
+void initializeInstCombine(PassRegistry &);
 
 /// initializeIPO - Initialize all passes linked into the IPO library.
-void initializeIPO(PassRegistry&);
+void initializeIPO(PassRegistry &);
 
 /// initializeInstrumentation - Initialize all passes linked into the
 /// Instrumentation library.
-void initializeInstrumentation(PassRegistry&);
+void initializeInstrumentation(PassRegistry &);
 
 /// initializeAnalysis - Initialize all passes linked into the Analysis library.
-void initializeAnalysis(PassRegistry&);
+void initializeAnalysis(PassRegistry &);
 
 /// initializeCodeGen - Initialize all passes linked into the CodeGen library.
-void initializeCodeGen(PassRegistry&);
+void initializeCodeGen(PassRegistry &);
 
 /// Initialize all passes linked into the GlobalISel library.
 void initializeGlobalISel(PassRegistry &Registry);
 
 /// initializeCodeGen - Initialize all passes linked into the CodeGen library.
-void initializeTarget(PassRegistry&);
+void initializeTarget(PassRegistry &);
 
-void initializeAAEvalLegacyPassPass(PassRegistry&);
-void initializeAddDiscriminatorsPass(PassRegistry&);
-void initializeADCELegacyPassPass(PassRegistry&);
+void initializeAAEvalLegacyPassPass(PassRegistry &);
+void initializeAddDiscriminatorsPass(PassRegistry &);
+void initializeADCELegacyPassPass(PassRegistry &);
 void initializeBDCELegacyPassPass(PassRegistry &);
-void initializeAliasSetPrinterPass(PassRegistry&);
-void initializeAlwaysInlinerPass(PassRegistry&);
-void initializeArgPromotionPass(PassRegistry&);
-void initializeAtomicExpandPass(PassRegistry&);
-void initializeSampleProfileLoaderLegacyPassPass(PassRegistry&);
-void initializeAlignmentFromAssumptionsPass(PassRegistry&);
-void initializeBarrierNoopPass(PassRegistry&);
-void initializeBasicAAWrapperPassPass(PassRegistry&);
+void initializeAliasSetPrinterPass(PassRegistry &);
+void initializeAlwaysInlinerPass(PassRegistry &);
+void initializeArgPromotionPass(PassRegistry &);
+void initializeAtomicExpandPass(PassRegistry &);
+void initializeSampleProfileLoaderLegacyPassPass(PassRegistry &);
+void initializeAlignmentFromAssumptionsPass(PassRegistry &);
+void initializeBarrierNoopPass(PassRegistry &);
+void initializeBasicAAWrapperPassPass(PassRegistry &);
 void initializeCallGraphWrapperPassPass(PassRegistry &);
-void initializeBlockExtractorPassPass(PassRegistry&);
-void initializeBlockFrequencyInfoWrapperPassPass(PassRegistry&);
-void initializeBoundsCheckingPass(PassRegistry&);
-void initializeBranchFolderPassPass(PassRegistry&);
-void initializeBranchProbabilityInfoWrapperPassPass(PassRegistry&);
-void initializeBreakCriticalEdgesPass(PassRegistry&);
-void initializeCallGraphDOTPrinterPass(PassRegistry&);
-void initializeCallGraphPrinterLegacyPassPass(PassRegistry&);
-void initializeCallGraphViewerPass(PassRegistry&);
-void initializeCFGOnlyPrinterPass(PassRegistry&);
-void initializeCFGOnlyViewerPass(PassRegistry&);
-void initializeCFGPrinterPass(PassRegistry&);
-void initializeCFGSimplifyPassPass(PassRegistry&);
-void initializeCFLAAWrapperPassPass(PassRegistry&);
-void initializeExternalAAWrapperPassPass(PassRegistry&);
-void initializeForwardControlFlowIntegrityPass(PassRegistry&);
-void initializeFlattenCFGPassPass(PassRegistry&);
-void initializeStructurizeCFGPass(PassRegistry&);
-void initializeCFGViewerPass(PassRegistry&);
-void initializeConstantHoistingPass(PassRegistry&);
-void initializeCodeGenPreparePass(PassRegistry&);
+void initializeBlockExtractorPassPass(PassRegistry &);
+void initializeBlockFrequencyInfoWrapperPassPass(PassRegistry &);
+void initializeBoundsCheckingPass(PassRegistry &);
+void initializeBranchFolderPassPass(PassRegistry &);
+void initializeBranchProbabilityInfoWrapperPassPass(PassRegistry &);
+void initializeBreakCriticalEdgesPass(PassRegistry &);
+void initializeCallGraphDOTPrinterPass(PassRegistry &);
+void initializeCallGraphPrinterLegacyPassPass(PassRegistry &);
+void initializeCallGraphViewerPass(PassRegistry &);
+void initializeCFGOnlyPrinterPass(PassRegistry &);
+void initializeCFGOnlyViewerPass(PassRegistry &);
+void initializeCFGPrinterPass(PassRegistry &);
+void initializeCFGSimplifyPassPass(PassRegistry &);
+void initializeCFLAAWrapperPassPass(PassRegistry &);
+void initializeExternalAAWrapperPassPass(PassRegistry &);
+void initializeForwardControlFlowIntegrityPass(PassRegistry &);
+void initializeFlattenCFGPassPass(PassRegistry &);
+void initializeStructurizeCFGPass(PassRegistry &);
+void initializeCFGViewerPass(PassRegistry &);
+void initializeConstantHoistingPass(PassRegistry &);
+void initializeCodeGenPreparePass(PassRegistry &);
 void initializeConstantMergeLegacyPassPass(PassRegistry &);
-void initializeConstantPropagationPass(PassRegistry&);
-void initializeMachineCopyPropagationPass(PassRegistry&);
-void initializeCostModelAnalysisPass(PassRegistry&);
-void initializeCorrelatedValuePropagationPass(PassRegistry&);
-void initializeCrossDSOCFIPass(PassRegistry&);
-void initializeDAEPass(PassRegistry&);
-void initializeDAHPass(PassRegistry&);
-void initializeDCELegacyPassPass(PassRegistry&);
-void initializeDSELegacyPassPass(PassRegistry&);
-void initializeDeadInstEliminationPass(PassRegistry&);
-void initializeDeadMachineInstructionElimPass(PassRegistry&);
+void initializeConstantPropagationPass(PassRegistry &);
+void initializeMachineCopyPropagationPass(PassRegistry &);
+void initializeCostModelAnalysisPass(PassRegistry &);
+void initializeCorrelatedValuePropagationPass(PassRegistry &);
+void initializeCrossDSOCFIPass(PassRegistry &);
+void initializeDAEPass(PassRegistry &);
+void initializeDAHPass(PassRegistry &);
+void initializeDCELegacyPassPass(PassRegistry &);
+void initializeDSELegacyPassPass(PassRegistry &);
+void initializeDeadInstEliminationPass(PassRegistry &);
+void initializeDeadMachineInstructionElimPass(PassRegistry &);
 void initializeDelinearizationPass(PassRegistry &);
-void initializeDependenceAnalysisPass(PassRegistry&);
-void initializeDetectDeadLanesPass(PassRegistry&);
-void initializeDependenceAnalysisWrapperPassPass(PassRegistry&);
-void initializeDivergenceAnalysisPass(PassRegistry&);
-void initializeDomOnlyPrinterPass(PassRegistry&);
-void initializeDomOnlyViewerPass(PassRegistry&);
-void initializeDomPrinterPass(PassRegistry&);
-void initializeDomViewerPass(PassRegistry&);
-void initializeDominanceFrontierWrapperPassPass(PassRegistry&);
-void initializeDominatorTreeWrapperPassPass(PassRegistry&);
-void initializeEarlyIfConverterPass(PassRegistry&);
-void initializeEdgeBundlesPass(PassRegistry&);
-void initializeExpandPostRAPass(PassRegistry&);
+void initializeDependenceAnalysisPass(PassRegistry &);
+void initializeDetectDeadLanesPass(PassRegistry &);
+void initializeDependenceAnalysisWrapperPassPass(PassRegistry &);
+void initializeDivergenceAnalysisPass(PassRegistry &);
+void initializeDomOnlyPrinterPass(PassRegistry &);
+void initializeDomOnlyViewerPass(PassRegistry &);
+void initializeDomPrinterPass(PassRegistry &);
+void initializeDomViewerPass(PassRegistry &);
+void initializeDominanceFrontierWrapperPassPass(PassRegistry &);
+void initializeDominatorTreeWrapperPassPass(PassRegistry &);
+void initializeEarlyIfConverterPass(PassRegistry &);
+void initializeEdgeBundlesPass(PassRegistry &);
+void initializeExpandPostRAPass(PassRegistry &);
 void initializeAAResultsWrapperPassPass(PassRegistry &);
-void initializeGCOVProfilerPass(PassRegistry&);
-void initializePGOInstrumentationGenLegacyPassPass(PassRegistry&);
-void initializePGOInstrumentationUseLegacyPassPass(PassRegistry&);
-void initializePGOIndirectCallPromotionLegacyPassPass(PassRegistry&);
+void initializeGCOVProfilerPass(PassRegistry &);
+void initializePGOInstrumentationGenLegacyPassPass(PassRegistry &);
+void initializePGOInstrumentationUseLegacyPassPass(PassRegistry &);
+void initializePGOIndirectCallPromotionLegacyPassPass(PassRegistry &);
 void initializeInstrProfilingLegacyPassPass(PassRegistry &);
-void initializeAddressSanitizerPass(PassRegistry&);
-void initializeAddressSanitizerModulePass(PassRegistry&);
-void initializeMemorySanitizerPass(PassRegistry&);
-void initializeThreadSanitizerPass(PassRegistry&);
-void initializeSanitizerCoverageModulePass(PassRegistry&);
-void initializeDataFlowSanitizerPass(PassRegistry&);
-void initializeEfficiencySanitizerPass(PassRegistry&);
-void initializeScalarizerPass(PassRegistry&);
+void initializeAddressSanitizerPass(PassRegistry &);
+void initializeAddressSanitizerModulePass(PassRegistry &);
+void initializeMemorySanitizerPass(PassRegistry &);
+void initializeThreadSanitizerPass(PassRegistry &);
+void initializeSanitizerCoverageModulePass(PassRegistry &);
+void initializeDataFlowSanitizerPass(PassRegistry &);
+void initializeEfficiencySanitizerPass(PassRegistry &);
+void initializeScalarizerPass(PassRegistry &);
 void initializeEarlyCSELegacyPassPass(PassRegistry &);
 void initializeEliminateAvailableExternallyLegacyPassPass(PassRegistry &);
-void initializeExpandISelPseudosPass(PassRegistry&);
-void initializeForceFunctionAttrsLegacyPassPass(PassRegistry&);
-void initializeGCMachineCodeAnalysisPass(PassRegistry&);
-void initializeGCModuleInfoPass(PassRegistry&);
-void initializeGuardWideningLegacyPassPass(PassRegistry&);
-void initializeGVNLegacyPassPass(PassRegistry&);
-void initializeGlobalDCELegacyPassPass(PassRegistry&);
-void initializeGlobalOptLegacyPassPass(PassRegistry&);
-void initializeGlobalsAAWrapperPassPass(PassRegistry&);
-void initializeIPCPPass(PassRegistry&);
+void initializeExpandISelPseudosPass(PassRegistry &);
+void initializeForceFunctionAttrsLegacyPassPass(PassRegistry &);
+void initializeGCMachineCodeAnalysisPass(PassRegistry &);
+void initializeGCModuleInfoPass(PassRegistry &);
+void initializeGuardWideningLegacyPassPass(PassRegistry &);
+void initializeGVNLegacyPassPass(PassRegistry &);
+void initializeGlobalDCELegacyPassPass(PassRegistry &);
+void initializeGlobalOptLegacyPassPass(PassRegistry &);
+void initializeGlobalsAAWrapperPassPass(PassRegistry &);
+void initializeIPCPPass(PassRegistry &);
 void initializeIPSCCPLegacyPassPass(PassRegistry &);
-void initializeIVUsersPass(PassRegistry&);
-void initializeIfConverterPass(PassRegistry&);
-void initializeInductiveRangeCheckEliminationPass(PassRegistry&);
-void initializeIndVarSimplifyLegacyPassPass(PassRegistry&);
-void initializeInferFunctionAttrsLegacyPassPass(PassRegistry&);
-void initializeInlineCostAnalysisPass(PassRegistry&);
-void initializeInstructionCombiningPassPass(PassRegistry&);
-void initializeInstCountPass(PassRegistry&);
-void initializeInstNamerPass(PassRegistry&);
+void initializeIVUsersPass(PassRegistry &);
+void initializeIfConverterPass(PassRegistry &);
+void initializeInductiveRangeCheckEliminationPass(PassRegistry &);
+void initializeIndVarSimplifyLegacyPassPass(PassRegistry &);
+void initializeInferFunctionAttrsLegacyPassPass(PassRegistry &);
+void initializeInlineCostAnalysisPass(PassRegistry &);
+void initializeInstructionCombiningPassPass(PassRegistry &);
+void initializeInstCountPass(PassRegistry &);
+void initializeInstNamerPass(PassRegistry &);
 void initializeInterleavedAccessPass(PassRegistry &);
-void initializeInternalizeLegacyPassPass(PassRegistry&);
-void initializeIntervalPartitionPass(PassRegistry&);
+void initializeInternalizeLegacyPassPass(PassRegistry &);
+void initializeIntervalPartitionPass(PassRegistry &);
 void initializeIRTranslatorPass(PassRegistry &);
-void initializeJumpThreadingPass(PassRegistry&);
-void initializeLCSSAPass(PassRegistry&);
-void initializeLICMPass(PassRegistry&);
-void initializeLazyValueInfoPass(PassRegistry&);
-void initializeLintPass(PassRegistry&);
-void initializeLiveDebugVariablesPass(PassRegistry&);
-void initializeLiveIntervalsPass(PassRegistry&);
-void initializeLiveRegMatrixPass(PassRegistry&);
-void initializeLiveStacksPass(PassRegistry&);
-void initializeLiveVariablesPass(PassRegistry&);
-void initializeLoaderPassPass(PassRegistry&);
-void initializeLocalStackSlotPassPass(PassRegistry&);
-void initializeLoopDataPrefetchPass(PassRegistry&);
-void initializeLoopPassPass(PassRegistry&);
-void initializeLoopDeletionPass(PassRegistry&);
-void initializeLoopExtractorPass(PassRegistry&);
-void initializeLoopInfoWrapperPassPass(PassRegistry&);
+void initializeJumpThreadingPass(PassRegistry &);
+void initializeLCSSAPass(PassRegistry &);
+void initializeLICMPass(PassRegistry &);
+void initializeLazyValueInfoPass(PassRegistry &);
+void initializeLintPass(PassRegistry &);
+void initializeLiveDebugVariablesPass(PassRegistry &);
+void initializeLiveIntervalsPass(PassRegistry &);
+void initializeLiveRegMatrixPass(PassRegistry &);
+void initializeLiveStacksPass(PassRegistry &);
+void initializeLiveVariablesPass(PassRegistry &);
+void initializeLoaderPassPass(PassRegistry &);
+void initializeLocalStackSlotPassPass(PassRegistry &);
+void initializeLoopDataPrefetchPass(PassRegistry &);
+void initializeLoopPassPass(PassRegistry &);
+void initializeLoopDeletionPass(PassRegistry &);
+void initializeLoopExtractorPass(PassRegistry &);
+void initializeLoopInfoWrapperPassPass(PassRegistry &);
 void initializeLoopInterchangePass(PassRegistry &);
-void initializeLoopInstSimplifyPass(PassRegistry&);
-void initializeLoopRotateLegacyPassPass(PassRegistry&);
-void initializeLoopSimplifyPass(PassRegistry&);
-void initializeLoopSimplifyCFGLegacyPassPass(PassRegistry&);
-void initializeLoopStrengthReducePass(PassRegistry&);
-void initializeGlobalMergePass(PassRegistry&);
-void initializeLoopRerollPass(PassRegistry&);
-void initializeLoopUnrollPass(PassRegistry&);
-void initializeLoopUnswitchPass(PassRegistry&);
-void initializeLoopVersioningLICMPass(PassRegistry&);
-void initializeLoopIdiomRecognizePass(PassRegistry&);
+void initializeLoopInstSimplifyPass(PassRegistry &);
+void initializeLoopRotateLegacyPassPass(PassRegistry &);
+void initializeLoopSimplifyPass(PassRegistry &);
+void initializeLoopSimplifyCFGLegacyPassPass(PassRegistry &);
+void initializeLoopStrengthReducePass(PassRegistry &);
+void initializeGlobalMergePass(PassRegistry &);
+void initializeLoopRerollPass(PassRegistry &);
+void initializeLoopUnrollPass(PassRegistry &);
+void initializeLoopUnswitchPass(PassRegistry &);
+void initializeLoopVersioningLICMPass(PassRegistry &);
+void initializeLoopIdiomRecognizePass(PassRegistry &);
 void initializeLowerAtomicLegacyPassPass(PassRegistry &);
-void initializeLowerBitSetsPass(PassRegistry&);
-void initializeLowerExpectIntrinsicPass(PassRegistry&);
-void initializeLowerGuardIntrinsicPass(PassRegistry&);
-void initializeLowerIntrinsicsPass(PassRegistry&);
-void initializeLowerInvokePass(PassRegistry&);
-void initializeLowerSwitchPass(PassRegistry&);
-void initializeLowerEmuTLSPass(PassRegistry&);
-void initializeMachineBlockFrequencyInfoPass(PassRegistry&);
-void initializeMachineBlockPlacementPass(PassRegistry&);
-void initializeMachineBlockPlacementStatsPass(PassRegistry&);
-void initializeMachineBranchProbabilityInfoPass(PassRegistry&);
-void initializeMachineCSEPass(PassRegistry&);
+void initializeLowerBitSetsPass(PassRegistry &);
+void initializeLowerExpectIntrinsicPass(PassRegistry &);
+void initializeLowerGuardIntrinsicPass(PassRegistry &);
+void initializeLowerIntrinsicsPass(PassRegistry &);
+void initializeLowerInvokePass(PassRegistry &);
+void initializeLowerSwitchPass(PassRegistry &);
+void initializeLowerEmuTLSPass(PassRegistry &);
+void initializeMachineBlockFrequencyInfoPass(PassRegistry &);
+void initializeMachineBlockPlacementPass(PassRegistry &);
+void initializeMachineBlockPlacementStatsPass(PassRegistry &);
+void initializeMachineBranchProbabilityInfoPass(PassRegistry &);
+void initializeMachineCSEPass(PassRegistry &);
 void initializeModuleSummaryIndexWrapperPassPass(PassRegistry &);
-void initializeImplicitNullChecksPass(PassRegistry&);
-void initializeMachineDominatorTreePass(PassRegistry&);
-void initializeMachineDominanceFrontierPass(PassRegistry&);
-void initializeMachinePostDominatorTreePass(PassRegistry&);
-void initializeMachineLICMPass(PassRegistry&);
-void initializeMachineLoopInfoPass(PassRegistry&);
-void initializeMachineModuleInfoPass(PassRegistry&);
-void initializeMachineRegionInfoPassPass(PassRegistry&);
-void initializeMachineSchedulerPass(PassRegistry&);
-void initializeMachineSinkingPass(PassRegistry&);
-void initializeMachineTraceMetricsPass(PassRegistry&);
-void initializeMachineVerifierPassPass(PassRegistry&);
-void initializeMemCpyOptPass(PassRegistry&);
-void initializeMemDepPrinterPass(PassRegistry&);
-void initializeMemDerefPrinterPass(PassRegistry&);
-void initializeMemoryDependenceWrapperPassPass(PassRegistry&);
-void initializeMemorySSALazyPass(PassRegistry&);
-void initializeMemorySSAPrinterPassPass(PassRegistry&);
+void initializeImplicitNullChecksPass(PassRegistry &);
+void initializeMachineDominatorTreePass(PassRegistry &);
+void initializeMachineDominanceFrontierPass(PassRegistry &);
+void initializeMachinePostDominatorTreePass(PassRegistry &);
+void initializeMachineLICMPass(PassRegistry &);
+void initializeMachineLoopInfoPass(PassRegistry &);
+void initializeMachineModuleInfoPass(PassRegistry &);
+void initializeMachineRegionInfoPassPass(PassRegistry &);
+void initializeMachineSchedulerPass(PassRegistry &);
+void initializeMachineSinkingPass(PassRegistry &);
+void initializeMachineTraceMetricsPass(PassRegistry &);
+void initializeMachineVerifierPassPass(PassRegistry &);
+void initializeMemCpyOptPass(PassRegistry &);
+void initializeMemDepPrinterPass(PassRegistry &);
+void initializeMemDerefPrinterPass(PassRegistry &);
+void initializeMemoryDependenceWrapperPassPass(PassRegistry &);
+void initializeMemorySSALazyPass(PassRegistry &);
+void initializeMemorySSAPrinterPassPass(PassRegistry &);
 void initializeMergedLoadStoreMotionPass(PassRegistry &);
-void initializeMetaRenamerPass(PassRegistry&);
-void initializeMergeFunctionsPass(PassRegistry&);
-void initializeModuleDebugInfoPrinterPass(PassRegistry&);
+void initializeMetaRenamerPass(PassRegistry &);
+void initializeMergeFunctionsPass(PassRegistry &);
+void initializeModuleDebugInfoPrinterPass(PassRegistry &);
 void initializeNameAnonFunctionPass(PassRegistry &);
-void initializeNaryReassociatePass(PassRegistry&);
-void initializeNoAAPass(PassRegistry&);
-void initializeObjCARCAAWrapperPassPass(PassRegistry&);
-void initializeObjCARCAPElimPass(PassRegistry&);
-void initializeObjCARCExpandPass(PassRegistry&);
-void initializeObjCARCContractPass(PassRegistry&);
-void initializeObjCARCOptPass(PassRegistry&);
+void initializeNaryReassociatePass(PassRegistry &);
+void initializeNoAAPass(PassRegistry &);
+void initializeObjCARCAAWrapperPassPass(PassRegistry &);
+void initializeObjCARCAPElimPass(PassRegistry &);
+void initializeObjCARCExpandPass(PassRegistry &);
+void initializeObjCARCContractPass(PassRegistry &);
+void initializeObjCARCOptPass(PassRegistry &);
 void initializePAEvalPass(PassRegistry &);
-void initializeOptimizePHIsPass(PassRegistry&);
+void initializeOptimizePHIsPass(PassRegistry &);
 void initializePartiallyInlineLibCallsLegacyPassPass(PassRegistry &);
-void initializePEIPass(PassRegistry&);
-void initializePHIEliminationPass(PassRegistry&);
-void initializePartialInlinerPass(PassRegistry&);
-void initializePeepholeOptimizerPass(PassRegistry&);
-void initializePostDomOnlyPrinterPass(PassRegistry&);
-void initializePostDomOnlyViewerPass(PassRegistry&);
-void initializePostDomPrinterPass(PassRegistry&);
-void initializePostDomViewerPass(PassRegistry&);
-void initializePostDominatorTreeWrapperPassPass(PassRegistry&);
-void initializePostOrderFunctionAttrsLegacyPassPass(PassRegistry&);
-void initializePostRAHazardRecognizerPass(PassRegistry&);
-void initializePostRASchedulerPass(PassRegistry&);
-void initializePostMachineSchedulerPass(PassRegistry&);
-void initializePreISelIntrinsicLoweringPass(PassRegistry&);
-void initializePrintFunctionPassWrapperPass(PassRegistry&);
-void initializePrintModulePassWrapperPass(PassRegistry&);
-void initializePrintBasicBlockPassPass(PassRegistry&);
-void initializeProcessImplicitDefsPass(PassRegistry&);
-void initializePromotePassPass(PassRegistry&);
-void initializePruneEHPass(PassRegistry&);
-void initializeReassociateLegacyPassPass(PassRegistry&);
+void initializePEIPass(PassRegistry &);
+void initializePHIEliminationPass(PassRegistry &);
+void initializePhysicalRegisterUsageInfoPass(PassRegistry &);
+void initializePartialInlinerPass(PassRegistry &);
+void initializePeepholeOptimizerPass(PassRegistry &);
+void initializePostDomOnlyPrinterPass(PassRegistry &);
+void initializePostDomOnlyViewerPass(PassRegistry &);
+void initializePostDomPrinterPass(PassRegistry &);
+void initializePostDomViewerPass(PassRegistry &);
+void initializePostDominatorTreeWrapperPassPass(PassRegistry &);
+void initializePostOrderFunctionAttrsLegacyPassPass(PassRegistry &);
+void initializePostRAHazardRecognizerPass(PassRegistry &);
+void initializePostRASchedulerPass(PassRegistry &);
+void initializePostMachineSchedulerPass(PassRegistry &);
+void initializePreISelIntrinsicLoweringPass(PassRegistry &);
+void initializePrintFunctionPassWrapperPass(PassRegistry &);
+void initializePrintModulePassWrapperPass(PassRegistry &);
+void initializePrintBasicBlockPassPass(PassRegistry &);
+void initializeProcessImplicitDefsPass(PassRegistry &);
+void initializePromotePassPass(PassRegistry &);
+void initializePruneEHPass(PassRegistry &);
+void initializeReassociateLegacyPassPass(PassRegistry &);
 void initializeRegBankSelectPass(PassRegistry &);
-void initializeRegToMemPass(PassRegistry&);
-void initializeRegionInfoPassPass(PassRegistry&);
-void initializeRegionOnlyPrinterPass(PassRegistry&);
-void initializeRegionOnlyViewerPass(PassRegistry&);
-void initializeRegionPrinterPass(PassRegistry&);
-void initializeRegionViewerPass(PassRegistry&);
-void initializeReversePostOrderFunctionAttrsPass(PassRegistry&);
-void initializeRewriteStatepointsForGCPass(PassRegistry&);
-void initializeSafeStackPass(PassRegistry&);
+void initializeRegToMemPass(PassRegistry &);
+void initializeRegionInfoPassPass(PassRegistry &);
+void initializeRegionOnlyPrinterPass(PassRegistry &);
+void initializeRegionOnlyViewerPass(PassRegistry &);
+void initializeRegionPrinterPass(PassRegistry &);
+void initializeRegionViewerPass(PassRegistry &);
+void initializeReversePostOrderFunctionAttrsPass(PassRegistry &);
+void initializeRewriteStatepointsForGCPass(PassRegistry &);
+void initializeSafeStackPass(PassRegistry &);
 void initializeSCCPLegacyPassPass(PassRegistry &);
-void initializeSROALegacyPassPass(PassRegistry&);
-void initializeSROA_DTPass(PassRegistry&);
-void initializeSROA_SSAUpPass(PassRegistry&);
-void initializeSCEVAAWrapperPassPass(PassRegistry&);
-void initializeScalarEvolutionWrapperPassPass(PassRegistry&);
+void initializeSROALegacyPassPass(PassRegistry &);
+void initializeSROA_DTPass(PassRegistry &);
+void initializeSROA_SSAUpPass(PassRegistry &);
+void initializeSCEVAAWrapperPassPass(PassRegistry &);
+void initializeScalarEvolutionWrapperPassPass(PassRegistry &);
 void initializeShrinkWrapPass(PassRegistry &);
-void initializeSimpleInlinerPass(PassRegistry&);
-void initializeShadowStackGCLoweringPass(PassRegistry&);
-void initializeRegisterCoalescerPass(PassRegistry&);
-void initializeSingleLoopExtractorPass(PassRegistry&);
-void initializeSinkingLegacyPassPass(PassRegistry&);
+void initializeSimpleInlinerPass(PassRegistry &);
+void initializeShadowStackGCLoweringPass(PassRegistry &);
+void initializeRegisterCoalescerPass(PassRegistry &);
+void initializeSingleLoopExtractorPass(PassRegistry &);
+void initializeSinkingLegacyPassPass(PassRegistry &);
 void initializeSeparateConstOffsetFromGEPPass(PassRegistry &);
-void initializeSlotIndexesPass(PassRegistry&);
-void initializeSpillPlacementPass(PassRegistry&);
-void initializeSpeculativeExecutionPass(PassRegistry&);
-void initializeStackProtectorPass(PassRegistry&);
-void initializeStackColoringPass(PassRegistry&);
-void initializeStackSlotColoringPass(PassRegistry&);
+void initializeSlotIndexesPass(PassRegistry &);
+void initializeSpillPlacementPass(PassRegistry &);
+void initializeSpeculativeExecutionPass(PassRegistry &);
+void initializeStackProtectorPass(PassRegistry &);
+void initializeStackColoringPass(PassRegistry &);
+void initializeStackSlotColoringPass(PassRegistry &);
 void initializeStraightLineStrengthReducePass(PassRegistry &);
-void initializeStripDeadDebugInfoPass(PassRegistry&);
-void initializeStripDeadPrototypesLegacyPassPass(PassRegistry&);
-void initializeStripDebugDeclarePass(PassRegistry&);
-void initializeStripNonDebugSymbolsPass(PassRegistry&);
-void initializeStripSymbolsPass(PassRegistry&);
-void initializeTailCallElimPass(PassRegistry&);
-void initializeTailDuplicatePassPass(PassRegistry&);
-void initializeTargetPassConfigPass(PassRegistry&);
+void initializeStripDeadDebugInfoPass(PassRegistry &);
+void initializeStripDeadPrototypesLegacyPassPass(PassRegistry &);
+void initializeStripDebugDeclarePass(PassRegistry &);
+void initializeStripNonDebugSymbolsPass(PassRegistry &);
+void initializeStripSymbolsPass(PassRegistry &);
+void initializeTailCallElimPass(PassRegistry &);
+void initializeTailDuplicatePassPass(PassRegistry &);
+void initializeTargetPassConfigPass(PassRegistry &);
 void initializeTargetTransformInfoWrapperPassPass(PassRegistry &);
 void initializeTargetLibraryInfoWrapperPassPass(PassRegistry &);
 void initializeAssumptionCacheTrackerPass(PassRegistry &);
-void initializeTwoAddressInstructionPassPass(PassRegistry&);
-void initializeTypeBasedAAWrapperPassPass(PassRegistry&);
-void initializeScopedNoAliasAAWrapperPassPass(PassRegistry&);
-void initializeUnifyFunctionExitNodesPass(PassRegistry&);
-void initializeUnreachableBlockElimPass(PassRegistry&);
-void initializeUnreachableMachineBlockElimPass(PassRegistry&);
-void initializeVerifierLegacyPassPass(PassRegistry&);
-void initializeVirtRegMapPass(PassRegistry&);
-void initializeVirtRegRewriterPass(PassRegistry&);
-void initializeInstSimplifierPass(PassRegistry&);
-void initializeUnpackMachineBundlesPass(PassRegistry&);
-void initializeFinalizeMachineBundlesPass(PassRegistry&);
-void initializeLoopAccessAnalysisPass(PassRegistry&);
-void initializeLoopVectorizePass(PassRegistry&);
-void initializeSLPVectorizerPass(PassRegistry&);
-void initializeBBVectorizePass(PassRegistry&);
-void initializeMachineFunctionPrinterPassPass(PassRegistry&);
-void initializeMIRPrintingPassPass(PassRegistry&);
-void initializeStackMapLivenessPass(PassRegistry&);
-void initializeLiveDebugValuesPass(PassRegistry&);
+void initializeTwoAddressInstructionPassPass(PassRegistry &);
+void initializeTypeBasedAAWrapperPassPass(PassRegistry &);
+void initializeScopedNoAliasAAWrapperPassPass(PassRegistry &);
+void initializeUnifyFunctionExitNodesPass(PassRegistry &);
+void initializeUnreachableBlockElimPass(PassRegistry &);
+void initializeUnreachableMachineBlockElimPass(PassRegistry &);
+void initializeVerifierLegacyPassPass(PassRegistry &);
+void initializeVirtRegMapPass(PassRegistry &);
+void initializeVirtRegRewriterPass(PassRegistry &);
+void initializeInstSimplifierPass(PassRegistry &);
+void initializeUnpackMachineBundlesPass(PassRegistry &);
+void initializeFinalizeMachineBundlesPass(PassRegistry &);
+void initializeLoopAccessAnalysisPass(PassRegistry &);
+void initializeLoopVectorizePass(PassRegistry &);
+void initializeSLPVectorizerPass(PassRegistry &);
+void initializeBBVectorizePass(PassRegistry &);
+void initializeMachineFunctionPrinterPassPass(PassRegistry &);
+void initializeMIRPrintingPassPass(PassRegistry &);
+void initializeStackMapLivenessPass(PassRegistry &);
+void initializeLiveDebugValuesPass(PassRegistry &);
 void initializeMachineCombinerPass(PassRegistry &);
-void initializeLoadCombinePass(PassRegistry&);
-void initializeRewriteSymbolsPass(PassRegistry&);
-void initializeWinEHPreparePass(PassRegistry&);
+void initializeLoadCombinePass(PassRegistry &);
+void initializeRewriteSymbolsPass(PassRegistry &);
+void initializeWinEHPreparePass(PassRegistry &);
 void initializeWriteBitcodePassPass(PassRegistry &);
-void initializePlaceBackedgeSafepointsImplPass(PassRegistry&);
-void initializePlaceSafepointsPass(PassRegistry&);
-void initializeDwarfEHPreparePass(PassRegistry&);
-void initializeFloat2IntPass(PassRegistry&);
-void initializeLoopDistributePass(PassRegistry&);
-void initializeSjLjEHPreparePass(PassRegistry&);
-void initializeDemandedBitsWrapperPassPass(PassRegistry&);
+void initializePlaceBackedgeSafepointsImplPass(PassRegistry &);
+void initializePlaceSafepointsPass(PassRegistry &);
+void initializeDwarfEHPreparePass(PassRegistry &);
+void initializeFloat2IntPass(PassRegistry &);
+void initializeLoopDistributePass(PassRegistry &);
+void initializeSjLjEHPreparePass(PassRegistry &);
+void initializeDemandedBitsWrapperPassPass(PassRegistry &);
 void initializeFuncletLayoutPass(PassRegistry &);
-void initializeLoopLoadEliminationPass(PassRegistry&);
+void initializeLoopLoadEliminationPass(PassRegistry &);
 void initializeFunctionImportPassPass(PassRegistry &);
 void initializeLoopVersioningPassPass(PassRegistry &);
 void initializeWholeProgramDevirtPass(PassRegistry &);
 void initializePatchableFunctionPass(PassRegistry &);
 }
 
 #endif

lib/CodeGen/CMakeLists.txt

add_llvm_library(LLVMCodeGen
   PatchableFunction.cpp
   MIRPrinter.cpp
   MIRPrintingPass.cpp
   OptimizePHIs.cpp
   ParallelCG.cpp
   PeepholeOptimizer.cpp
   PHIElimination.cpp
   PHIEliminationUtils.cpp
+  PhysicalRegisterUsageInfo.cpp
   PostRAHazardRecognizer.cpp
   PostRASchedulerList.cpp
   PreISelIntrinsicLowering.cpp
   ProcessImplicitDefs.cpp
   PrologEpilogInserter.cpp
   PseudoSourceValue.cpp
   RegAllocBase.cpp
   RegAllocBasic.cpp
   RegAllocFast.cpp
   RegAllocGreedy.cpp
   RegAllocPBQP.cpp
   RegisterClassInfo.cpp
   RegisterCoalescer.cpp
   RegisterPressure.cpp
   RegisterScavenging.cpp
+  RegUsageInfoCollector.cpp
   SafeStack.cpp
   ScheduleDAG.cpp
   ScheduleDAGInstrs.cpp
   ScheduleDAGPrinter.cpp
   ScoreboardHazardRecognizer.cpp
   ShadowStackGCLowering.cpp
   ShrinkWrap.cpp
   SjLjEHPrepare.cpp
   SlotIndexes.cpp

lib/CodeGen/PhysicalRegisterUsageInfo.cpp

+//=- PhysicalRegisterUsageInfo.cpp - Register Usage Informartion Storage -*- C++
+//-*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This pass is required to get Interprocedural Register Allocation effect.
+// See other two passes at lib/Target/X86/X86RegUsageInfoPropagate.cpp and
+// lib/CodeGen/RegUsageInfoCollector.cpp
+//
+// This pass is simple immutable pass which keeps StringMap of
+// function name to RegMask (calculated based on actual register allocation) and
+// provides simple API to query this information.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/PhysicalRegisterUsageInfo.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "ipra"
+
+INITIALIZE_PASS(PhysicalRegisterUsageInfo, "reg-usage-info",
+                "Register Usage Informartion Stroage", false, true)
+
+char PhysicalRegisterUsageInfo::ID = 0;
+
+void PhysicalRegisterUsageInfo::anchor() {}
+
+void PhysicalRegisterUsageInfo::storeUpdateRegUsageInfo(
+    StringRef MFName, std::vector<uint32_t> RegMask) {
+  RegMasks[MFName] = std::move(RegMask);
+}
+
+const std::vector<uint32_t> *
+PhysicalRegisterUsageInfo::getRegUsageInfo(StringRef MFName) {
+  if (RegMasks.find(MFName) != RegMasks.end())
+    return &(RegMasks.find(MFName)->second);
+  else
+    return nullptr;
+}

lib/CodeGen/RegUsageInfoCollector.cpp

+//=- RegUsageInfoCollector.cpp - Register Usage Informartion Collector -*- C++
+//-*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This pass is required to get Interprocedural Register Allocation effect.
+// See other two passes at lib/Target/X86/X86RegUsageInfoPropagate.cpp and
+// lib/CodeGen/PhysicalRegisterUsageInfo.cpp
+//
+// This pass is simple MachineFunction pass which collects register usage
+// details by iterating through
+// each physical registers and checking MRI::isPhysRegUsed() then creates a
+// RegMask based on this details.
+// The pass then stores this RegMask in PhysicalRegisterUsageInfo.cpp
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/PhysicalRegisterUsageInfo.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "ipra"
+
+namespace llvm {
+void initializeRegUsageInfoCollectorPass(PassRegistry &);
+}
+
+namespace {
+class RegUsageInfoCollector : public MachineFunctionPass {
+public:
+  RegUsageInfoCollector() : MachineFunctionPass(ID) {}
+
+  const char *getPassName() const override {
+    return "Register Usage Information Collector Pass";
+  }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override;
+
+  bool runOnMachineFunction(MachineFunction &MF) override;
+
+  static char ID;
+};
+}
+
+char RegUsageInfoCollector::ID = 0;
+
+INITIALIZE_PASS_BEGIN(RegUsageInfoCollector, "RegUsageInfoCollector",
+                      "Register Usage Information Collector Pass", false, false)
+INITIALIZE_PASS_DEPENDENCY(PhysicalRegisterUsageInfo)
+INITIALIZE_PASS_END(RegUsageInfoCollector, "RegUsageInfoCollector",
+                    "Register Usage Information Collector Pass", false, false)
+
+FunctionPass *llvm::createRegUsageInfoCollector() {
+  return new RegUsageInfoCollector();
+}
+
+void RegUsageInfoCollector::getAnalysisUsage(AnalysisUsage &AU) const {
+  AU.addRequired<PhysicalRegisterUsageInfo>();
+  AU.setPreservesAll();
+  MachineFunctionPass::getAnalysisUsage(AU);
+}
+
+bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
+  bool changed = false;
+  MachineRegisterInfo *MRI = &MF.getRegInfo();
+  TargetRegisterInfo *TRI =
+      (TargetRegisterInfo *)MF.getSubtarget().getRegisterInfo();
+
+  DEBUG(dbgs() << " -------------------- Register Usage Collection Pass "
+                  "----------------------- \n");
+  DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
+
+  std::vector<uint32_t> RegMask;
+  unsigned regMaskSize =
+      (TRI->getNumRegs() + 31) / 32; // size should be in multiple of 32.
+  RegMask.resize(regMaskSize, 0);
+
+  PhysicalRegisterUsageInfo *PRUI = &getAnalysis<PhysicalRegisterUsageInfo>();
+
+  for (unsigned PReg = 1; PReg < TRI->getNumRegs(); ++PReg) {
+    if (!MRI->reg_nodbg_empty(PReg)) {
+      if (MRI->isPhysRegUsed(PReg)) {
+        // If PReg is clobbered then all of its alias are also clobbered
+        for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI) {
+          RegMask[*AI / 32] |= 1u << *AI % 32;
+        }
+      }
+    }
+  }
+
+  DEBUG(dbgs() << " -----------------------------------------------------------"
+                  "------------------ \n");
+
+  // bitwise negation for RegMask because 0 means clobbred and 1 means preserved
+  for (unsigned index = 0; index < regMaskSize; index++) {
+    RegMask[index] = ~RegMask[index];
+  }
+
+  PRUI->storeUpdateRegUsageInfo(MF.getName(), std::move(RegMask));
+
+  return changed;
+}

lib/CodeGen/TargetPassConfig.cpp

 #include "llvm/CodeGen/TargetPassConfig.h"
 
 #include "llvm/Analysis/BasicAliasAnalysis.h"
 #include "llvm/Analysis/CFLAliasAnalysis.h"
 #include "llvm/Analysis/Passes.h"
 #include "llvm/Analysis/ScopedNoAliasAA.h"
 #include "llvm/Analysis/TypeBasedAliasAnalysis.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/PhysicalRegisterUsageInfo.h"
 #include "llvm/CodeGen/RegAllocRegistry.h"
 #include "llvm/IR/IRPrintingPasses.h"
 #include "llvm/IR/LegacyPassManager.h"
 #include "llvm/IR/Verifier.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Transforms/Instrumentation.h"
 #include "llvm/Transforms/Scalar.h"
 #include "llvm/Transforms/Utils/SymbolRewriter.h"
 
 using namespace llvm;
 
 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
                                    cl::desc("Disable Post Regalloc"));
 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
                                        cl::desc("Disable branch folding"));
 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
                                           cl::desc("Disable tail duplication"));
-static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
+static cl::opt<bool> DisableEarlyTailDup(
+    "disable-early-taildup", cl::Hidden,
     cl::desc("Disable pre-register allocation tail duplication"));
-static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
-    cl::Hidden, cl::desc("Disable probability-driven block placement"));
-static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
-    cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
+static cl::opt<bool> DisableBlockPlacement(
+    "disable-block-placement", cl::Hidden,
+    cl::desc("Disable probability-driven block placement"));
+static cl::opt<bool> EnableBlockPlacementStats(
+    "enable-block-placement-stats", cl::Hidden,
+    cl::desc("Collect probability-driven block placement stats"));
 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
                                 cl::desc("Disable Stack Slot Coloring"));
-static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
+static cl::opt<bool>
+    DisableMachineDCE("disable-machine-dce", cl::Hidden,
                       cl::desc("Disable Machine Dead Code Elimination"));
-static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
+static cl::opt<bool>
+    DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
                              cl::desc("Disable Early If-conversion"));
 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
                                         cl::desc("Disable Machine LICM"));
-static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
+static cl::opt<bool> DisableMachineCSE(
+    "disable-machine-cse", cl::Hidden,
     cl::desc("Disable Machine Common Subexpression Elimination"));
 static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
     "optimize-regalloc", cl::Hidden,
     cl::desc("Enable optimized register allocation compilation path."));
 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
                                               cl::Hidden,
                                               cl::desc("Disable Machine LICM"));
 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
                                         cl::desc("Disable Machine Sinking"));
-static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
+static cl::opt<bool>
+    DisableLSR("disable-lsr", cl::Hidden,
                cl::desc("Disable Loop Strength Reduction Pass"));
-static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
-    cl::Hidden, cl::desc("Disable ConstantHoisting"));
+static cl::opt<bool>
+    DisableConstantHoisting("disable-constant-hoisting", cl::Hidden,
+                            cl::desc("Disable ConstantHoisting"));
 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
                                 cl::desc("Disable Codegen Prepare"));
 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
                                      cl::desc("Disable Copy Propagation pass"));
-static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
-    cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
+static cl::opt<bool>
+    DisablePartialLibcallInlining("disable-partial-libcall-inlining",
+                                  cl::Hidden,
+                                  cl::desc("Disable Partial Libcall Inlining"));
 static cl::opt<bool> EnableImplicitNullChecks(
     "enable-implicit-null-checks",
     cl::desc("Fold null checks into faulting memory operations"),
     cl::init(false));
-static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
+static cl::opt<bool>
+    PrintLSR("print-lsr-output", cl::Hidden,
              cl::desc("Print LLVM IR produced by the loop-reduce pass"));
-static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
+static cl::opt<bool>
+    PrintISelInput("print-isel-input", cl::Hidden,
                    cl::desc("Print LLVM IR input to isel pass"));
 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
                                  cl::desc("Dump garbage collector data"));
-static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
+static cl::opt<bool>
+    VerifyMachineCode("verify-machineinstrs", cl::Hidden,
                       cl::desc("Verify generated machine code"),
-    cl::init(false),
-    cl::ZeroOrMore);
+                      cl::init(false), cl::ZeroOrMore);
 
-static cl::opt<std::string>
-PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
+static cl::opt<std::string> PrintMachineInstrs("print-machineinstrs",
+                                               cl::ValueOptional,
                                                cl::desc("Print machine instrs"),
-                   cl::value_desc("pass-name"), cl::init("option-unspecified"));
+                                               cl::value_desc("pass-name"),
+                                               cl::init("option-unspecified"));
 
 // Temporary option to allow experimenting with MachineScheduler as a post-RA
 // scheduler. Targets can "properly" enable this with
 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
 // Targets can return true in targetSchedulesPostRAScheduling() and
 // insert a PostRA scheduling pass wherever it wants.
-cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
-  cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
+cl::opt<bool> MISchedPostRA(
+    "misched-postra", cl::Hidden,
+    cl::desc(
+        "Run MachineScheduler post regalloc (independent of preRA sched)"));
 
 // Experimental option to run live interval analysis early.
-static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
+static cl::opt<bool> EarlyLiveIntervals(
+    "early-live-intervals", cl::Hidden,
     cl::desc("Run live interval analysis earlier in the pipeline"));
 
-static cl::opt<bool> UseCFLAA("use-cfl-aa-in-codegen",
-  cl::init(false), cl::Hidden,
+static cl::opt<bool> UseCFLAA(
+    "use-cfl-aa-in-codegen", cl::init(false), cl::Hidden,
     cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"));
 
+// Option to enable compile time interprocedural register allocation.
+cl::opt<bool>
+    UseIPRA("enable-ipra", cl::init(false),
+            cl::desc("Enable compile time interprocedural register allocation "
+                     "to reduce load/store at procedure calls."));
+
 /// Allow standard passes to be disabled by command line options. This supports
 /// simple binary flags that either suppress the pass or do nothing.
 /// i.e. -disable-mypass=false has no effect.
 /// These should be converted to boolOrDefault in order to use applyOverride.
 static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
                                        bool Override) {
   if (Override)
     return IdentifyingPassPtr();
   return PassID;
 }
 

 public:
   // List of passes explicitly substituted by this target. Normally this is
   // empty, but it is a convenient way to suppress or replace specific passes
   // that are part of a standard pass pipeline without overridding the entire
   // pipeline. This mechanism allows target options to inherit a standard pass's
   // user interface. For example, a target may disable a standard pass by
   // default by substituting a pass ID of zero, and the user may still enable
   // that standard pass with an explicit command line option.
-  DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
+  DenseMap<AnalysisID, IdentifyingPassPtr> TargetPasses;
 
   /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
   /// is inserted after each instance of the first one.
   SmallVector<InsertedPass, 4> InsertedPasses;
 };
 } // namespace llvm
 
 // Out of line virtual method.
-TargetPassConfig::~TargetPassConfig() {
-  delete Impl;
-}
+TargetPassConfig::~TargetPassConfig() { delete Impl; }
 
 // Out of line constructor provides default values for pass options and
 // registers all common codegen passes.
 TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
     : ImmutablePass(ID), PM(&pm), StartBefore(nullptr), StartAfter(nullptr),
       StopAfter(nullptr), Started(true), Stopped(false),
       AddingMachinePasses(false), TM(tm), Impl(nullptr), Initialized(false),
       DisableVerify(false), EnableTailMerge(true) {

 /// createPassConfig - Create a pass configuration object to be used by
 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
 ///
 /// Targets may override this to extend TargetPassConfig.
 TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
   return new TargetPassConfig(this, PM);
 }
 
-TargetPassConfig::TargetPassConfig()
-  : ImmutablePass(ID), PM(nullptr) {
+TargetPassConfig::TargetPassConfig() : ImmutablePass(ID), PM(nullptr) {
   llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
 }
 
 // Helper to verify the analysis is really immutable.
 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
   assert(!Initialized && "PassConfig is immutable");
   Opt = Val;
 }
 
 void TargetPassConfig::substitutePass(AnalysisID StandardID,
                                       IdentifyingPassPtr TargetID) {
   Impl->TargetPasses[StandardID] = TargetID;
 }
 
 IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
-  DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
-    I = Impl->TargetPasses.find(ID);
+  DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator I =
+      Impl->TargetPasses.find(ID);
   if (I == Impl->TargetPasses.end())
     return ID;
   return I->second;
 }
 
 bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const {
   IdentifyingPassPtr TargetID = getPassSubstitution(ID);
   IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID);
-  return !FinalPtr.isValid() || FinalPtr.isInstance() ||
-      FinalPtr.getID() != ID;
+  return !FinalPtr.isValid() || FinalPtr.isInstance() || FinalPtr.getID() != ID;
 }
 
 /// Add a pass to the PassManager if that pass is supposed to be run.  If the
 /// Started/Stopped flags indicate either that the compilation should start at
 /// a later pass or that it should stop after an earlier pass, then do not add
 /// the pass.  Finally, compare the current pass against the StartAfter
 /// and StopAfter options and change the Started/Stopped flags accordingly.
 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
void TargetPassConfig::addPassesToHandleExceptions() {
   case ExceptionHandling::SjLj:
     // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
     // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
     // catch info can get misplaced when a selector ends up more than one block
     // removed from the parent invoke(s). This could happen when a landing
     // pad is shared by multiple invokes and is also a target of a normal
     // edge from elsewhere.
     addPass(createSjLjEHPreparePass());
-    // FALLTHROUGH
   case ExceptionHandling::DwarfCFI:
   case ExceptionHandling::ARM:
     addPass(createDwarfEHPass(TM));
     break;
   case ExceptionHandling::WinEH:
     // We support using both GCC-style and MSVC-style exceptions on Windows, so
     // add both preparation passes. Each pass will only actually run if it
     // recognizes the personality function.

 /// Add pass to prepare the LLVM IR for code generation. This should be done
 /// before exception handling preparation passes.
 void TargetPassConfig::addCodeGenPrepare() {
   if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
     addPass(createCodeGenPreparePass(TM));
   addPass(createRewriteSymbolsPass());
 }
 
+#include "llvm/Analysis/CallGraphSCCPass.h"
+namespace llvm {
+void initializeDummyCGSCCPassPass(PassRegistry &);
+}
+namespace {
+class DummyCGSCCPass : public CallGraphSCCPass {
+public:
+  static char ID;
+  DummyCGSCCPass() : CallGraphSCCPass(ID){};
+  bool runOnSCC(CallGraphSCC &SCC) override { return false; }
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.setPreservesAll();
+  }
+};
+}
+
+char DummyCGSCCPass::ID = 0;
+INITIALIZE_PASS_BEGIN(DummyCGSCCPass, "DummyCGSCCPass", "DummyCGSCCPass", false,
+                      false)
+INITIALIZE_PASS_DEPENDENCY(CallGraphWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfoWrapperPass)
+INITIALIZE_PASS_END(DummyCGSCCPass, "DummyCGSCCPass", "DummyCGSCCPass", false,
+                    false)
+
 /// Add common passes that perform LLVM IR to IR transforms in preparation for
 /// instruction selection.
 void TargetPassConfig::addISelPrepare() {
   addPreISel();
 
+  if (UseIPRA) {
+    // FORCE CODEGEN TO RUN ACCORDING TO THE CALLGRAPH
+    initializeDummyCGSCCPassPass(*PassRegistry::getPassRegistry());
+    addPass(new DummyCGSCCPass);
+  }
+
   // Add both the safe stack and the stack protection passes: each of them will
   // only protect functions that have corresponding attributes.
   addPass(createSafeStackPass(TM));
   addPass(createStackProtectorPass(TM));
 
   if (PrintISelInput)
     addPass(createPrintFunctionPass(
         dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
void TargetPassConfig::addMachinePasses() {
   AddingMachinePasses = true;
 
   // Insert a machine instr printer pass after the specified pass.
   if (!StringRef(PrintMachineInstrs.getValue()).equals("") &&
       !StringRef(PrintMachineInstrs.getValue()).equals("option-unspecified")) {
     const PassRegistry *PR = PassRegistry::getPassRegistry();
     const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
     const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
-    assert (TPI && IPI && "Pass ID not registered!");
+    assert(TPI && IPI && "Pass ID not registered!");
     const char *TID = (const char *)(TPI->getTypeInfo());
     const char *IID = (const char *)(IPI->getTypeInfo());
     insertPass(TID, IID);
   }
 
   // Print the instruction selected machine code...
   printAndVerify("After Instruction Selection");
 
   // Expand pseudo-instructions emitted by ISel.
   addPass(&ExpandISelPseudosID);
 
   // Add passes that optimize machine instructions in SSA form.
   if (getOptLevel() != CodeGenOpt::None) {
     addMachineSSAOptimization();
   } else {
     // If the target requests it, assign local variables to stack slots relative
     // to one another and simplify frame index references where possible.
     addPass(&LocalStackSlotAllocationID, false);
   }
 
   // Run pre-ra passes.
   addPreRegAlloc();
 
   // Run register allocation and passes that are tightly coupled with it,
   // including phi elimination and scheduling.
   if (getOptimizeRegAlloc())
     addOptimizedRegAlloc(createRegAllocPass(true));
   else
     addFastRegAlloc(createRegAllocPass(false));
 
   // Run post-ra passes.
   addPostRegAlloc();
 
+  if (UseIPRA) {
+    // this is MachineFunction pass which iterates through register
+    // to check if it is used or not and creates RegMask
+    addPass(createRegUsageInfoCollector());
+  }
+
   // Insert prolog/epilog code.  Eliminate abstract frame index references...
   if (getOptLevel() != CodeGenOpt::None)
     addPass(&ShrinkWrapID);
 
   // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only
   // do so if it hasn't been disabled, substituted, or overridden.
   if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID))
-      addPass(createPrologEpilogInserterPass(TM));
 
   /// Add passes that optimize machine instructions after register allocation.
   if (getOptLevel() != CodeGenOpt::None)
     addMachineLateOptimization();
 
   // Expand pseudo instructions before second scheduling pass.
   addPass(&ExpandPostRAPseudosID);
 
void TargetPassConfig::addMachinePasses() {
   if (addGCPasses()) {
     if (PrintGCInfo)
       addPass(createGCInfoPrinter(dbgs()), false, false);
   }
 
   // Basic block placement.
   if (getOptLevel() != CodeGenOpt::None)
     addBlockPlacement();
 
   addPreEmitPass();
 
   addPass(&FuncletLayoutID, false);
 
   addPass(&StackMapLivenessID, false);
   addPass(&LiveDebugValuesID, false);
 
   addPass(&PatchableFunctionID, false);
 
   AddingMachinePasses = false;
 }
 
 /// Add passes that optimize machine instructions in SSA form.
 void TargetPassConfig::addMachineSSAOptimization() {
   // Pre-ra tail duplication.
   addPass(&EarlyTailDuplicateID);

 }
 
 //===---------------------------------------------------------------------===//
 /// Register Allocation Pass Configuration
 //===---------------------------------------------------------------------===//
 
 bool TargetPassConfig::getOptimizeRegAlloc() const {
   switch (OptimizeRegAlloc) {
-  case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
-  case cl::BOU_TRUE:  return true;
-  case cl::BOU_FALSE: return false;
+  case cl::BOU_UNSET:
+    return getOptLevel() != CodeGenOpt::None;
+  case cl::BOU_TRUE:
+    return true;
+  case cl::BOU_FALSE:
+    return false;
   }
   llvm_unreachable("Invalid optimize-regalloc state");
 }
 
 /// RegisterRegAlloc's global Registry tracks allocator registration.
 MachinePassRegistry RegisterRegAlloc::Registry;
 
 /// A dummy default pass factory indicates whether the register allocator is
 /// overridden on the command line.
 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
 static RegisterRegAlloc
-defaultRegAlloc("default",
-                "pick register allocator based on -O option",
+    defaultRegAlloc("default", "pick register allocator based on -O option",
                     useDefaultRegisterAllocator);
 
 /// -regalloc=... command line option.
 static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
-               RegisterPassParser<RegisterRegAlloc> >
-RegAlloc("regalloc",
-         cl::init(&useDefaultRegisterAllocator),
+               RegisterPassParser<RegisterRegAlloc>>
+    RegAlloc("regalloc", cl::init(&useDefaultRegisterAllocator),
              cl::desc("Register allocator to use"));
 
-
 /// Instantiate the default register allocator pass for this target for either
 /// the optimized or unoptimized allocation path. This will be added to the pass
 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
 /// in the optimized case.
 ///
 /// A target that uses the standard regalloc pass order for fast or optimized
 /// allocation may still override this for per-target regalloc
 /// selection. But -regalloc=... always takes precedence.

lib/Target/X86/CMakeLists.txt

set(sources
   X86FrameLowering.cpp
   X86ISelDAGToDAG.cpp
   X86ISelLowering.cpp
   X86InstrInfo.cpp
   X86MCInstLower.cpp
   X86MachineFunctionInfo.cpp
   X86PadShortFunction.cpp
   X86RegisterInfo.cpp
+  X86RegUsageInfoPropagate.cpp
   X86SelectionDAGInfo.cpp
   X86ShuffleDecodeConstantPool.cpp
   X86Subtarget.cpp
   X86TargetMachine.cpp
   X86TargetObjectFile.cpp
   X86TargetTransformInfo.cpp
   X86VZeroUpper.cpp
   X86FixupLEAs.cpp

lib/Target/X86/X86.h

 FunctionPass *createX86ExpandPseudoPass();
 
 /// Return a Machine IR pass that selectively replaces
 /// certain byte and word instructions by equivalent 32 bit instructions,
 /// in order to eliminate partial register usage, false dependences on
 /// the upper portions of registers, and to save code size.
 FunctionPass *createX86FixupBWInsts();
 
+/// Return a MachineFunction pass that identifies call site
+/// and propagates register usage information of callee to caller
+/// if available with PysicalRegisterUsageInfo pass.
+FunctionPass *createRegUsageInfoPropPass();
+
 void initializeFixupBWInstPassPass(PassRegistry &);
 } // End llvm namespace
 
 #endif

lib/Target/X86/X86RegUsageInfoPropagate.cpp

+//=- X86RegUsageInfoPropagate.cpp - Target Specific Register Usage Informartion
+//Propagation -*- C++ -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+// This pass is last required pass to get Interprocedural Register Allocation
+// effect.
+// See other two passes at lib/CodeGen/PhysicalRegisterUsageInfo.cpp and
+// lib/CodeGen/RegUsageInfoCollector.cpp
+//
+// This pass iterates through MachineInstr in given MachineFunction and at each
+// callsite quires PhysicalRegisterUsageInfo.cpp
+// for RegMask (calculated based on actual register allocation) of callee
+// function, if such details found then pass will update
+// RegMask in call instruction. This updated RegMask will be used RegAllocators
+// while allocating current MachineFunction.
+//
+//===----------------------------------------------------------------------===//
+
+#include "X86.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/PhysicalRegisterUsageInfo.h"
+#include "llvm/PassAnalysisSupport.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetMachine.h"
+#include <map>
+#include <string>
+
+namespace llvm {
+void initializeRegUsageInfoPropagationPassPass(PassRegistry &);
+}
+
+using namespace llvm;
+
+#define DEBUG_TYPE "ipra"
+
+namespace {
+class RegUsageInfoPropagationPass : public MachineFunctionPass {
+
+public:
+  RegUsageInfoPropagationPass() : MachineFunctionPass(ID) {
+    PassRegistry &Registry = *PassRegistry::getPassRegistry();
+    initializeRegUsageInfoPropagationPassPass(Registry);
+  }
+
+  const char *getPassName() const override {
+    return "X86 Register Usage Information Propagation";
+  }
+
+  bool runOnMachineFunction(MachineFunction &MF) override;
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override;
+
+  static char ID;
+
+private:
+  static void setRegMask(MachineInstr &MI, const uint32_t *RegMask) {
+    for (MachineOperand &MO : MI.operands()) {
+      if (MO.isRegMask())
+        MO.setRegMask(RegMask);
+    }
+  }
+};
+}
+char RegUsageInfoPropagationPass::ID = 0;
+
+INITIALIZE_PASS_BEGIN(RegUsageInfoPropagationPass,
+                      "RegUsageInfoPropagationPass",
+                      "X86 Register Usage Information Propagation", false,
+                      false)
+INITIALIZE_PASS_DEPENDENCY(PhysicalRegisterUsageInfo)
+INITIALIZE_PASS_END(RegUsageInfoPropagationPass, "RegUsageInfoPropagationPass",
+                    "X86 Register Usage Information Propagation", false, false)
+
+FunctionPass *llvm::createRegUsageInfoPropPass() {
+  return new RegUsageInfoPropagationPass();
+}
+
+void RegUsageInfoPropagationPass::getAnalysisUsage(AnalysisUsage &AU) const {
+  AU.addRequired<PhysicalRegisterUsageInfo>();
+  AU.setPreservesAll();
+  MachineFunctionPass::getAnalysisUsage(AU);
+}
+
+bool RegUsageInfoPropagationPass::runOnMachineFunction(MachineFunction &MF) {
+  PhysicalRegisterUsageInfo *PRUI = &getAnalysis<PhysicalRegisterUsageInfo>();
+
+  DEBUG(dbgs() << " ++++++++++++++++++++ Register Usage Info Propagation Pass "
+                  "++++++++++++++++++++  \n");
+  DEBUG(dbgs() << "MachineFunction : " << MF.getName() << "\n");
+
+  bool changed = false;
+
+  for (auto &MBB : MF) {
+    for (auto &MI : MBB) {
+      // is it a call instr ?
+      if (MI.isCall()) {
+        DEBUG(
+            dbgs()
+            << "Call Instrunction Before Register Usage Info Propagation : \n");
+        DEBUG(MI.print(dbgs()));
+        DEBUG(dbgs() << "\n");
+
+        auto updateRegMask = [&](StringRef FuncName) {
+          const auto *RegMask = PRUI->getRegUsageInfo(FuncName);
+          if (RegMask) { // else skip optimization
+            setRegMask(MI, &(*RegMask)[0]);
+            changed = true;
+          }
+        };
+
+        MachineOperand &Operand = MI.getOperand(0);
+        if (Operand.isGlobal()) {
+          updateRegMask(Operand.getGlobal()->getName());
+        } else if (Operand.isSymbol()) {
+          updateRegMask(Operand.getSymbolName());
+        }
+
+        DEBUG(
+            dbgs()
+            << "Call Instrunction After Register Usage Info Propagation : \n");
+        DEBUG(MI.print(dbgs()));
+        DEBUG(dbgs() << "\n");
+      }
+    }
+  }
+
+  DEBUG(dbgs() << " +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"
+                  "++++++ \n");
+  return changed;
+}

lib/Target/X86/X86TargetMachine.cpp

 #include "llvm/IR/Function.h"
 #include "llvm/IR/LegacyPassManager.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Target/TargetOptions.h"
 using namespace llvm;
 
-static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
-                               cl::desc("Enable the machine combiner pass"),
-                               cl::init(true), cl::Hidden);
+static cl::opt<bool>
+    EnableMachineCombinerPass("x86-machine-combiner",
+extern cl::opt<bool> UseIPRA;
 
 namespace llvm {
 void initializeWinEHStatePassPass(PassRegistry &);
 }
 
 extern "C" void LLVMInitializeX86Target() {
   // Register the target.
   RegisterTargetMachine<X86TargetMachine> X(TheX86_32Target);
X86TargetMachine::getSubtargetImpl(const Function &F) const {
   }
   return I.get();
 }
 
 //===----------------------------------------------------------------------===//
 // Command line options for x86
 //===----------------------------------------------------------------------===//
 static cl::opt<bool>
     UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
                   cl::desc("Minimize AVX to SSE transition penalty"),
                   cl::init(true));
 
 //===----------------------------------------------------------------------===//
 // X86 TTI query.
 //===----------------------------------------------------------------------===//
 
 TargetIRAnalysis X86TargetMachine::getTargetIRAnalysis() {
   return TargetIRAnalysis([this](const Function &F) {
     return TargetTransformInfo(X86TTIImpl(this, F));
   });
 }
 
-
 //===----------------------------------------------------------------------===//
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
 
 namespace {
 /// X86 Code Generator Pass Configuration Options.
 class X86PassConfig : public TargetPassConfig {
 public:
   X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
       : TargetPassConfig(TM, PM) {}
 
   X86TargetMachine &getX86TargetMachine() const {
     return getTM<X86TargetMachine>();
   }
 
   void addIRPasses() override;
   bool addInstSelector() override;
   bool addILPOpts() override;
void X86PassConfig::addIRPasses() {
 
   TargetPassConfig::addIRPasses();
 }
 
 bool X86PassConfig::addInstSelector() {
   // Install an instruction selector.
   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
 
+  if (UseIPRA)
+    addPass(createRegUsageInfoPropPass());
+
   // For ELF, cleanup any local-dynamic TLS accesses.
   if (TM->getTargetTriple().isOSBinFormatELF() &&
       getOptLevel() != CodeGenOpt::None)
     addPass(createCleanupLocalDynamicTLSPass());
 
   addPass(createX86GlobalBaseRegPass());
 
   return false;
bool X86PassConfig::addPreISel() {
   return true;
 }
 
 void X86PassConfig::addPreRegAlloc() {
   if (getOptLevel() != CodeGenOpt::None)
     addPass(createX86OptimizeLEAs());
 
   addPass(createX86CallFrameOptimization());
   addPass(createX86WinAllocaExpander());
 }
 
 void X86PassConfig::addPostRegAlloc() {
   addPass(createX86FloatingPointStackifierPass());
 }
 
 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }