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[SelectionDAG] Attempt to split BITREVERSE vector legalization into BSWAP and BITREVERSE stages
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Authored by RKSimon on May 5 2016, 8:33 AM.

Details

Summary

For BITREVERSE, bit shifting/masking every bit in a vector element is a very lengthy procedure.

If the input vector type is a whole multiple of bytes wide then we can split this into a BSWAP shuffle stage (to reverse at the byte level) and then a BITREVERSE stage applied to each byte. Most vector capable targets can efficiently BSWAP using shuffles resulting in a considerable reduction in instructions.

With this patch targets would only need to implement a target specific vXi8 BITREVERSE implementation to efficiently reverse most legal vector types (I'm intending to add a SSSE3 PSHUFB implementation as an example).

James - This has definitely been tested on AARCH64 this time, at the moment I've just added a token rev32 CHECK but I can expand this to a more thorough set of CHECKs if you'd prefer? I know the x86 approach of scripted 'full' CHECKs isn't always popular ;-)

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Repository
rL LLVM

Event Timeline

RKSimon updated this revision to Diff 56295.May 5 2016, 8:33 AM
RKSimon retitled this revision from to [SelectionDAG] Attempt to split BITREVERSE vector legalization into BSWAP and BITREVERSE stages .
RKSimon updated this object.
RKSimon added reviewers: jmolloy, spatel, andreadb.
RKSimon set the repository for this revision to rL LLVM.
RKSimon added a subscriber: llvm-commits.
jmolloy accepted this revision.May 12 2016, 4:33 AM
jmolloy edited edge metadata.

LGTM

This revision is now accepted and ready to land.May 12 2016, 4:33 AM
This revision was automatically updated to reflect the committed changes.
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp