Give backends an opportunity to finish layout post-relaxation

[colinl]

Summary

Overriding this function gives targets access to the layout post-relaxation and before writing fragments to output.

Hexagon is using this to more intelligently pad nops by using a larger encoding for the previous instruction if possible.

We aren't able to do this with the existing writeNopData since the previous instructions have already been encoded to the output stream.

I imagine other targets would be able to do similar optimizations and possibly more.

include/llvm/MC/MCAsmBackend.h

   /// \return - True on success.
   virtual bool writeNopData(uint64_t Count, MCObjectWriter *OW) const = 0;
 
+  /// Give backend an opportunity to finish layout after relaxation
+  virtual void finishLayout(MCAssembler const &Asm,
+                            MCAsmLayout &Layout) const {}
+
   /// Handle any target-specific assembler flags. By default, do nothing.
   virtual void handleAssemblerFlag(MCAssemblerFlag Flag) {}
 

lib/MC/MCAssembler.cpp

   for (unsigned int i = 0, n = Layout.getSectionOrder().size(); i != n; ++i) {
     Layout.getFragmentOffset(&*Layout.getSectionOrder()[i]->rbegin());
   }
+  getBackend().finishLayout(*this, Layout);
 }

lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp

 #include "HexagonFixupKinds.h"
 #include "HexagonMCTargetDesc.h"
 #include "MCTargetDesc/HexagonBaseInfo.h"
+#include "MCTargetDesc/HexagonMCChecker.h"
+#include "MCTargetDesc/HexagonMCCodeEmitter.h"
 #include "MCTargetDesc/HexagonMCInstrInfo.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCAsmLayout.h"

   std::unique_ptr <MCInstrInfo> MCII;
   std::unique_ptr <MCInst *> RelaxTarget;
   MCInst * Extender;
+
+  void ReplaceInstruction(MCCodeEmitter &E, MCRelaxableFragment &RF,
+                          MCInst &HMB) const {
+    SmallVector<MCFixup, 4> Fixups;
+    SmallString<256> Code;
+    raw_svector_ostream VecOS(Code);
+    E.encodeInstruction(HMB, VecOS, Fixups, RF.getSubtargetInfo());
+
+    // Update the fragment.
+    RF.setInst(HMB);
+    RF.getContents() = Code;
+    RF.getFixups() = Fixups;
+  }
 public:
   HexagonAsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) :
     OSABI(OSABI), MCII (T.createMCInstrInfo()), RelaxTarget(new MCInst *),

     return Relaxable;
   }
 
-  /// MayNeedRelaxation - Check whether the given instruction may need
-  /// relaxation.
-  ///
-  /// \param Inst - The instruction to test.
   bool mayNeedRelaxation(MCInst const &Inst) const override {
-    assert(HexagonMCInstrInfo::isBundle(Inst));
-    bool PreviousIsExtender = false;
-    for (auto const &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
-      auto const &Inst = *I.getInst();
-      if (!PreviousIsExtender) {
-        if (HexagonMCInstrInfo::isDuplex(*MCII, Inst)) {
-          if (isInstRelaxable(*Inst.getOperand(0).getInst()) ||
-              isInstRelaxable(*Inst.getOperand(1).getInst()))
-            return true;
-        } else {
-          if (isInstRelaxable(Inst))
-            return true;
-        }
-      }
-      PreviousIsExtender = HexagonMCInstrInfo::isImmext(Inst);
-    }
-    return false;
+    return true;
   }
 
   /// fixupNeedsRelaxation - Target specific predicate for whether a given

     }
     return true;
   }
+
+  void finishLayout(MCAssembler const &Asm,
+                    MCAsmLayout &Layout) const override {
+    for (auto I : Layout.getSectionOrder()) {
+      auto &Fragments = I->getFragmentList();
+      for (auto &J : Fragments) {
+        switch (J.getKind()) {
+        default:
+          break;
+        case MCFragment::FT_Align: {
+          auto Size = Asm.computeFragmentSize(Layout, J);
+          for (auto K = J.getIterator();
+               K != Fragments.begin() && Size >= HEXAGON_PACKET_SIZE;) {
+            --K;
+            switch (K->getKind()) {
+            default:
+              break;
+            case MCFragment::FT_Align: {
+              // Don't pad before other alignments
+              Size = 0;
+              break;
+            }
+            case MCFragment::FT_Relaxable: {
+              auto &RF = cast<MCRelaxableFragment>(*K);
+              auto &Inst = const_cast<MCInst &>(RF.getInst());
+              while (Size > 0) {
+                MCInst *Nop = new (Asm.getContext()) MCInst;
+                Nop->setOpcode(Hexagon::A2_nop);
+                Inst.addOperand(MCOperand::createInst(Nop));
+                Size -= 4;
+                if (!HexagonMCChecker(
+                           *MCII, RF.getSubtargetInfo(), Inst, Inst,
+                           *Asm.getContext().getRegisterInfo()).check()) {
+                  Inst.erase(Inst.end() - 1);
+                  Size = 0;
+                }
+              }
+              HexagonMCShuffle(*MCII, RF.getSubtargetInfo(), Inst);
+              ReplaceInstruction(Asm.getEmitter(), RF, Inst);
+              Layout.invalidateFragmentsFrom(&RF);
+              Size = 0; // Only look back one instruction
+              break;
+            }
+            }
+          }
+        }
+        }
+      }
+    }
+  }
 };
 } // end anonymous namespace
 

test/MC/Hexagon/align.s

+# RUN: llvm-mc -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+
+# Verify that the .align directive emits the proper insn packets.
+
+{ r1 = sub(#1, r1) }
+# CHECK: 76414021 { r1 = sub(#1, r1)
+# CHECK-NEXT: 7f004000   nop
+# CHECK-NEXT: 7f004000   nop
+# CHECK-NEXT: 7f00c000   nop }
+
+.align 16
+{ r1 = sub(#1, r1)
+  r2 = sub(#1, r2) }
+# CHECK: 76414021 { r1 = sub(#1, r1)
+# CHECK-NEXT: 76424022   r2 = sub(#1, r2)
+# CHECK-NEXT: 7f004000  nop
+# CHECK-NEXT: 7f00c000   nop }
+
+.p2align 5
+{ r1 = sub(#1, r1)
+  r2 = sub(#1, r2)
+  r3 = sub(#1, r3) }
+# CHECK: 76434023   r3 = sub(#1, r3)
+# CHECK-NEXT: 7f00c000 nop }
+
+.align 16
+{ r1 = sub(#1, r1)
+  r2 = sub(#1, r2)
+  r3 = sub(#1, r3)
+  r4 = sub(#1, r4) }
+
+# Don't pad packets that can't be padded e.g. solo insts
+# CHECK: 9200c020 {  r0 = vextract(v0,r0) }
+r0 = vextract(v0, r0)
+.align 128
+# CHECK: 76414021 { r1 = sub(#1, r1)
+# CHECK-NEXT: 7f00c000   nop }
+{ r1 = sub(#1, r1) }
+
+.falign
+.align 8
+{ r1 = sub(#1, r1)
+  r2 = sub(#1, r2)
+  r3 = sub(#1, r3)  }
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