[mips] Fix select patterns for MIPS64

[sdardis]

Summary

When targetting MIPS64R6 some of the patterns for select were guarded by a
broken predicate. The predicate was supposed to test if a constant value
could fit in a 16 bit zero-extended field. Instead the value was tested to
fit in a 16 bit sign-extended field. For negative constants of native word
width this resulted in wrong code generation.

lib/Target/Mips/Mips64InstrInfo.td

 def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
 
 // Node immediate fits as 10-bit sign extended on target immediate.
 // e.g. seqi, snei
 def immSExt10_64 : PatLeaf<(i64 imm),
                            [{ return isInt<10>(N->getSExtValue()); }]>;
 
 def immZExt16_64 : PatLeaf<(i64 imm),
-                           [{ return isInt<16>(N->getZExtValue()); }]>;
+                           [{ return isUInt<16>(N->getZExtValue()); }]>;
 
 def immZExt5_64 : ImmLeaf<i64, [{ return Imm == (Imm & 0x1f); }]>;
 
 // Transformation function: get log2 of low 32 bits of immediate
 def Log2LO : SDNodeXForm<imm, [{
   return getImm(N, Log2_64((unsigned) N->getZExtValue()));
 }]>;
 

test/CodeGen/Mips/llvm-ir/select-int.ll

entry:
   ; FIXME: This shift is redundant
   ; SEL-64:     sll     $[[T0]], $[[T0]], 0
   ; SEL-64:     seleqz  $[[T1:[0-9]+]], $6, $[[T0]]
   ; SEL-64:     selnez  $[[T0]], $5, $[[T0]]
   ; SEL-64:     or      $2, $[[T0]], $[[T1]]
   %r = select i1 %s, i64 %x, i64 %y
   ret i64 %r
 }
+
+define i8* @tst_select_word_cst(i8* %a, i8* %b) {
+  ; ALL-LABEL: tst_select_i64_cst:
+
+  ; M2:         addiu   $1, $zero, -1
+  ; M2:         xor     $1, $5, $1
+  ; M2:         sltu    $1, $zero, $1
+  ; M2:         bnez    $1, $[[BB0:BB[0-9_]+]]
+  ; M2:         addiu   $2, $zero, 0
+  ; M2:         move    $2, $4
+  ; M2: $[[BB0]]:
+  ; M2:         jr      $ra
+
+  ; CMOV-32:    addiu   $1, $zero, -1
+  ; CMOV-32:    xor     $1, $5, $1
+  ; CMOV-32:    movn    $4, $zero, $1
+  ; CMOV-32:    jr      $ra
+  ; CMOV-32:    move    $2, $4
+
+  ; SEL-32:     addiu   $1, $zero, -1
+  ; SEL-32:     xor     $1, $5, $1
+  ; SEL-32:     sltu    $1, $zero, $1
+  ; SEL-32:     jr      $ra
+  ; SEL-32:     seleqz  $2, $4, $1
+
+  ; CMOV-64:    daddiu  $1, $zero, -1
+  ; CMOV-64:    xor     $1, $5, $1
+  ; CMOV-64:    movn    $4, $zero, $1
+  ; CMOV-64:    move    $2, $4
+
+  ; SEL-64:     daddiu  $1, $zero, -1
+  ; SEL-64:     xor     $1, $5, $1
+  ; SEL-64:     sltu    $1, $zero, $1
+  ; SEL-64: sll     $1, $1, 0
+  ; SEL-64: seleqz  $2, $4, $1
+
+  %cmp = icmp eq i8* %b, inttoptr (i64 -1 to i8*)
+  %r = select i1 %cmp, i8* %a, i8* null
+  ret i8* %r
+}