[Sparc] Add Soft Float support

[jacob_hansen]

Summary

This patch adds support for software floating point operations for Sparc targets.

This is the first in a set of patches to enable software floating point on Sparc. The next patch will enable the option to be used with Clang.

[jacob_hansen]

Reintroduced the header on line 1 of SparcISelLowering.h which was accidentally removed.

[jacob_hansen]

I had initially planned to do this over two patches but changed my mind a decided it was better to do it in one. This updated patch ensures that the soft-float attribute is retained when the target options are being reset (this change is identical to how other targets handles this situation).

[jyknight]

What's the ABI impact of this? Will this use the same calling convention as GCC does?

lib/Target/Sparc/SparcTargetMachine.cpp

87 ↗

(On Diff #54368)

I wonder what the point of having this redundant way of specifying soft-float via "use-soft-float" is. Clang seems to emit *both* use-soft-float=true and +soft-float. Hopefully this isn't needed these days. @echristo?

lib/Target/Sparc/SparcTargetMachine.h

25 ↗

(On Diff #54368)

Pretty sure this ought to be deleted while adding the SubtargetMap.

[jacob_hansen]

The change should use the same calling convention as GCC does, yes. I tested the change by linking with libgcc (from http://www.gaisler.com/index.php/products/operating-systems/bcc) which contains implementation of all the floating point procedures, that seemed to work perfectly. I also tested it by manually compiling a library of the builtins from the Compiler-RT project (Compiler-RT builtins are compatible with libgcc as noted on http://compiler-rt.llvm.org/), and that worked as well.

lib/Target/Sparc/SparcTargetMachine.cpp

87 ↗

(On Diff #54368)

I was wondering as well actually, didn't really find an answer to why this might be, but all targets seem to do this at the moment.

lib/Target/Sparc/SparcTargetMachine.h

25 ↗

(On Diff #54368)

I think you are right. Currently I use that object on line 100 of SparcTargetMachine.cpp to determine whether the target is currently 32 or 64 bit (using is64Bit()). Should I just create a new boolean variable here to determine this value instead of using the Subtarget object, or is there a better way?

[echristo]

lib/Target/Sparc/SparcSubtarget.cpp

54

Can you do this constification in a separate patch? (Feel free to just submit it).

lib/Target/Sparc/SparcTargetMachine.cpp

87 ↗

(On Diff #54368)

It's redundant as a subtarget feature for soft float wasn't across all targets yet, but if someone is willing to do that cleanup we can get rid of it. (Should do this in a separate patch as I know there are out of tree users etc...)

lib/Target/Sparc/SparcTargetMachine.h

25 ↗

(On Diff #54368)

This should be removed for sure. You should determine 32 or 64-bit ness in the TargetMachine based on what information you have in the TargetMachine configuration rather than the other. It can't change on a subtarget specific basis anyhow.

[jacob_hansen]

lib/Target/Sparc/SparcSubtarget.cpp

54

Sure, I submitted D19797 - This was my first patch so I do not have SVN write access at this time, could you submit it for me?

[jacob_hansen]

Removed the subtarget object from the TargetMachine and changed the way 32/64 bit ness is determined as requested.

The constification of TargetMachine arguments in SparcISelLowering and SparcSubtarget has been moved to D19797, which is now a dependency for this patch.

[jyknight]

Looks pretty good to me, but here's a few issues:

1. There's a *bunch* of trailing whitespace in your patch (e.g. most of getSubtargetImpl). If you run your patch through clang-format, it will fix that for you, either use git clang-format (if you're using git for your checkout -- which I'd recommend), or clang-format-diff as mentioned on http://clang.llvm.org/docs/ClangFormat.html, if you're using svn.

2. Your CHECKs in your test are incorrectly specified -- CHECK-LABEL is to specify the beginning of the function, *not* for the assertion itself. See http://llvm.org/docs/CommandGuide/FileCheck.html

3. You can simplify your test cases by getting rid of the alloca and loads: just move the values to function arguments.

Like this, for example:

 define i1 @test_gtdf2(double %a, double %b) #0 {
; CHECK-LABEL: test_gtdf2:
; CHECK: call __gtdf2
  %cmp = fcmp ogt double %a, %b
  ret i1 %cmp
}

5. There are no function call/return ABI tests. Can probably add to the existing 32abi.ll and 64abi.ll tests for this, by adding another RUN line.

E.g. for 64abi.ll

; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s --check-prefix=CHECK --check-prefix=HARD
; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc  -mattr=soft-float | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT

And then you just expand the CHECK: lines which differ for hard/soft-float to have a separate HARD: and SOFT: case, instead.

5. No tests for float or fp128. For fp128, it might make sense to have another RUN line on the existing tests in fp128.ll.

6. Nit: I'd rename the file "soft-float.ll", vs "softfloat.ll"

[jacob_hansen]

The following have been updated in this patch:

• trailing whitespace removed
• soft-float.ll tests is now correctly specified, the test cases have been simplified, added tests for fp128, and file was renamed from softfloat.ll
• adjusted the test cases in 32abi.ll and 62abi.ll to include testing for software floating point
• Adjusted behavior for fp128/quad floats so that the compiler-rt function calls (__addtf3 and so forth) are used for all floating point operations, including fp128, when soft-float option is enabled (before calls to _Q_add was used for fp128/quad floats when softfloat was enabled)

[jacob_hansen]

Accidentally removed two tests from 32abi.ll in the previous revision, this revision reintroduces them.

lib/Target/Sparc/Sparc.td

 
 def FeatureHardQuad
   : SubtargetFeature<"hard-quad-float", "HasHardQuad", "true",
                      "Enable quad-word floating point instructions">;
 
 def UsePopc : SubtargetFeature<"popc", "UsePopc", "true",
                                "Use the popc (population count) instruction">;
 
+def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
+                              "Use software emulation for floating point">;  
+
 //===----------------------------------------------------------------------===//
 // Register File, Calling Conv, Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
 include "SparcRegisterInfo.td"
 include "SparcCallingConv.td"
 include "SparcInstrInfo.td"
 

lib/Target/Sparc/SparcISelLowering.h

namespace SPISD {
     };
   }
 
   class SparcTargetLowering : public TargetLowering {
     const SparcSubtarget *Subtarget;
   public:
     SparcTargetLowering(TargetMachine &TM, const SparcSubtarget &STI);
     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
     
+    bool useSoftFloat() const override;
+    
     /// computeKnownBitsForTargetNode - Determine which of the bits specified
     /// in Mask are known to be either zero or one and return them in the
     /// KnownZero/KnownOne bitsets.
     void computeKnownBitsForTargetNode(const SDValue Op,
                                        APInt &KnownZero,
                                        APInt &KnownOne,
                                        const SelectionDAG &DAG,
                                        unsigned Depth = 0) const override;

lib/Target/Sparc/SparcISelLowering.cpp

SparcTargetLowering::SparcTargetLowering(TargetMachine &TM,
   // matters much whether it's ZeroOrOneBooleanContent, or
   // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
   // former.
   setBooleanContents(ZeroOrOneBooleanContent);
   setBooleanVectorContents(ZeroOrOneBooleanContent);
 
   // Set up the register classes.
   addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
+  if (!Subtarget->useSoftFloat()) {
     addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
     addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
     addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
+  }
   if (Subtarget->is64Bit()) {
     addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
   } else {
     // On 32bit sparc, we define a double-register 32bit register
     // class, as well. This is modeled in LLVM as a 2-vector of i32.
     addRegisterClass(MVT::v2i32, &SP::IntPairRegClass);
 
     // ...but almost all operations must be expanded, so set that as
if (Subtarget->hasHardQuad()) {
     }
   }
 
   setMinFunctionAlignment(2);
 
   computeRegisterProperties(Subtarget->getRegisterInfo());
 }
 
+bool SparcTargetLowering::useSoftFloat() const {
+  return Subtarget->useSoftFloat();
+}
+
 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch ((SPISD::NodeType)Opcode) {
   case SPISD::FIRST_NUMBER: break;
   case SPISD::CMPICC:     return "SPISD::CMPICC";
   case SPISD::CMPFCC:     return "SPISD::CMPFCC";
   case SPISD::BRICC:      return "SPISD::BRICC";
   case SPISD::BRXCC:      return "SPISD::BRXCC";
   case SPISD::BRFCC:      return "SPISD::BRFCC";

lib/Target/Sparc/SparcSubtarget.h

 class SparcSubtarget : public SparcGenSubtargetInfo {
   virtual void anchor();
   bool IsV9;
   bool V8DeprecatedInsts;
   bool IsVIS, IsVIS2, IsVIS3;
   bool Is64Bit;
   bool HasHardQuad;
   bool UsePopc;
+  bool UseSoftFloat;
   SparcInstrInfo InstrInfo;
   SparcTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
   SparcFrameLowering FrameLowering;
 
 public:
   SparcSubtarget(const Triple &TT, const std::string &CPU,
                  const std::string &FS, TargetMachine &TM, bool is64bit);
public:
 
   bool isV9() const { return IsV9; }
   bool isVIS() const { return IsVIS; }
   bool isVIS2() const { return IsVIS2; }
   bool isVIS3() const { return IsVIS3; }
   bool useDeprecatedV8Instructions() const { return V8DeprecatedInsts; }
   bool hasHardQuad() const { return HasHardQuad; }
   bool usePopc() const { return UsePopc; }
+  bool useSoftFloat() const { return UseSoftFloat; }
 
   /// ParseSubtargetFeatures - Parses features string setting specified
   /// subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
   SparcSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 
   bool is64Bit() const { return Is64Bit; }
 

lib/Target/Sparc/SparcSubtarget.cpp

 
 SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
                                                                 StringRef FS) {
   IsV9 = false;
   V8DeprecatedInsts = false;
   IsVIS = false;
   HasHardQuad = false;
   UsePopc = false;
+  UseSoftFloat = false;
   
   // Determine default and user specified characteristics
   std::string CPUName = CPU;
   if (CPUName.empty())
     CPUName = (Is64Bit) ? "v9" : "v8";
 
   // Parse features string.
   ParseSubtargetFeatures(CPUName, FS);
 
   // Popc is a v9-only instruction.
   if (!IsV9)
     UsePopc = false;
 
   return *this;
 }
 
 SparcSubtarget::SparcSubtarget(const Triple &TT, const std::string &CPU,
                                const std::string &FS, TargetMachine &TM,
                                bool is64Bit)
     : SparcGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
       FrameLowering(*this) {}
 
 int SparcSubtarget::getAdjustedFrameSize(int frameSize) const {
 
   if (is64Bit()) {

test/CodeGen/SPARC/softfloat.ll

+; RUN: llc -march=sparc -mattr=soft-float -O0 < %s | FileCheck %s
+
+; Arithmetic functions
+define double @test_add() #0 {
+entry:
+  %a = alloca double, align 8
+  %b = alloca double, align 8
+  %0 = load double, double* %a, align 8
+  %1 = load double, double* %b, align 8
+  %add = fadd double %0, %1
+  ret double %add
+
+  ; CHECK-LABEL:      __adddf3
+}
+
+define double @test_mul() #0 {
+entry:
+  %a = alloca double, align 8
+  %b = alloca double, align 8
+  %0 = load double, double* %a, align 8
+  %1 = load double, double* %b, align 8
+  %mul = fmul double %0, %1
+  ret double %mul
+
+  ; CHECK-LABEL:      __muldf3
+}
+
+define double @test_sub() #0 {
+entry:
+  %a = alloca double, align 8
+  %b = alloca double, align 8
+  %0 = load double, double* %a, align 8
+  %1 = load double, double* %b, align 8
+  %sub = fsub double %0, %1
+  ret double %sub
+
+  ; CHECK-LABEL:      __subdf3
+}
+
+define double @test_div() #0 {
+entry:
+  %a = alloca double, align 8
+  %b = alloca double, align 8
+  %0 = load double, double* %a, align 8
+  %1 = load double, double* %b, align 8
+  %div = fdiv double %0, %1
+  ret double %div
+
+  ; CHECK-LABEL:      __divdf3
+}
+
+; Comparison functions
+
+define i1 @test_unorddf2() #0 {
+entry:
+  %a = alloca double, align 8
+  %b = alloca double, align 8
+  %0 = load double, double* %a, align 8
+  %1 = load double, double* %b, align 8
+  %cmp = fcmp uno double %0, %1
+  ret i1 %cmp
+
+  ; CHECK-LABEL:     __unorddf2
+}
+
+define i1 @test_eqdf2() #0 {
+entry:
+  %a = alloca double, align 8
+  %b = alloca double, align 8
+  %0 = load double, double* %a, align 8
+  %1 = load double, double* %b, align 8
+  %cmp = fcmp oeq double %0, %1
+  ret i1 %cmp
+
+  ; CHECK-LABEL:      __eqdf2
+}
+
+define i1 @test_nedf2() #0 {
+entry:
+  %a = alloca double, align 8
+  %b = alloca double, align 8
+  %0 = load double, double* %a, align 8
+  %1 = load double, double* %b, align 8
+  %cmp = fcmp une double %0, %1
+  ret i1 %cmp
+
+  ; CHECK-LABEL:     __nedf2
+}
+
+define i1 @test_gedf2() #0 {
+entry:
+  %a = alloca double, align 8
+  %b = alloca double, align 8
+  %0 = load double, double* %a, align 8
+  %1 = load double, double* %b, align 8
+  %cmp = fcmp oge double %0, %1
+  ret i1 %cmp
+
+  ; CHECK-LABEL:     __gedf2
+}
+
+define i1 @test_ltdf2() #0 {
+entry:
+  %a = alloca double, align 8
+  %b = alloca double, align 8
+  %0 = load double, double* %a, align 8
+  %1 = load double, double* %b, align 8
+  %cmp = fcmp olt double %0, %1
+  ret i1 %cmp
+
+  ; CHECK-LABEL:     __ltdf2
+}
+
+define i1 @test_ledf2() #0 {
+entry:
+  %a = alloca double, align 8
+  %b = alloca double, align 8
+  %0 = load double, double* %a, align 8
+  %1 = load double, double* %b, align 8
+  %cmp = fcmp ole double %0, %1
+  ret i1 %cmp
+
+  ; CHECK-LABEL:     __ledf2
+}
+
+define i1 @test_gtdf2() #0 {
+entry:
+  %a = alloca double, align 8
+  %b = alloca double, align 8
+  %0 = load double, double* %a, align 8
+  %1 = load double, double* %b, align 8
+  %cmp = fcmp ogt double %0, %1
+  ret i1 %cmp
+
+  ; CHECK-LABEL:      __gtdf2
+}