[ppc64] fix bug in prologue that mfocrf's cr operand should be explict state instead of implicit

[cycheng]

Summary

This patch resolves https://llvm.org/bugs/show_bug.cgi?id=27414

[kbarton]

lib/Target/PowerPC/PPCFrameLowering.cpp

846–847

Why does this need to be put into a variable? I only see it used once below - can you not just put RegState::ImplicitKill directly in the MIB.addReg call below?

[mgrang]

Can you also add the testcase mentioned in the bug as a unit test?

[cycheng]

In D19255#411042, @mgrang wrote:

Can you also add the testcase mentioned in the bug as a unit test?

Sure, I will add "-verify-machineinstrs" in test/CodeGen/PowerPC/crsave.ll, the option can catch this issue (I've tested)

lib/Target/PowerPC/PPCFrameLowering.cpp

846–847

Do you mean:

MIB.addReg(MustSaveCRs[i], MfcrOpcode == PPC::MFCR8 ? RegState::ImplicitKill : RegState::Kill);

[kbarton]

LGTM.

lib/Target/PowerPC/PPCFrameLowering.cpp

846–847

Sorry, for some reason I missed the initialization. This is fine as is.

[cycheng]

Update testcase

[cycheng]

Committed r267660

lib/Target/PowerPC/PPCFrameLowering.cpp

void PPCFrameLowering::emitPrologue(MachineFunction &MF,
   // If we need to spill the CR and the LR but we don't have two separate
   // registers available, we must spill them one at a time
   if (MustSaveCR && SingleScratchReg && MustSaveLR) {
     // In the ELFv2 ABI, we are not required to save all CR fields.
     // If only one or two CR fields are clobbered, it is more efficient to use
     // mfocrf to selectively save just those fields, because mfocrf has short
     // latency compares to mfcr.
     unsigned MfcrOpcode = PPC::MFCR8;
-    if (isELFv2ABI && MustSaveCRs.size() == 1)
+    unsigned CrState = RegState::ImplicitKill;
+    if (isELFv2ABI && MustSaveCRs.size() == 1) {
       MfcrOpcode = PPC::MFOCRF8;
+      CrState = RegState::Kill;
+    }
     MachineInstrBuilder MIB =
       BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
     for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
-      MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
+      MIB.addReg(MustSaveCRs[i], CrState);
     BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
       .addReg(TempReg, getKillRegState(true))
       .addImm(8)
       .addReg(SPReg);
   }
 
   if (MustSaveLR)
     BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
 
   if (MustSaveCR &&
       !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64
     // In the ELFv2 ABI, we are not required to save all CR fields.
     // If only one or two CR fields are clobbered, it is more efficient to use
     // mfocrf to selectively save just those fields, because mfocrf has short
     // latency compares to mfcr.
     unsigned MfcrOpcode = PPC::MFCR8;
-    if (isELFv2ABI && MustSaveCRs.size() == 1)
+    unsigned CrState = RegState::ImplicitKill;
+    if (isELFv2ABI && MustSaveCRs.size() == 1) {
       MfcrOpcode = PPC::MFOCRF8;
+      CrState = RegState::Kill;
+    }
     MachineInstrBuilder MIB =
       BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
     for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
-      MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
+      MIB.addReg(MustSaveCRs[i], CrState);
   }
 
   if (HasFP)
     // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
     BuildMI(MBB, MBBI, dl, StoreInst)
       .addReg(FPReg)
       .addImm(FPOffset)
       .addReg(SPReg);

test/CodeGen/PowerPC/crsave.ll

 ; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC32
 ; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC64
-; RUN: llc -O0 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC64-ELFv2
+; RUN: llc -O0 -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s -check-prefix=PPC64-ELFv2
 
 declare void @foo()
 
 define i32 @test_cr2() nounwind uwtable {
 entry:
   %ret = alloca i32, align 4
   %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmpw 2,$2,$1\0A\09mfcr $0", "=r,r,r,r,r,~{cr2}"(i32 1, i32 2, i32 3, i32 0) nounwind
   store i32 %0, i32* %ret, align 4