[scan-build] fix warnings emitted on LLVM CodeGen code base

[apelete]

Summary

Fix logic error warnings of the type "called C++ object pointer is
null" emitted by Clang Static Analyzer on the following files:

• lib/CodeGen/AsmPrinter/DwarfUnit.cpp,
• lib/CodeGen/ScheduleDAGInstrs.cpp,
• lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp.

Signed-off-by: Apelete Seketeli <[e-mail]>

[jlebar]

lgtm for NVPTX changes.

[apelete]

Ping :).
Can someone help this one find its way into he main repo ?

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[clang-analyzer] fix warnings emitted on llvm code base

Changes since last revision:

• lib/Transforms/Vectorize/SLPVectorizer.cpp: rework the fix for the warning in BoUpSLP::optimizeGatherSequence() and fix another one in BoUpSLP::BlockScheduling::tryScheduleBundle(),

• lib/Analysis/LoopInfo.cpp: rework the fix in UnloopUpdater::getNearestLoop().

[apelete]

[clang-analyzer] fix warnings emitted on llvm code base

Changes since last revision:

• fast forward rebase on git master branch.

[apelete]

Waiting for review, could someone please have a look at this one ?

[apelete]

[scan-build] fix warnings emitted on LLVM CodeGen code base

Changes since last revision:

• split patch into CodeGen changes unit to ease review process,
• cherry-pick CodeGen changes from D19498.

[MatzeB]

LGTM

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

6454

... "must not be NULL"

lib/Analysis/LoopInfo.cpp

 
 /// Return the nearest parent loop among this block's successors. If a successor
 /// is a subloop header, consider its parent to be the nearest parent of the
 /// subloop's exits.
 ///
 /// For subloop blocks, simply update SubloopParents and return NULL.
 Loop *UnloopUpdater::getNearestLoop(BasicBlock *BB, Loop *BBLoop) {
 
+  assert(Unloop && "Unloop cannot be NULL");
+
   // Initially for blocks directly contained by Unloop, NearLoop == Unloop and
   // is considered uninitialized.
   Loop *NearLoop = BBLoop;
 
   Loop *Subloop = nullptr;
   if (NearLoop != Unloop && Unloop->contains(NearLoop)) {
     Subloop = NearLoop;
     // Find the subloop ancestor that is directly contained within Unloop.

lib/CodeGen/AsmPrinter/DwarfUnit.cpp

for (unsigned i = 0, N = Fields.size(); i < N; ++i) {
     auto *DT = cast<DIDerivedType>(Fields[i]);
     StringRef fieldName = DT->getName();
     if (fieldName == "__forwarding")
       forwardingField = DT;
     else if (fieldName == varName)
       varField = DT;
   }
 
+  assert(forwardingField && "forwarding field must not be NULL");
+  assert(varField && "var field must not be NULL");
+
   // Get the offsets for the forwarding field and the variable field.
   unsigned forwardingFieldOffset = forwardingField->getOffsetInBits() >> 3;
   unsigned varFieldOffset = varField->getOffsetInBits() >> 2;
 
   // Decode the original location, and use that as the start of the byref
   // variable's location.
   DIELoc *Loc = new (DIEValueAllocator) DIELoc;
 

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

static void GetRegistersForValue(SelectionDAG &DAG,
 
   MVT RegVT;
   EVT ValueVT = OpInfo.ConstraintVT;
 
   // If this is a constraint for a specific physical register, like {r17},
   // assign it now.
   if (unsigned AssignedReg = PhysReg.first) {
     const TargetRegisterClass *RC = PhysReg.second;
+
+    assert(RC && "TargetRegisterClass needs to be not NULL");
+
     if (OpInfo.ConstraintVT == MVT::Other)
       ValueVT = *RC->vt_begin();
 
     // Get the actual register value type.  This is important, because the user
     // may have asked for (e.g.) the AX register in i32 type.  We need to
     // remember that AX is actually i16 to get the right extension.
     RegVT = *RC->vt_begin();
 

lib/MC/MCParser/AsmParser.cpp

bool AsmParser::Run(bool NoInitialTextSection, bool NoFinalize) {
 
   HadError = false;
   AsmCond StartingCondState = TheCondState;
 
   // If we are generating dwarf for assembly source files save the initial text
   // section and generate a .file directive.
   if (getContext().getGenDwarfForAssembly()) {
     MCSection *Sec = getStreamer().getCurrentSection().first;
-    if (!Sec->getBeginSymbol()) {
+    if (Sec && !Sec->getBeginSymbol()) {
       MCSymbol *SectionStartSym = getContext().createTempSymbol();
       getStreamer().EmitLabel(SectionStartSym);
       Sec->setBeginSymbol(SectionStartSym);
     }
     bool InsertResult = getContext().addGenDwarfSection(Sec);
     assert(InsertResult && ".text section should not have debug info yet");
     (void)InsertResult;
     getContext().setGenDwarfFileNumber(getStreamer().EmitDwarfFileDirective(

lib/Target/Hexagon/HexagonInstrInfo.cpp

bool HexagonInstrInfo::isPredicable(MachineInstr &MI) const {
   if (!isPred)
     return false;
 
   const int Opc = MI.getOpcode();
   int NumOperands = MI.getNumOperands();
 
   // Keep a flag for upto 4 operands in the instructions, to indicate if
   // that operand has been constant extended.
-  bool OpCExtended[4];
+  bool OpCExtended[4] = {false};
   if (NumOperands > 4)
     NumOperands = 4;
 
   for (int i = 0; i < NumOperands; i++)
     OpCExtended[i] = (isOperandExtended(&MI, i) && isConstExtended(&MI));
 
   switch(Opc) {
   case Hexagon::A2_tfrsi:

lib/Target/NVPTX/NVPTXInstrInfo.cpp

bool NVPTXInstrInfo::AnalyzeBranch(
   // Get the instruction before it if it's a terminator.
   MachineInstr *SecondLastInst = I;
 
   // If there are three terminators, we don't know what sort of block this is.
   if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
     return true;
 
   // If the block ends with NVPTX::GOTO and NVPTX:CBranch, handle it.
-  if (SecondLastInst->getOpcode() == NVPTX::CBranch &&
+  if (SecondLastInst && SecondLastInst->getOpcode() == NVPTX::CBranch &&
       LastInst->getOpcode() == NVPTX::GOTO) {
     TBB = SecondLastInst->getOperand(1).getMBB();
     Cond.push_back(SecondLastInst->getOperand(0));
     FBB = LastInst->getOperand(0).getMBB();
     return false;
   }
 
   // If the block ends with two NVPTX:GOTOs, handle it.  The second one is not
   // executed, so remove it.
-  if (SecondLastInst->getOpcode() == NVPTX::GOTO &&
+  if (SecondLastInst && SecondLastInst->getOpcode() == NVPTX::GOTO &&
       LastInst->getOpcode() == NVPTX::GOTO) {
     TBB = SecondLastInst->getOperand(0).getMBB();
     I = LastInst;
     if (AllowModify)
       I->eraseFromParent();
     return false;
   }
 

lib/Target/TargetRecip.cpp

 }
 
 bool TargetRecip::parseGlobalParams(const std::string &Arg) {
   StringRef ArgSub = Arg;
 
   // Look for an optional setting of the number of refinement steps needed
   // for this type of reciprocal operation.
   size_t RefPos;
-  uint8_t RefSteps;
+  uint8_t RefSteps = 0;
   StringRef RefStepString;
   if (parseRefinementStep(ArgSub, RefPos, RefSteps)) {
     // Split the string for further processing.
     RefStepString = ArgSub.substr(RefPos + 1);
     ArgSub = ArgSub.substr(0, RefPos);
   }
   bool Enable;
   bool UseDefaults;
for (unsigned i = 0; i != NumArgs; ++i) {
     StringRef Val = Args[i];
     
     bool IsDisabled = Val[0] == DisabledPrefix;
     // Ignore the disablement token for string matching.
     if (IsDisabled)
       Val = Val.substr(1);
     
     size_t RefPos;
-    uint8_t RefSteps;
+    uint8_t RefSteps = 0;
     StringRef RefStepString;
     if (parseRefinementStep(Val, RefPos, RefSteps)) {
       // Split the string for further processing.
       RefStepString = Val.substr(RefPos + 1);
       Val = Val.substr(0, RefPos);
     }
 
     RecipIter Iter = RecipMap.find(Val);

lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp

bool InstCombiner::SimplifyStoreAtEndOfBlock(StoreInst &SI) {
   if (++PI != pred_end(DestBB))
     return false;
 
   // Bail out if all the relevant blocks aren't distinct (this can happen,
   // for example, if SI is in an infinite loop)
   if (StoreBB == DestBB || OtherBB == DestBB)
     return false;
 
+  assert(OtherBB && "BasicBlock needs to be not NULL");
+
   // Verify that the other block ends in a branch and is not otherwise empty.
   BasicBlock::iterator BBI(OtherBB->getTerminator());
   BranchInst *OtherBr = dyn_cast<BranchInst>(BBI);
   if (!OtherBr || BBI == OtherBB->begin())
     return false;
 
   // If the other block ends in an unconditional branch, check for the 'if then
   // else' case.  there is an instruction before the branch.

lib/Transforms/Scalar/ConstantHoisting.cpp

Instruction *ConstantHoisting::findMatInsertPt(Instruction *Inst,
   BasicBlock *IDom = DT->getNode(Inst->getParent())->getIDom()->getBlock();
   return IDom->getTerminator();
 }
 
 /// \brief Find an insertion point that dominates all uses.
 Instruction *ConstantHoisting::
 findConstantInsertionPoint(const ConstantInfo &ConstInfo) const {
   assert(!ConstInfo.RebasedConstants.empty() && "Invalid constant info entry.");
+  assert(Entry && "Entry basic block cannot be NULL");
   // Collect all basic blocks.
   SmallPtrSet<BasicBlock *, 8> BBs;
   for (auto const &RCI : ConstInfo.RebasedConstants)
     for (auto const &U : RCI.Uses)
       BBs.insert(findMatInsertPt(U.Inst, U.OpndIdx)->getParent());
 
   if (BBs.count(Entry))
     return &Entry->front();

lib/Transforms/Scalar/RewriteStatepointsForGC.cpp

#endif
       // Find the instruction which produces the base for each input.  We may
       // need to insert a bitcast.
       Value *Base = getBaseForInput(InVal, BaseEE);
       BaseEE->setOperand(0, Base);
     } else {
       auto *BaseIE = cast<InsertElementInst>(State.getBase());
       auto *BdvIE = cast<InsertElementInst>(BDV);
       auto UpdateOperand = [&](int OperandIdx) {
+        assert(BaseIE && "base InsertElementInst must not be NULL");
         Value *InVal = BdvIE->getOperand(OperandIdx);
         Value *Base = getBaseForInput(InVal, BaseIE);
         BaseIE->setOperand(OperandIdx, Base);
       };
       UpdateOperand(0); // vector operand
       UpdateOperand(1); // scalar operand
     }
 

lib/Transforms/Vectorize/SLPVectorizer.cpp

std::stable_sort(CSEWorkList.begin(), CSEWorkList.end(),
     return DT->properlyDominates(A, B);
   });
 
   // Perform O(N^2) search over the gather sequences and merge identical
   // instructions. TODO: We can further optimize this scan if we split the
   // instructions into different buckets based on the insert lane.
   SmallVector<Instruction *, 16> Visited;
   for (auto I = CSEWorkList.begin(), E = CSEWorkList.end(); I != E; ++I) {
+    assert(I && "Worklist cannot be NULL");
     assert((I == CSEWorkList.begin() || !DT->dominates(*I, *std::prev(I))) &&
            "Worklist not sorted properly!");
     BasicBlock *BB = (*I)->getBlock();
     // For all instructions in blocks containing gather sequences:
     for (BasicBlock::iterator it = BB->begin(), e = BB->end(); it != e;) {
       Instruction *In = &*it++;
       if (!isa<InsertElementInst>(In) && !isa<ExtractElementInst>(In))
         continue;

tools/dsymutil/DwarfLinker.cpp

if (AttrSpec.Form == dwarf::DW_FORM_exprloc) {
     Linker.DIELocs.push_back(Loc);
   } else {
     Block = new (DIEAlloc) DIEBlock;
     Linker.DIEBlocks.push_back(Block);
   }
   Attr = Loc ? static_cast<DIEValueList *>(Loc)
              : static_cast<DIEValueList *>(Block);
 
+  assert(Attr && "DIEValue list needs to be not NULL");
+
   if (Loc)
     Value = DIEValue(dwarf::Attribute(AttrSpec.Attr),
                      dwarf::Form(AttrSpec.Form), Loc);
   else
     Value = DIEValue(dwarf::Attribute(AttrSpec.Attr),
                      dwarf::Form(AttrSpec.Form), Block);
   ArrayRef<uint8_t> Bytes = *Val.getAsBlock();
   for (auto Byte : Bytes)