Permit memory operands in ins/outs instructions

[niravd]

Summary

[x86] (PR15455) While (ins|outs)[bwld] instructions do not take %dx as a
memory operand, various unofficial references do and objdump
disassembles to this format. Extend special treatment of
similar (in|out)[bwld] operations.

[niravd]

Polite Ping for review.

[niravd]

Ping.

[niravd]

Ping

[ab]

Gross, but LGTM.

test/MC/X86/x86-32.s

603

It's *really* minor, but the inconsistent newlines make me twitch: either separate the CHECKs from the instructions, or don't ;)

625

space

test/MC/X86/x86-64.s

284

space

290

Comment in a separate line?

lib/Target/X86/AsmParser/X86AsmParser.cpp

if (IsFp && Operands.size() == 1) {
     const char *Repl = StringSwitch<const char *>(Name)
       .Case("fsub", "fsubp")
       .Case("fdiv", "fdivp")
       .Case("fsubr", "fsubrp")
       .Case("fdivr", "fdivrp");
     static_cast<X86Operand &>(*Operands[0]).setTokenValue(Repl);
   }
 
-  // This is a terrible hack to handle "out[bwl]? %al, (%dx)" ->
+  // This is a terrible hack to handle "out[s]?[bwl]? %al, (%dx)" ->
   // "outb %al, %dx".  Out doesn't take a memory form, but this is a widely
   // documented form in various unofficial manuals, so a lot of code uses it.
-  if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
+  if ((Name == "outb" || Name == "outsb" || Name == "outw" || Name == "outsw" ||
+       Name == "outl" || Name == "outsl" || Name == "out" || Name == "outs") &&
       Operands.size() == 3) {
     X86Operand &Op = (X86Operand &)*Operands.back();
     if (Op.isMem() && Op.Mem.SegReg == 0 &&
         isa<MCConstantExpr>(Op.Mem.Disp) &&
         cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
         Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
       SMLoc Loc = Op.getEndLoc();
       Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
     }
   }
-  // Same hack for "in[bwl]? (%dx), %al" -> "inb %dx, %al".
-  if ((Name == "inb" || Name == "inw" || Name == "inl" || Name == "in") &&
+  // Same hack for "in[s]?[bwl]? (%dx), %al" -> "inb %dx, %al".
+  if ((Name == "inb" || Name == "insb" || Name == "inw" || Name == "insw" ||
+       Name == "inl" || Name == "insl" || Name == "in" || Name == "ins") &&
       Operands.size() == 3) {
     X86Operand &Op = (X86Operand &)*Operands[1];
     if (Op.isMem() && Op.Mem.SegReg == 0 &&
         isa<MCConstantExpr>(Op.Mem.Disp) &&
         cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
         Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
       SMLoc Loc = Op.getEndLoc();
       Operands[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);

test/MC/X86/x86-32.s

// rdar://8416805
   setnle  %bl
 
 // PR8686
         setneb  %cl // CHECK: setne %cl
   setcb %bl // CHECK: setb %bl
   setnaeb %bl // CHECK: setb %bl
 
 
+// PR8114
+// CHECK: outb  %al, %dx
+// CHECK: outb  %al, %dx
+// CHECK: outw  %ax, %dx
+// CHECK: outw  %ax, %dx
+// CHECK: outl  %eax, %dx
+// CHECK: outl  %eax, %dx
+
+out %al, (%dx)
+outb  %al, (%dx)
+out %ax, (%dx)
+outw  %ax, (%dx)
+out %eax, (%dx)
+outl  %eax, (%dx)
+
+// CHECK: inb %dx, %al
+// CHECK: inb %dx, %al
+// CHECK: inw %dx, %ax
+// CHECK: inw %dx, %ax
+// CHECK: inl %dx, %eax
+// CHECK: inl %dx, %eax
+
+in  (%dx), %al
+inb (%dx), %al
+in  (%dx), %ax
+inw (%dx), %ax
+in  (%dx), %eax
+inl (%dx), %eax
+
+//PR15455
+// CHECK: outsw (%esi), %dx
+// CHECK: outsb (%esi), %dx
+// CHECK: outsw (%esi), %dx
+// CHECK: outsl (%esi), %dx
+
+outs  (%esi), (%dx)
+outsb (%esi), (%dx)
+outsw (%esi), (%dx)
+outsl (%esi), (%dx)
+
+// CHECK: insw  %dx, %es:(%edi)
+// CHECK: insb  %dx, %es:(%edi)
+// CHECK: insw  %dx, %es:(%edi)
+// CHECK: insl  %dx, %es:(%edi) 
+ins   (%dx), %es:(%edi)
+insb  (%dx), %es:(%edi)
+insw  (%dx), %es:(%edi)
+insl  (%dx), %es:(%edi)
+  
 // CHECK: lcalll  $31438, $31438
 // CHECK: lcalll  $31438, $31438
 // CHECK: ljmpl $31438, $31438
 // CHECK: ljmpl $31438, $31438
 
 calll $0x7ace,$0x7ace
 lcalll  $0x7ace,$0x7ace
 jmpl  $0x7ace,$0x7ace

test/MC/X86/x86-64.s

 
 in  (%dx), %al
 inb (%dx), %al
 in  (%dx), %ax
 inw (%dx), %ax
 in  (%dx), %eax
 inl (%dx), %eax
 
+//PR15455
+// CHECK: outsw (%rsi), %dx
+// CHECK: outsb (%rsi), %dx
+// CHECK: outsw (%rsi), %dx
+// CHECK: outsl (%rsi), %dx
+
+outs  (%rsi), (%dx) //permitted invalid memory form
+outsb (%rsi), (%dx)
+outsw (%rsi), (%dx)
+outsl (%rsi), (%dx)
+
+// CHECK: insw  %dx, %es:(%rdi)
+// CHECK: insb  %dx, %es:(%rdi)
+// CHECK: insw  %dx, %es:(%rdi)
+// CHECK: insl  %dx, %es:(%rdi) 
+ins (%dx), %es:(%rdi)
+insb  (%dx), %es:(%rdi)
+insw  (%dx), %es:(%rdi)
+insl  (%dx), %es:(%rdi)
+
 // rdar://8431422
 
 // CHECK: fxch %st(1)
 // CHECK: fucom %st(1)
 // CHECK: fucomp %st(1)
 // CHECK: faddp %st(1)
 // CHECK: faddp %st(0)
 // CHECK: fsubp %st(1)