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[AArch64] Do not lower scalar sdiv/udiv to a shifts + mul sequence when optimizing for minsize
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Authored by haicheng on Mar 27 2016, 8:22 PM.

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Summary

Mimic what x86 does when optimizing sdiv/udiv for minsize.

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rL LLVM

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haicheng updated this revision to Diff 51768.Mar 27 2016, 8:22 PM
haicheng retitled this revision from to [AArch64] Do not lower scalar sdiv/udiv to a shifts + mul sequence when optimizing for minsize.
haicheng updated this object.
haicheng added reviewers: mcrosier, gberry, mssimpso.
haicheng set the repository for this revision to rL LLVM.
haicheng added a subscriber: llvm-commits.
jmolloy accepted this revision.Mar 28 2016, 2:45 AM
jmolloy added a reviewer: jmolloy.
jmolloy added a subscriber: jmolloy.

LGTM, thanks!

This revision is now accepted and ready to land.Mar 28 2016, 2:45 AM
haicheng closed this revision.Mar 29 2016, 6:24 AM

Committed in r264606. Thank you for reviewing this, James and Junmo.