This is an archive of the discontinued LLVM Phabricator instance.

Differential D18353

Release notes update
ClosedPublic

Authored by delena on Mar 22 2016, 8:27 AM.

Details

Reviewers
Ayal
kbsmith1
Commits
rG2c35e20dd7f2: Added 2 notes 1) Skylake and KNL support for X86 2) masked intrinsics…
rL264703: Added 2 notes

Diff Detail

Repository
rL LLVM

Event Timeline

delena updated this revision to Diff 51290.Mar 22 2016, 8:27 AM
delena retitled this revision from to Release notes update.
delena updated this object.
delena added a reviewer: Ayal.
delena set the repository for this revision to rL LLVM.
Ayal added inline comments.Mar 22 2016, 11:04 AM
../docs/ReleaseNotes.rst
121 ↗(On Diff #51290)

make sure quotes are around each of the intrinsics separately:
`llvm.masked.load`
and
`llvm.masked.store`

241 ↗(On Diff #51290)
  • LLVM now supports Intel's CPU codenamed Skylake Server with its AVX-512 extensions using
243 ↗(On Diff #51290)

can put F first, then alphabetically, and shorten to:
AVX-512{F, BW, CD, DQ, VL}.

245 ↗(On Diff #51290)

LLVM now supports the Intel's CPU codenamed Knights Landing with its AVX-512 extensions using
`-march=knl`. The switch enables the ISA extensions AVX-512{F, ER, PF}.

Ayal added a reviewer: kbsmith1.Mar 22 2016, 11:06 AM
delena updated this revision to Diff 51519.Mar 24 2016, 1:38 AM
delena removed rL LLVM as the repository for this revision.
delena marked 4 inline comments as done.
delena added a subscriber: llvm-commits.

I applied Ayal's comments and rebased changes to the current trunk

delena added a comment.Mar 28 2016, 12:49 AM

Please complete this review ..

kbsmith1 accepted this revision.Mar 28 2016, 2:11 PM
kbsmith1 edited edge metadata.

LGTM

This revision is now accepted and ready to land.Mar 28 2016, 2:11 PM
Closed by commit rL264703: Added 2 notes (authored by delena). · Explain WhyMar 29 2016, 12:01 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
docs/
17 lines

Diff 51875

llvm/trunk/docs/ReleaseNotes.rst

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines.. NOTE
subsection about it right here. You can copy the following boilerplate subsection about it right here. You can copy the following boilerplate
and un-indent it (the indentation causes it to be inside this comment). and un-indent it (the indentation causes it to be inside this comment).
Special New Feature Special New Feature
------------------- -------------------
Makes programs 10x faster by doing Special New Thing. Makes programs 10x faster by doing Special New Thing.
Changes to the LLVM IR
----------------------
* New intrinsics ``llvm.masked.load``, ``llvm.masked.store``,
``llvm.masked.gather`` and ``llvm.masked.scatter`` were introduced to the
LLVM IR to allow selective memory access for vector data types.
Changes to the ARM Backend Changes to the ARM Backend
-------------------------- --------------------------
During this release ... During this release ...
Changes to the MIPS Target Changes to the MIPS Target
-------------------------- --------------------------
During this release ... During this release ...
Changes to the PowerPC Target Changes to the PowerPC Target
----------------------------- -----------------------------
During this release ... During this release ...
Changes to the X86 Target Changes to the X86 Target
----------------------------- -------------------------
During this release ... * LLVM now supports the Intel CPU codenamed Skylake Server with AVX-512
extensions using ``-march=skylake-avx512``. The switch enables the
ISA extensions AVX-512{F, CD, VL, BW, DQ}.
* LLVM now supports the Intel CPU codenamed Knights Landing with AVX-512
extensions using ``-march=knl``. The switch enables the ISA extensions
AVX-512{F, CD, ER, PF}.
Changes to the AMDGPU Target Changes to the AMDGPU Target
----------------------------- -----------------------------
* Mesa 11.0.x is no longer supported * Mesa 11.0.x is no longer supported
Changes to the OCaml bindings Changes to the OCaml bindings
Show All 34 Lines