Release notes update

[Ayal]

../docs/ReleaseNotes.rst

121

make sure quotes are around each of the intrinsics separately:
`llvm.masked.load`
and
`llvm.masked.store`

241

• LLVM now supports Intel's CPU codenamed Skylake Server with its AVX-512 extensions using

243

can put F first, then alphabetically, and shorten to:
AVX-512{F, BW, CD, DQ, VL}.

245

LLVM now supports the Intel's CPU codenamed Knights Landing with its AVX-512 extensions using
`-march=knl`. The switch enables the ISA extensions AVX-512{F, ER, PF}.

[delena]

I applied Ayal's comments and rebased changes to the current trunk

[delena]

Please complete this review ..

[kbsmith1]

LGTM

../docs/ReleaseNotes.rst

 
 * MSVC-compatible exception handling has been completely overhauled. New
   instructions have been introduced to facilitate this:
   `New exception handling instructions <ExceptionHandling.html#new-exception-handling-instructions>`_. 
   While we have done our best to test this feature thoroughly, it would
   not be completely surprising if there were a few lingering issues that
   early adopters might bump into.
 
+* New intrinsics ``llvm.masked.load and llvm.masked.store`` were introduced to
+  LLVM IR to allow selective memory access for vector data types.
 
 Changes to the ARM Backends
 ---------------------------
 
 During this release the AArch64 target has:
 
 * Added support for more sanitizers (MSAN, TSAN) and made them compatible with
   all VMA kernel configurations (currently tested on 39 and 42 bits).
* Additional vector APIs for vector comparisons and vector merges have been
   added to altivec.h
 
 * Many bugs have been identified and fixed
 
 
 Changes to the X86 Target
 -----------------------------
 
+* LLVM now supports the Intel CPU named Skylake with AVX-512 extensions through
+  ``-march=skylake-avx512``. The switch enables the following ISA extensions:
+  AVX-512F, AVX512VL, AVX-512CD, AVX-512BW, AVX-512DQ.
+
+* Enabled support of Intel MIC architecture processor Knights Landing (KNL)
+  through ``-march=knl`` with ISA extensions AVX-512F, AVX-512ER, AVX-512PF.
+
 * TLS is enabled for Cygwin as emutls.
 
 * Smaller code for materializing 32-bit 1 and -1 constants at ``-Os``.
 
 * More efficient code for wide integer compares. (E.g. 64-bit compares
   on 32-bit targets.)
 
 * Tail call support for ``thiscall``, ``stdcall``, ``vectorcall``, and