[x86] fix cost model inaccuracy for vector memory ops

[spatel]

Summary

The irony of this patch is that the one CPU that is affected is AMD Jaguar, and Jaguar has a completely double-pumped AVX implementation. But getting the cost model to reflect that is a much bigger problem. The small goal here is simply to improve on the lie that !AVX2 == SandyBridge.

[zansari]

lgtm for being an improvement over the existing code.

[DavidKreitzer]

This seems reasonable to me also. It might be nice to have a separate X86Subtarget property for double pumped 32-byte load/stores, but that may be overkill for this one use.

[spatel]

In D18000#371254, @DavidKreitzer wrote:

This seems reasonable to me also. It might be nice to have a separate X86Subtarget property for double pumped 32-byte load/stores, but that may be overkill for this one use.

Thanks, Zia and Dave. I agree a separate property would be good if we really want to model this better. For reference, I noticed this bug as part of the TTI cost model discussion in PR26837:
https://llvm.org/bugs/show_bug.cgi?id=26837

There's a lot of bigger stuff that could be modeled better. :)
Ideally, I think we would lift latency/throughput data from the SchedMachineModel, but I'm not sure how to do that yet.

lib/Target/X86/X86TargetTransformInfo.cpp

int X86TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
   // Legalize the type.
   std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
   assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
          "Invalid Opcode");
 
   // Each load/store unit costs 1.
   int Cost = LT.first * 1;
 
-  // On Sandybridge 256bit load/stores are double pumped
-  // (but not on Haswell).
-  if (LT.second.getSizeInBits() > 128 && !ST->hasAVX2())
-    Cost*=2;
+  // This isn't exactly right. We're using slow unaligned 32-byte accesses as a
+  // proxy for a double-pumped AVX memory interface such as on Sandybridge.
+  if (LT.second.getStoreSize() == 32 && ST->isUnalignedMem32Slow())
+    Cost *= 2;
 
   return Cost;
 }
 
 int X86TTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy,
                                       unsigned Alignment,
                                       unsigned AddressSpace) {
   VectorType *SrcVTy = dyn_cast<VectorType>(SrcTy);

test/Transforms/LoopVectorize/X86/avx1.ll

.lr.ph:                                           ; preds = %0, %.lr.ph
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
   %exitcond = icmp eq i32 %lftr.wideiv, %n
   br i1 %exitcond, label %._crit_edge, label %.lr.ph
 
 ._crit_edge:                                      ; preds = %.lr.ph, %0
   ret i32 undef
 }
 
-;;; FIXME: If 32-byte accesses are fast, this should use a <4 x i64> load.
 
 ; CHECK-LABEL: @read_mod_i64(
-; CHECK: load <2 x i64>
+; SLOWMEM32: load <2 x i64>
+; FASTMEM32: load <4 x i64>
 ; CHECK: ret i32
 define i32 @read_mod_i64(i64* nocapture %a, i32 %n) nounwind uwtable ssp {
   %1 = icmp sgt i32 %n, 0
   br i1 %1, label %.lr.ph, label %._crit_edge
 
 .lr.ph:                                           ; preds = %0, %.lr.ph
   %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %0 ]
   %2 = getelementptr inbounds i64, i64* %a, i64 %indvars.iv