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Fix for PR 26617 (disable scalar-to-vector conversions using direct moves for 32-bit targets)
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Authored by nemanjai on Feb 29 2016, 4:15 AM.

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Summary

When I implemented these conversions, I didn't consider what the results would be if someone attempted to build 32-bit applications on targets that have direct moves. This just disables the problematic conversions when 32-bit registers are used.

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rL LLVM

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nemanjai updated this revision to Diff 49357.Feb 29 2016, 4:15 AM
nemanjai retitled this revision from to Fix for PR 26617 (disable scalar-to-vector conversions using direct moves for 32-bit targets).
nemanjai updated this object.
nemanjai added reviewers: hfinkel, kbarton, wschmidt.
nemanjai set the repository for this revision to rL LLVM.
nemanjai added a subscriber: llvm-commits.
nemanjai updated this revision to Diff 49529.Mar 1 2016, 11:52 AM

Added the test case that I forgot to svn add.

kbarton added inline comments.Mar 1 2016, 1:42 PM
lib/Target/PowerPC/PPCISelLowering.cpp
560

The definition of use64BitRegs is confusing to me.
Could you use Subtarget.isPPC64() instead? We basically only want to do this when we are in 64-bit mode, as I understand it.

nemanjai added inline comments.Mar 2 2016, 2:58 AM
lib/Target/PowerPC/PPCISelLowering.cpp
560

I only used this because it most closely encapsulates the conditions under which we aren't able to perform these actions. However, I think the simplest thing would indeed be to use Subtarget.isPPC64() (or even the local isPPC64) instead. I'll change it and test it prior to committing.

I'll change it to:

if (Subtarget.hasDirectMove() && isPPC64)
kbarton accepted this revision.Mar 7 2016, 8:57 PM
kbarton edited edge metadata.

LGTM

This revision is now accepted and ready to land.Mar 7 2016, 8:57 PM
nemanjai closed this revision.Mar 24 2016, 6:46 AM

Committed revision 264282.