[X86] AMD Bobcat CPU (btver1) doesn't support XSAVE

[RKSimon]

Summary

btver1 is a SSSE3/SSE4a only CPU - it doesn't have AVX and doesn't support XSAVE.

This looks like some kind of copy+paste error from bdver1.

LLVM companion to D17682.

[craig.topper]

LGTM. I seem to be the one that added it in the first place, but I was just bulk adding to many processors and I guess got carried away.

[craig.topper]

Though gcc does also believe the btver1 has xsave...

[RKSimon]

In D17683#363683, @craig.topper wrote:

Though gcc does also believe the btver1 has xsave...

I've gone through the 14h BKDG and can't find any reference to XSAVE/XSAVEOPT at all. I'll try to dig up a bobcat laptop from somewhere to confirm but I think this is correct.

The only reason I noticed this is that clang (correctly I believe) auto-enables AVX for XSAVE capable targets meaning we generate VEX-encoded instructions for btver1!

http://support.amd.com/TechDocs/43170_14h_Mod_00h-0Fh_BKDG.pdf

[craig.topper]

Apparently I'm the one who made clang do that and I don't know why. gcc doesn't do that as far as I can tell. I'm going to remove that.

[RKSimon]

Craig - thanks for the XSAVE/AVX fix.

I've got a /proc/cpuinfo dump now for a typical bobcat cpu (first core below) - XSAVE is not present.

Am I OK to commit this and D17682 ?

processor : 0
vendor_id : AuthenticAMD
cpu family : 20
model : 1
model name : AMD E-350 Processor
stepping : 0
microcode : 0x5000028
cpu MHz : 800.000
cache size : 512 KB
physical id : 0
siblings : 2
core id : 0
cpu cores : 2
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 6
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc extd_apicid aperfmperf pni monitor ssse3 cx16 popcnt lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch ibs skinit wdt arat hw_pstate npt lbrv svm_lock nrip_save pausefilter
bogomips : 3192.21
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management: ts ttp tm stc 100mhzsteps hwpstate

[RKSimon]

In D17683#365157, @RKSimon wrote:

I've got a /proc/cpuinfo dump now for a typical bobcat cpu (first core below) - XSAVE is not present.

Am I OK to commit this and D17682 ?

Craig - just wanted to double check you're happy with both these patches before committing? Cheers, Simon.

[craig.topper]

I'm happy.

llvm/trunk/lib/Target/X86/X86.td

def : Proc<"btver1", [
   FeatureMMX,
   FeatureSSSE3,
   FeatureSSE4A,
   FeatureFXSR,
   FeatureCMPXCHG16B,
   FeaturePRFCHW,
   FeatureLZCNT,
   FeaturePOPCNT,
-  FeatureXSAVE,
   FeatureSlowSHLD,
   FeatureLAHFSAHF
 ]>;
 
 // Jaguar
 def : ProcessorModel<"btver2", BtVer2Model, [
   FeatureMMX,
   FeatureAVX,