[AMDGPU] Fix SMEM instructions encoding/operand namings

[vpykhtin]

Summary

rename sdata, dst -> sdst

SMEMe, SMEMe_vi encodings were split to SMEM_IMMe/SMEM_SOFFe and SMEM_IMMe_vi/SMEM_SOFFe_vi so that they have appropriate encoding field namings - "offset" for immediate and "soff" for SGPR. Having one encoding would require the same name "offset" for immediate and SGPR case, but we want to have it distinct.

S_MEMTIME instruction was fixed as it actually has sdst.

[vpykhtin]

unfortunatelly testing failed as correct names produced more dissassembler operand decoders which are not in the trunk yet. Have to wait on my disassembler changes to be submitted.

[arsenm]

lib/Target/AMDGPU/SIInstrInfo.cpp

278 ↗

(On Diff #49212)

This should be its own patch and have a testcase

[arsenm]

lib/Target/AMDGPU/SIInstrInfo.cpp

278 ↗

(On Diff #49212)

Actually why is this happening? soffset should be a separate operand

[vpykhtin]

My previous fix was incorrect, now encodings splitted, tests added.

[vpykhtin]

lib/Target/AMDGPU/SIInstrInfo.cpp

278 ↗

(On Diff #49212)

Fixed.

[vpykhtin]

ping.

[arsenm]

LGTM

lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

 DECODE_OPERAND(VGPR_32)
 DECODE_OPERAND(VS_32)
 DECODE_OPERAND(VS_64)
 
 DECODE_OPERAND(VReg_64)
 DECODE_OPERAND(VReg_96)
 DECODE_OPERAND(VReg_128)
 
+DECODE_OPERAND(SGPR_32)
 DECODE_OPERAND(SReg_32)
 DECODE_OPERAND(SReg_64)
 DECODE_OPERAND(SReg_128)
 DECODE_OPERAND(SReg_256)
+DECODE_OPERAND(SReg_512)
 
 #define GET_SUBTARGETINFO_ENUM
 #include "AMDGPUGenSubtargetInfo.inc"
 #undef GET_SUBTARGETINFO_ENUM
 
 #include "AMDGPUGenDisassemblerTables.inc"
 
 //===----------------------------------------------------------------------===//

lib/Target/AMDGPU/SIInstrFormats.td

class SOPPe <bits<7> op> : Enc32 {
   let Inst{15-0} = simm16;
   let Inst{22-16} = op;
   let Inst{31-23} = 0x17f; // encoding
 }
 
 class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
   bits<7> sdst;
   bits<7> sbase;
-  bits<8> offset;
 
-  let Inst{7-0} = offset;
   let Inst{8} = imm;
   let Inst{14-9} = sbase{6-1};
   let Inst{21-15} = sdst;
   let Inst{26-22} = op;
   let Inst{31-27} = 0x18; //encoding
 }
 
+class SMRD_IMMe <bits<5> op> : SMRDe<op, 1> {
+  bits<8> offset;
+  let Inst{7-0} = offset;
+}
+
+class SMRD_SOFFe <bits<5> op> : SMRDe<op, 0> {
+  bits<8> soff;
+  let Inst{7-0} = soff;
+}
+
+
+
 class SMRD_IMMe_ci <bits<5> op> : Enc64 {
   bits<7> sdst;
   bits<7> sbase;
   bits<32> offset;
 
   let Inst{7-0}   = 0xff;
   let Inst{8}     = 0;
   let Inst{14-9}  = sbase{6-1};

lib/Target/AMDGPU/SIInstrInfo.td

 
 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
   SMRD <outs, ins, "", pattern>,
   SIMCInstr<opName, SISubtarget.NONE> {
   let isPseudo = 1;
   let isCodeGenOnly = 1;
 }
 
-class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
+class SMRD_IMM_Real_si <bits<5> op, string opName, dag outs, dag ins,
                         string asm> :
   SMRD <outs, ins, asm, []>,
-  SMRDe <op, imm>,
+  SMRD_IMMe <op>,
   SIMCInstr<opName, SISubtarget.SI> {
   let AssemblerPredicates = [isSICI];
   let DecoderNamespace = "SICI";
   let DisableDecoder = DisableSIDecoder;
 }
 
-class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
+class SMRD_SOFF_Real_si <bits<5> op, string opName, dag outs, dag ins,
+                         string asm> :
+  SMRD <outs, ins, asm, []>,
+  SMRD_SOFFe <op>,
+  SIMCInstr<opName, SISubtarget.SI> {
+  let AssemblerPredicates = [isSICI];
+  let DecoderNamespace = "SICI";
+  let DisableDecoder = DisableSIDecoder;
+}
+
+
+class SMRD_IMM_Real_vi <bits<8> op, string opName, dag outs, dag ins,
+                        string asm, list<dag> pattern = []> :
+  SMRD <outs, ins, asm, pattern>,
+  SMEM_IMMe_vi <op>,
+  SIMCInstr<opName, SISubtarget.VI> {
+  let AssemblerPredicates = [isVI];
+  let DecoderNamespace = "VI";
+  let DisableDecoder = DisableVIDecoder;
+}
+
+class SMRD_SOFF_Real_vi <bits<8> op, string opName, dag outs, dag ins,
                          string asm, list<dag> pattern = []> :
   SMRD <outs, ins, asm, pattern>,
-  SMEMe_vi <op, imm>,
+  SMEM_SOFFe_vi <op>,
   SIMCInstr<opName, SISubtarget.VI> {
   let AssemblerPredicates = [isVI];
   let DecoderNamespace = "VI";
   let DisableDecoder = DisableVIDecoder;
 }
 
-multiclass SMRD_m <smrd op, string opName, bit imm, dag outs, dag ins,
+
+multiclass SMRD_IMM_m <smrd op, string opName, dag outs, dag ins,
+                   string asm, list<dag> pattern> {
+
+  def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
+
+  def _si : SMRD_IMM_Real_si <op.SI, opName, outs, ins, asm>;
+
+  // glc is only applicable to scalar stores, which are not yet
+  // implemented.
+  let glc = 0 in {
+    def _vi : SMRD_IMM_Real_vi <op.VI, opName, outs, ins, asm>;
+  }
+}
+
+multiclass SMRD_SOFF_m <smrd op, string opName, dag outs, dag ins,
                         string asm, list<dag> pattern> {
 
   def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
 
-  def _si : SMRD_Real_si <op.SI, opName, imm, outs, ins, asm>;
+  def _si : SMRD_SOFF_Real_si <op.SI, opName, outs, ins, asm>;
 
   // glc is only applicable to scalar stores, which are not yet
   // implemented.
   let glc = 0 in {
-    def _vi : SMRD_Real_vi <op.VI, opName, imm, outs, ins, asm>;
+    def _vi : SMRD_SOFF_Real_vi <op.VI, opName, outs, ins, asm>;
   }
 }
 
 multiclass SMRD_Special <smrd op, string opName, dag outs,
+                       int sdst_ = ?,
                        string opStr = "",
                        list<dag> pattern = []> {
   let hasSideEffects = 1 in {
     def "" : SMRD_Pseudo <opName, outs, (ins), pattern>;
 
-    let sbase = 0, offset = 0 in {
-      let sdst = 0 in {
-        def _si : SMRD_Real_si <op.SI, opName, 0, outs, (ins), opName#opStr>;
-      }
+    let sbase = 0, soff = 0, sdst = sdst_ in {
+      def _si : SMRD_SOFF_Real_si <op.SI, opName, outs, (ins), opName#opStr>;
 
-      let glc = 0, sdata = 0 in {
-        def _vi : SMRD_Real_vi <op.VI, opName, 0, outs, (ins), opName#opStr>;
+      let glc = 0 in {
+        def _vi : SMRD_SOFF_Real_vi <op.VI, opName, outs, (ins), opName#opStr>;
       }
     }
   }
 }
 
 multiclass SMRD_Inval <smrd op, string opName,
                      SDPatternOperator node> {
   let mayStore = 1 in {
-    defm : SMRD_Special<op, opName, (outs), "", [(node)]>;
+    defm : SMRD_Special<op, opName, (outs), 0, "", [(node)]>;
   }
 }
 
 class SMEM_Inval <bits<8> op, string opName, SDPatternOperator node> :
-  SMRD_Real_vi<op, opName, 0, (outs), (ins), opName, [(node)]> {
+  SMRD_SOFF_Real_vi<op, opName, (outs), (ins), opName, [(node)]> {
   let hasSideEffects = 1;
   let mayStore = 1;
   let sbase = 0;
-  let sdata = 0;
+  let sdst = 0;
   let glc = 0;
-  let offset = 0;
+  let soff = 0;
 }
 
 class SMEM_Ret <bits<8> op, string opName, SDPatternOperator node> :
-  SMRD_Real_vi<op, opName, 0, (outs SReg_64:$dst), (ins),
-  opName#" $dst", [(set i64:$dst, (node))]> {
+  SMRD_SOFF_Real_vi<op, opName, (outs SReg_64:$sdst), (ins),
+  opName#" $sdst", [(set i64:$sdst, (node))]> {
   let hasSideEffects = 1;
   let mayStore = ?;
   let mayLoad = ?;
   let sbase = 0;
-  let sdata = 0;
   let glc = 0;
-  let offset = 0;
+  let soff = 0;
 }
 
 multiclass SMRD_Helper <smrd op, string opName, RegisterClass baseClass,
                         RegisterClass dstClass> {
-  defm _IMM : SMRD_m <
-    op, opName#"_IMM", 1, (outs dstClass:$dst),
+  defm _IMM : SMRD_IMM_m <
+    op, opName#"_IMM", (outs dstClass:$sdst),
     (ins baseClass:$sbase, smrd_offset:$offset),
-    opName#" $dst, $sbase, $offset", []
+    opName#" $sdst, $sbase, $offset", []
   >;
 
   def _IMM_ci : SMRD <
-    (outs dstClass:$dst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
-    opName#" $dst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
+    (outs dstClass:$sdst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
+    opName#" $sdst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
     let AssemblerPredicates = [isCIOnly];
     let DecoderNamespace = "CI";
   }
 
-  defm _SGPR : SMRD_m <
-    op, opName#"_SGPR", 0, (outs dstClass:$dst),
+  defm _SGPR : SMRD_SOFF_m <
+    op, opName#"_SGPR", (outs dstClass:$sdst),
     (ins baseClass:$sbase, SReg_32:$soff),
-    opName#" $dst, $sbase, $soff", []
+    opName#" $sdst, $sbase, $soff", []
   >;
 }
 
 //===----------------------------------------------------------------------===//
 // Vector ALU classes
 //===----------------------------------------------------------------------===//
 
 // This must always be right before the operand being input modified.

lib/Target/AMDGPU/SIInstructions.td

 >;
 
 let mayStore = ? in {
 // FIXME: mayStore = ? is a workaround for tablegen bug for different
 // inferred mayStore flags for the instruction pattern vs. standalone
 // Pat. Each considers the other contradictory.
 
 defm S_MEMTIME : SMRD_Special <smrd<0x1e, 0x24>, "s_memtime",
-  (outs SReg_64:$dst), " $dst", [(set i64:$dst, (int_amdgcn_s_memtime))]
+  (outs SReg_64:$sdst), ?, " $sdst", [(set i64:$sdst, (int_amdgcn_s_memtime))]
 >;
 }
 
 defm S_DCACHE_INV : SMRD_Inval <smrd<0x1f, 0x20>, "s_dcache_inv",
   int_amdgcn_s_dcache_inv>;
 
 //===----------------------------------------------------------------------===//
 // SOP1 Instructions

lib/Target/AMDGPU/VIInstrFormats.td

class MTBUFe_vi <bits<4> op> : Enc64 {
   let Inst{52-48} = srsrc{6-2};
   let Inst{54}    = slc;
   let Inst{55}    = tfe;
   let Inst{63-56} = soffset;
 }
 
 class SMEMe_vi <bits<8> op, bit imm> : Enc64 {
   bits<7>  sbase;
-  bits<7>  sdata;
+  bits<7>  sdst;
   bits<1>  glc;
-  bits<20> offset;
 
   let Inst{5-0}   = sbase{6-1};
-  let Inst{12-6}  = sdata;
+  let Inst{12-6}  = sdst;
   let Inst{16}    = glc;
   let Inst{17}    = imm;
   let Inst{25-18} = op;
   let Inst{31-26} = 0x30; //encoding
+}
+
+class SMEM_IMMe_vi <bits<8> op> : SMEMe_vi<op, 1> {
+  bits<20> offset;
   let Inst{51-32} = offset;
 }
 
+class SMEM_SOFFe_vi <bits<8> op> : SMEMe_vi<op, 0> {
+  bits<20> soff;
+  let Inst{51-32} = soff;
+}
+
 class VOP3a_vi <bits<10> op> : Enc64 {
   bits<2> src0_modifiers;
   bits<9> src0;
   bits<2> src1_modifiers;
   bits<9> src1;
   bits<2> src2_modifiers;
   bits<9> src2;
   bits<1> clamp;

test/MC/AMDGPU/smrd.s

 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SI  %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SI %s
 // RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=CI %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefix=VI %s
 
 // RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSI
 // RUN: not llvm-mc -arch=amdgcn -mcpu=SI  %s 2>&1 | FileCheck %s --check-prefix=NOSI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=fiji  %s 2>&1 | FileCheck %s --check-prefix=NOVI
+
 //===----------------------------------------------------------------------===//
 // Offset Handling
 //===----------------------------------------------------------------------===//
 
 s_load_dword s1, s[2:3], 0xfc
 // GCN: s_load_dword s1, s[2:3], 0xfc ; encoding: [0xfc,0x83,0x00,0xc0]
+// VI:  s_load_dword s1, s[2:3], 0xfc   ; encoding: [0x41,0x00,0x02,0xc0,0xfc,0x00,0x00,0x00]
 
 s_load_dword s1, s[2:3], 0xff
 // GCN: s_load_dword s1, s[2:3], 0xff ; encoding: [0xff,0x83,0x00,0xc0]
+// VI:  s_load_dword s1, s[2:3], 0xff   ; encoding: [0x41,0x00,0x02,0xc0,0xff,0x00,0x00,0x00]
 
 s_load_dword s1, s[2:3], 0x100
 // NOSI: error: instruction not supported on this GPU
+// NOVI: error: instruction not supported on this GPU
 // CI: s_load_dword s1, s[2:3], 0x100 ; encoding: [0xff,0x82,0x00,0xc0,0x00,0x01,0x00,0x00]
 
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
 s_load_dword s1, s[2:3], 1
 // GCN: s_load_dword s1, s[2:3], 0x1 ; encoding: [0x01,0x83,0x00,0xc0]
+// VI:  s_load_dword s1, s[2:3], 0x1    ; encoding: [0x41,0x00,0x02,0xc0,0x01,0x00,0x00,0x00]
 
 s_load_dword s1, s[2:3], s4
 // GCN: s_load_dword s1, s[2:3], s4 ; encoding: [0x04,0x82,0x00,0xc0]
+// VI:  s_load_dword s1, s[2:3], s4     ; encoding: [0x41,0x00,0x00,0xc0,0x04,0x00,0x00,0x00]
 
 s_load_dwordx2 s[2:3], s[2:3], 1
 // GCN: s_load_dwordx2 s[2:3], s[2:3], 0x1 ; encoding: [0x01,0x03,0x41,0xc0]
+// VI:  s_load_dwordx2 s[2:3], s[2:3], 0x1 ; encoding: [0x81,0x00,0x06,0xc0,0x01,0x00,0x00,0x00]
 
 s_load_dwordx2 s[2:3], s[2:3], s4
 // GCN: s_load_dwordx2 s[2:3], s[2:3], s4 ; encoding: [0x04,0x02,0x41,0xc0]
+// VI:  s_load_dwordx2 s[2:3], s[2:3], s4 ; encoding: [0x81,0x00,0x04,0xc0,0x04,0x00,0x00,0x00]
 
 s_load_dwordx4 s[4:7], s[2:3], 1
 // GCN: s_load_dwordx4 s[4:7], s[2:3], 0x1 ; encoding: [0x01,0x03,0x82,0xc0]
+// VI:  s_load_dwordx4 s[4:7], s[2:3], 0x1 ; encoding: [0x01,0x01,0x0a,0xc0,0x01,0x00,0x00,0x00]
 
 s_load_dwordx4 s[4:7], s[2:3], s4
 // GCN: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x04,0x02,0x82,0xc0]
+// VI:  s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x01,0x01,0x08,0xc0,0x04,0x00,0x00,0x00]
 
 s_load_dwordx4 s[100:103], s[2:3], s4
 // GCN: s_load_dwordx4 s[100:103], s[2:3], s4 ; encoding: [0x04,0x02,0xb2,0xc0]
+// NOVI: error: invalid operand for instruction
 
 s_load_dwordx8 s[8:15], s[2:3], 1
 // GCN: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x03,0xc4,0xc0]
+// VI:  s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x02,0x0e,0xc0,0x01,0x00,0x00,0x00]
 
 s_load_dwordx8 s[8:15], s[2:3], s4
 // GCN: s_load_dwordx8 s[8:15], s[2:3], s4 ; encoding: [0x04,0x02,0xc4,0xc0]
+// VI:  s_load_dwordx8 s[8:15], s[2:3], s4 ; encoding: [0x01,0x02,0x0c,0xc0,0x04,0x00,0x00,0x00]
 
 s_load_dwordx8 s[96:103], s[2:3], s4
 // GCN: s_load_dwordx8 s[96:103], s[2:3], s4 ; encoding: [0x04,0x02,0xf0,0xc0]
+// NOVI: error: invalid operand for instruction
 
 s_load_dwordx16 s[16:31], s[2:3], 1
 // GCN: s_load_dwordx16 s[16:31], s[2:3], 0x1 ; encoding: [0x01,0x03,0x08,0xc1]
+// VI:  s_load_dwordx16 s[16:31], s[2:3], 0x1 ; encoding: [0x01,0x04,0x12,0xc0,0x01,0x00,0x00,0x00]
 
 s_load_dwordx16 s[16:31], s[2:3], s4
 // GCN: s_load_dwordx16 s[16:31], s[2:3], s4 ; encoding: [0x04,0x02,0x08,0xc1]
+// VI:  s_load_dwordx16 s[16:31], s[2:3], s4 ; encoding: [0x01,0x04,0x10,0xc0,0x04,0x00,0x00,0x00]
 
 s_load_dwordx16 s[88:103], s[2:3], s4
 // GCN: s_load_dwordx16 s[88:103], s[2:3], s4 ; encoding: [0x04,0x02,0x2c,0xc1]
+// NOVI: error: invalid operand for instruction
 
 s_dcache_inv
 // GCN: s_dcache_inv ; encoding: [0x00,0x00,0xc0,0xc7]
+// VI:  s_dcache_inv                    ; encoding: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00]
 
 s_dcache_inv_vol
 // CI: s_dcache_inv_vol ; encoding: [0x00,0x00,0x40,0xc7]
 // NOSI: error: instruction not supported on this GPU
+// VI: s_dcache_inv_vol                ; encoding: [0x00,0x00,0x88,0xc0,0x00,0x00,0x00,0x00]
 
 s_memtime s[0:1]
 // GCN: s_memtime s[0:1] ; encoding: [0x00,0x00,0x80,0xc7]
+// VI:  s_memtime s[0:1]                ; encoding: [0x00,0x00,0x90,0xc0,0x00,0x00,0x00,0x00]

test/MC/Disassembler/AMDGPU/smrd_vi.txt

+# RUN: llvm-mc -arch=amdgcn -mcpu=fiji -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
+
+# VI: s_load_dword s1, s[2:3], 0x1    ; encoding: [0x41,0x00,0x02,0xc0,0x01,0x00,0x00,0x00]
+0x41 0x00 0x02 0xc0 0x01 0x00 0x00 0x00
+
+# VI: s_load_dword s1, s[2:3], s4     ; encoding: [0x41,0x00,0x00,0xc0,0x04,0x00,0x00,0x00]
+0x41 0x00 0x00 0xc0 0x04 0x00 0x00 0x00
+
+# VI: s_load_dwordx2 s[2:3], s[2:3], 0x1 ; encoding: [0x81,0x00,0x06,0xc0,0x01,0x00,0x00,0x00]
+0x81 0x00 0x06 0xc0 0x01 0x00 0x00 0x00
+
+# VI: s_load_dwordx2 s[2:3], s[2:3], s4 ; encoding: [0x81,0x00,0x04,0xc0,0x04,0x00,0x00,0x00]
+0x81 0x00 0x04 0xc0 0x04 0x00 0x00 0x00
+
+# VI: s_load_dwordx4 s[4:7], s[2:3], 0x1 ; encoding: [0x01,0x01,0x0a,0xc0,0x01,0x00,0x00,0x00]
+0x01 0x01 0x0a 0xc0 0x01 0x00 0x00 0x00
+
+# VI: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x01,0x01,0x08,0xc0,0x04,0x00,0x00,0x00]
+0x01 0x01 0x08 0xc0 0x04 0x00 0x00 0x00
+
+# VI: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x02,0x0e,0xc0,0x01,0x00,0x00,0x00]
+0x01 0x02 0x0e 0xc0 0x01 0x00 0x00 0x00
+
+# VI: s_load_dwordx8 s[8:15], s[2:3], s4 ; encoding: [0x01,0x02,0x0c,0xc0,0x04,0x00,0x00,0x00]
+0x01 0x02 0x0c 0xc0 0x04 0x00 0x00 0x00
+
+# VI: s_load_dwordx16 s[16:31], s[2:3], 0x1 ; encoding: [0x01,0x04,0x12,0xc0,0x01,0x00,0x00,0x00]
+0x01 0x04 0x12 0xc0 0x01 0x00 0x00 0x00
+
+# VI: s_load_dwordx16 s[16:31], s[2:3], s4 ; encoding: [0x01,0x04,0x10,0xc0,0x04,0x00,0x00,0x00]
+0x01 0x04 0x10 0xc0 0x04 0x00 0x00 0x00
+
+# VI: s_dcache_inv                    ; encoding: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00]
+0x00 0x00 0x80 0xc0 0x00 0x00 0x00 0x00
+
+# VI: s_dcache_inv_vol                ; encoding: [0x00,0x00,0x88,0xc0,0x00,0x00,0x00,0x00]
+0x00 0x00 0x88 0xc0 0x00 0x00 0x00 0x00
+
+# VI: s_memtime s[0:1]                ; encoding: [0x00,0x00,0x90,0xc0,0x00,0x00,0x00,0x00]
+0x00 0x00 0x90 0xc0 0x00 0x00 0x00 0x00