[AMDGPU] Fix SMEM instructions encoding/operand namings

[vpykhtin]

Summary

rename sdata, dst -> sdst

SMEMe, SMEMe_vi encodings were split to SMEM_IMMe/SMEM_SOFFe and SMEM_IMMe_vi/SMEM_SOFFe_vi so that they have appropriate encoding field namings - "offset" for immediate and "soff" for SGPR. Having one encoding would require the same name "offset" for immediate and SGPR case, but we want to have it distinct.

S_MEMTIME instruction was fixed as it actually has sdst.

[vpykhtin]

unfortunatelly testing failed as correct names produced more dissassembler operand decoders which are not in the trunk yet. Have to wait on my disassembler changes to be submitted.

[arsenm]

lib/Target/AMDGPU/SIInstrInfo.cpp

278

This should be its own patch and have a testcase

[arsenm]

lib/Target/AMDGPU/SIInstrInfo.cpp

278

Actually why is this happening? soffset should be a separate operand

[vpykhtin]

My previous fix was incorrect, now encodings splitted, tests added.

[vpykhtin]

lib/Target/AMDGPU/SIInstrInfo.cpp

278

Fixed.

[vpykhtin]

ping.

[arsenm]

LGTM

lib/Target/AMDGPU/SIInstrInfo.cpp

if (isMUBUF(*LdSt) || isMTBUF(*LdSt)) {
     BaseReg = AddrReg->getReg();
     Offset = OffsetImm->getImm();
     return true;
   }
 
   if (isSMRD(*LdSt)) {
     const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
                                                       AMDGPU::OpName::offset);
-    if (!OffsetImm)
+    if (!OffsetImm || !OffsetImm->isImm()) // there might be SReg offset
       return false;
 
     const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
                                                      AMDGPU::OpName::sbase);
     BaseReg = SBaseReg->getReg();
     Offset = OffsetImm->getImm();
     return true;
   }

lib/Target/AMDGPU/SIInstrInfo.td

multiclass SMRD_Inval <smrd op, string opName,
   let hasSideEffects = 1, mayStore = 1 in {
     def "" : SMRD_Pseudo <opName, (outs), (ins), [(node)]>;
 
     let sbase = 0, offset = 0 in {
       let sdst = 0 in {
         def _si : SMRD_Real_si <op.SI, opName, 0, (outs), (ins), opName>;
       }
 
-      let glc = 0, sdata = 0 in {
+      let glc = 0, sdst = 0 in {
         def _vi : SMRD_Real_vi <op.VI, opName, 0, (outs), (ins), opName>;
       }
     }
   }
 }
 
 class SMEM_Inval <bits<8> op, string opName, SDPatternOperator node> :
   SMRD_Real_vi<op, opName, 0, (outs), (ins), opName, [(node)]> {
   let hasSideEffects = 1;
   let mayStore = 1;
   let sbase = 0;
-  let sdata = 0;
+  let sdst = 0;
   let glc = 0;
   let offset = 0;
 }
 
 multiclass SMRD_Helper <smrd op, string opName, RegisterClass baseClass,
                         RegisterClass dstClass> {
   defm _IMM : SMRD_m <
-    op, opName#"_IMM", 1, (outs dstClass:$dst),
+    op, opName#"_IMM", 1, (outs dstClass:$sdst),
     (ins baseClass:$sbase, smrd_offset:$offset),
-    opName#" $dst, $sbase, $offset", []
+    opName#" $sdst, $sbase, $offset", []
   >;
 
   def _IMM_ci : SMRD <
-    (outs dstClass:$dst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
-    opName#" $dst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
+    (outs dstClass:$sdst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
+    opName#" $sdst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
     let AssemblerPredicates = [isCIOnly];
     let DecoderNamespace = "CI";
   }
 
   defm _SGPR : SMRD_m <
-    op, opName#"_SGPR", 0, (outs dstClass:$dst),
-    (ins baseClass:$sbase, SReg_32:$soff),
-    opName#" $dst, $sbase, $soff", []
+    op, opName#"_SGPR", 0, (outs dstClass:$sdst),
+    (ins baseClass:$sbase, SReg_32:$offset),
+    opName#" $sdst, $sbase, $offset", [] 
   >;
 }
 
 //===----------------------------------------------------------------------===//
 // Vector ALU classes
 //===----------------------------------------------------------------------===//
 
 // This must always be right before the operand being input modified.

lib/Target/AMDGPU/VIInstrFormats.td

class MTBUFe_vi <bits<4> op> : Enc64 {
   let Inst{52-48} = srsrc{6-2};
   let Inst{54}    = slc;
   let Inst{55}    = tfe;
   let Inst{63-56} = soffset;
 }
 
 class SMEMe_vi <bits<8> op, bit imm> : Enc64 {
   bits<7>  sbase;
-  bits<7>  sdata;
+  bits<7>  sdst;
   bits<1>  glc;
   bits<20> offset;
 
   let Inst{5-0}   = sbase{6-1};
-  let Inst{12-6}  = sdata;
+  let Inst{12-6}  = sdst;
   let Inst{16}    = glc;
   let Inst{17}    = imm;
   let Inst{25-18} = op;
   let Inst{31-26} = 0x30; //encoding
   let Inst{51-32} = offset;
 }
 
 class VOP3a_vi <bits<10> op> : Enc64 {