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Differential D17540

[MIPS][LLVM-MC] Fix Disassemble of Negative Offset
ClosedPublic

Authored by nitesh.jain on Feb 23 2016, 2:49 AM.

Details

Reviewers
dsanders
vkalintiris
Commits
rGc222e5d3b43a: Merging r270542: --------------------------------------------------------------…
rG672c710de4aa: [MIPS][LLVM-MC] Fix Disassemble of Negative Offset
rL270542: [MIPS][LLVM-MC] Fix Disassemble of Negative Offset
Summary

The type of Imm in MipsDisassembler.cpp was incorrect since SignExtend64 return int64_t type.As per the MIPSr6 doc ,the offset is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address hence “4” is added to the offset. The offset of some test case are update to reflect the changes due to “ + 4 ” offset and new test case for negative offset are added.

Diff Detail

Repository
rL LLVM

Event Timeline

nitesh.jain updated this revision to Diff 48800.Feb 23 2016, 2:49 AM
nitesh.jain retitled this revision from to [MIPS][LLVM-MC] Fix Disassemble of Negative Offset .
nitesh.jain updated this object.
nitesh.jain added a reviewer: dsanders.
nitesh.jain set the repository for this revision to rL LLVM.
nitesh.jain added subscribers: jaydeep, bhushan, slthakur and 2 others.
Herald added a reviewer: vkalintiris. · View Herald TranscriptFeb 23 2016, 2:49 AM
Herald added a subscriber: dsanders. · View Herald Transcript
vkalintiris requested changes to this revision.Feb 29 2016, 9:10 AM
vkalintiris edited edge metadata.

Can you update the following tests too?

LLVM :: ExecutionEngine/RuntimeDyld/Mips/ELF_N64R6_relocations.s
LLVM :: ExecutionEngine/RuntimeDyld/Mips/ELF_O32R6_relocations.s
LLVM :: MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt (You forgot to update the BALC instruction).

They are failing on my machine with check-all.

This revision now requires changes to proceed.Feb 29 2016, 9:10 AM
nitesh.jain updated this revision to Diff 49609.Mar 2 2016, 5:47 AM
nitesh.jain edited edge metadata.

The tests are updated as per suggestion.

nitesh.jain added a comment.Mar 11 2016, 1:22 AM

Hi Vasileios,

Could you please find some time to review this ?

Thanks

dsanders edited edge metadata.Mar 11 2016, 6:30 AM

Can you check whether the assemble/disassemble/assemble or disassemble/assemble/disassemble round-trip works for the affected instructions?
Assuming it does: LGTM with the FIXME's removed.

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
36

Are these FIXME's still true? If you assemble the mnemonics from the disassembler do you get the same opcodes?
I suspect this change may have fixed the ones next to the tests you've updated.

nitesh.jain added inline comments.Mar 15 2016, 11:17 PM
test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
36

The encoding and decoding are not inverse of each other. Since while decoding the offset is left shifted by 2 and then 4 is added but in case of encoding it will just right shift by 2. Thus for example

encoding 0x18 0x42 0x01 0x4d -->disassemble -->bgezalc $2, 1336
bgezalc $2, 1336-->assemble-->0x18 0x42 0x01 0x4e
0x18 0x42 0x01 0x4e-->disassemble-->bgezalc $2, 1340.

So these FIXME's will always be true

nitesh.jain added a comment.Mar 23 2016, 3:11 AM

Hi,
Could you please find some time to review this ?

Thanks

dsanders added inline comments.Mar 23 2016, 3:27 AM
test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
36

That's definitely a bug, they should be inverses of each other.

I've just looked at the encode function and I think it's wrong for the path this test will use. The immediate path is just 'X >> 2' but the symbol reference path is '(X - 4) >> 2'. Would you be willing to fix the immediate-encode path as part of this patch? That way we can drop these FIXME's.

dsanders accepted this revision.Mar 23 2016, 4:45 AM
dsanders edited edge metadata.
dsanders added inline comments.
test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
36

It appears I'm mistaken on this but we think the current behaviour is weird/wrong in both GAS and IAS. In GAS, immediates are absolute addresses that are modified with +4 for unknown reasons. In IAS, immediates are currently offsets and are not modified.

Your change matches GAS's behaviour so: LGTM with the 'FIXME: ' comments changed to '# The encode/decode functions are not inverses of each other in the immediate case'

nitesh.jain updated this revision to Diff 51414.Mar 23 2016, 7:15 AM
nitesh.jain edited edge metadata.

Update the diff as per suggestion

nitesh.jain added a comment.Mar 29 2016, 2:18 AM
This comment was removed by nitesh.jain.
nitesh.jain added a comment.Mar 29 2016, 2:46 AM

Hi Vasileios,

Could you please find some time to review this ?

Thanks

nitesh.jain added a comment.Apr 5 2016, 5:55 AM

Hi Vasileios,

Could you please find some time to review this ?

Thanks

vkalintiris accepted this revision.Apr 20 2016, 2:23 AM
vkalintiris edited edge metadata.

Hi Nitesh, you can go ahead and commit this. But you should change the comments from:

# The encode/decode functions are not inverses of each other.

to:

# The encode/decode functions are not inverses of each other in the immediate case

first, ie. you missed the in the immediate case bit :)

This revision is now accepted and ready to land.Apr 20 2016, 2:23 AM
Closed by commit rL270542: [MIPS][LLVM-MC] Fix Disassemble of Negative Offset (authored by slthakur). · Explain WhyMay 24 2016, 3:03 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
Disassembler/
16 lines
test/
MC/
Disassembler/
Mips/
mips32r6/
65 lines
67 lines
mips64r6/
67 lines
63 lines
20 lines

Diff 48800

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

Show First 20 Lines • Show All 557 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
// We have: // We have:
// 0b001000 sssss ttttt iiiiiiiiiiiiiiii // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
// BOVC if rs >= rt // BOVC if rs >= rt
// BEQZALC if rs == 0 && rt != 0 // BEQZALC if rs == 0 && rt != 0
// BEQC if rs < rt && rs != 0 // BEQC if rs < rt && rs != 0
InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5);
InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
bool HasRs = false; bool HasRs = false;
if (Rs >= Rt) { if (Rs >= Rt) {
MI.setOpcode(Mips::BOVC); MI.setOpcode(Mips::BOVC);
HasRs = true; HasRs = true;
} else if (Rs != 0 && Rs < Rt) { } else if (Rs != 0 && Rs < Rt) {
MI.setOpcode(Mips::BEQC); MI.setOpcode(Mips::BEQC);
HasRs = true; HasRs = true;
Show All 22 Linesstatic DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
// We have: // We have:
// 0b011000 sssss ttttt iiiiiiiiiiiiiiii // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
// BNVC if rs >= rt // BNVC if rs >= rt
// BNEZALC if rs == 0 && rt != 0 // BNEZALC if rs == 0 && rt != 0
// BNEC if rs < rt && rs != 0 // BNEC if rs < rt && rs != 0
InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5);
InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
bool HasRs = false; bool HasRs = false;
if (Rs >= Rt) { if (Rs >= Rt) {
MI.setOpcode(Mips::BNVC); MI.setOpcode(Mips::BNVC);
HasRs = true; HasRs = true;
} else if (Rs != 0 && Rs < Rt) { } else if (Rs != 0 && Rs < Rt) {
MI.setOpcode(Mips::BNEC); MI.setOpcode(Mips::BNEC);
HasRs = true; HasRs = true;
Show All 23 Linesstatic DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
// 0b010110 sssss ttttt iiiiiiiiiiiiiiii // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
// Invalid if rs == 0 // Invalid if rs == 0
// BLEZC if rs == 0 && rt != 0 // BLEZC if rs == 0 && rt != 0
// BGEZC if rs == rt && rt != 0 // BGEZC if rs == rt && rt != 0
// BGEC if rs != rt && rs != 0 && rt != 0 // BGEC if rs != rt && rs != 0 && rt != 0
InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5);
InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
bool HasRs = false; bool HasRs = false;
if (Rt == 0) if (Rt == 0)
return MCDisassembler::Fail; return MCDisassembler::Fail;
else if (Rs == 0) else if (Rs == 0)
MI.setOpcode(Mips::BLEZC); MI.setOpcode(Mips::BLEZC);
else if (Rs == Rt) else if (Rs == Rt)
MI.setOpcode(Mips::BGEZC); MI.setOpcode(Mips::BGEZC);
Show All 28 Linesstatic DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
// BGTZC if rs == 0 && rt != 0 // BGTZC if rs == 0 && rt != 0
// BLTZC if rs == rt && rt != 0 // BLTZC if rs == rt && rt != 0
// BLTC if rs != rt && rs != 0 && rt != 0 // BLTC if rs != rt && rs != 0 && rt != 0
bool HasRs = false; bool HasRs = false;
InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5);
InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
if (Rt == 0) if (Rt == 0)
return MCDisassembler::Fail; return MCDisassembler::Fail;
else if (Rs == 0) else if (Rs == 0)
MI.setOpcode(Mips::BGTZC); MI.setOpcode(Mips::BGTZC);
else if (Rs == Rt) else if (Rs == Rt)
MI.setOpcode(Mips::BLTZC); MI.setOpcode(Mips::BLTZC);
else { else {
Show All 25 Linesstatic DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
// 0b000111 sssss ttttt iiiiiiiiiiiiiiii // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
// BGTZ if rt == 0 // BGTZ if rt == 0
// BGTZALC if rs == 0 && rt != 0 // BGTZALC if rs == 0 && rt != 0
// BLTZALC if rs != 0 && rs == rt // BLTZALC if rs != 0 && rs == rt
// BLTUC if rs != 0 && rs != rt // BLTUC if rs != 0 && rs != rt
InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5);
InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
bool HasRs = false; bool HasRs = false;
bool HasRt = false; bool HasRt = false;
if (Rt == 0) { if (Rt == 0) {
MI.setOpcode(Mips::BGTZ); MI.setOpcode(Mips::BGTZ);
HasRs = true; HasRs = true;
} else if (Rs == 0) { } else if (Rs == 0) {
MI.setOpcode(Mips::BGTZALC); MI.setOpcode(Mips::BGTZALC);
Show All 32 Linesstatic DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
// 0b000110 sssss ttttt iiiiiiiiiiiiiiii // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
// Invalid if rs == 0 // Invalid if rs == 0
// BLEZALC if rs == 0 && rt != 0 // BLEZALC if rs == 0 && rt != 0
// BGEZALC if rs == rt && rt != 0 // BGEZALC if rs == rt && rt != 0
// BGEUC if rs != rt && rs != 0 && rt != 0 // BGEUC if rs != rt && rs != 0 && rt != 0
InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 21, 5);
InsnType Rt = fieldFromInstruction(insn, 16, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5);
InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4;
bool HasRs = false; bool HasRs = false;
if (Rt == 0) if (Rt == 0)
return MCDisassembler::Fail; return MCDisassembler::Fail;
else if (Rs == 0) else if (Rs == 0)
MI.setOpcode(Mips::BLEZALC); MI.setOpcode(Mips::BLEZALC);
else if (Rs == Rt) else if (Rs == Rt)
MI.setOpcode(Mips::BGEZALC); MI.setOpcode(Mips::BGEZALC);
▲ Show 20 Lines • Show All 1,027 Lines • ▼ Show 20 Linesstatic DecodeStatus DecodeJumpTarget(MCInst &Inst,
Inst.addOperand(MCOperand::createImm(JumpOffset)); Inst.addOperand(MCOperand::createImm(JumpOffset));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeBranchTarget21(MCInst &Inst, static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
unsigned Offset, unsigned Offset,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
int32_t BranchOffset = SignExtend32<21>(Offset) * 4; int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4;
Inst.addOperand(MCOperand::createImm(BranchOffset)); Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeBranchTarget26(MCInst &Inst, static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
unsigned Offset, unsigned Offset,
uint64_t Address, uint64_t Address,
const void *Decoder) { const void *Decoder) {
int32_t BranchOffset = SignExtend32<26>(Offset) * 4; int32_t BranchOffset = SignExtend32<26>(Offset) * 4 + 4;
Inst.addOperand(MCOperand::createImm(BranchOffset)); Inst.addOperand(MCOperand::createImm(BranchOffset));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
unsigned Offset, unsigned Offset,
uint64_t Address, uint64_t Address,
▲ Show 20 Lines • Show All 264 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt

# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r6 | FileCheck %s # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r6 | FileCheck %s
0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4 0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4
0x19 0x00 0x80 0xec # CHECK: addiupc $4, 100 0x19 0x00 0x80 0xec # CHECK: addiupc $4, 100
0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10 0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10
0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2 0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2
0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56 0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56
0xe9 0xff 0x62 0x3c # CHECK: aui $3, $2, -23 0xe9 0xff 0x62 0x3c # CHECK: aui $3, $2, -23
0xff 0xff 0x7e 0xec # CHECK: auipc $3, -1 0xff 0xff 0x7e 0xec # CHECK: auipc $3, -1
0x9b 0x14 0x11 0x04 # CHECK: bal 21104 0x9b 0x14 0x11 0x04 # CHECK: bal 21104
0xb8 0x96 0x37 0xe8 # CHECK: balc 14572256 0xb8 0x96 0x37 0xe8 # CHECK: balc 14572260
0xb8 0x96 0x37 0xc8 # CHECK: bc 14572256 0xb8 0x96 0x37 0xc8 # CHECK: bc 14572260
0x01 0x00 0x20 0x45 # CHECK: bc1eqz $f0, 8 0x01 0x00 0x20 0x45 # CHECK: bc1eqz $f0, 8
0x01 0x00 0x3f 0x45 # CHECK: bc1eqz $f31, 8 0x01 0x00 0x3f 0x45 # CHECK: bc1eqz $f31, 8
0x01 0x00 0xa0 0x45 # CHECK: bc1nez $f0, 8 0x01 0x00 0xa0 0x45 # CHECK: bc1nez $f0, 8
0x01 0x00 0xbf 0x45 # CHECK: bc1nez $f31, 8 0x01 0x00 0xbf 0x45 # CHECK: bc1nez $f31, 8
0x02 0x00 0x20 0x49 # CHECK: bc2eqz $0, 12 0x02 0x00 0x20 0x49 # CHECK: bc2eqz $0, 12
0x02 0x00 0x3f 0x49 # CHECK: bc2eqz $31, 12 0x02 0x00 0x3f 0x49 # CHECK: bc2eqz $31, 12
0x02 0x00 0xa0 0x49 # CHECK: bc2nez $0, 12 0x02 0x00 0xa0 0x49 # CHECK: bc2nez $0, 12
0x02 0x00 0xbf 0x49 # CHECK: bc2nez $31, 12 0x02 0x00 0xbf 0x49 # CHECK: bc2nez $31, 12
0x40 0x00 0xa6 0x20 # CHECK: beqc $5, $6, 256 0x40 0x00 0xa6 0x20 # CHECK: beqc $5, $6, 260
0x4d 0x01 0x02 0x20 # CHECK: beqzalc $2, 1332 0x4d 0x01 0x02 0x20 # CHECK: beqzalc $2, 1336
0x40 0x00 0xa6 0x60 # CHECK: bnec $5, $6, 256 0x40 0x00 0xa6 0x60 # CHECK: bnec $5, $6, 260
0x4d 0x01 0x02 0x60 # CHECK: bnezalc $2, 1332 0xfa 0xff 0x43 0x60 # CHECK: bnec $2, $3, -20
0x90 0x46 0xa0 0xd8 # CHECK: beqzc $5, 72256 0x4d 0x01 0x02 0x60 # CHECK: bnezalc $2, 1336
0x40 0x00 0x43 0x58 # CHECK: bgec $2, $3, 256 0x90 0x46 0xa0 0xd8 # CHECK: beqzc $5, 72260
0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 256 0x40 0x00 0x43 0x58 # CHECK: bgec $2, $3, 260
0x4d 0x01 0x42 0x18 # CHECK: bgezalc $2, 1332 0xfa 0xff 0x43 0x58 # CHECK: bgec $2, $3, -20
0x90 0x46 0xa0 0xf8 # CHECK: bnezc $5, 72256 0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 260
0x40 0x00 0xa5 0x5c # CHECK: bltzc $5, 256 0xfa 0xff 0x43 0x18 # CHECK: bgeuc $2, $3, -20
0x40 0x00 0xa5 0x58 # CHECK: bgezc $5, 256 0x4d 0x01 0x42 0x18 # CHECK: bgezalc $2, 1336
0x4d 0x01 0x02 0x1c # CHECK: bgtzalc $2, 1332 0xfa 0xff 0x42 0x18 # CHECK: bgezalc $2, -20
0x40 0x00 0x05 0x58 # CHECK: blezc $5, 256 0x90 0x46 0xa0 0xf8 # CHECK: bnezc $5, 72260
0x4d 0x01 0x42 0x1c # CHECK: bltzalc $2, 1332 0x40 0x00 0xa5 0x5c # CHECK: bltzc $5, 260
0x40 0x00 0x05 0x5c # CHECK: bgtzc $5, 256 0xfa 0xff 0xa5 0x5c # CHECK: bltzc $5, -20
0x40 0x00 0xa5 0x58 # CHECK: bgezc $5, 260
0xfa 0xff 0xa5 0x58 # CHECK: bgezc $5, -20
0x4d 0x01 0x02 0x1c # CHECK: bgtzalc $2, 1336
0xfa 0xff 0x02 0x1c # CHECK: bgtzalc $2, -20
0x40 0x00 0x05 0x58 # CHECK: blezc $5, 260
0xfa 0xff 0x05 0x58 # CHECK: blezc $5, -20
0x4d 0x01 0x42 0x1c # CHECK: bltzalc $2, 1336
0xfa 0xff 0x42 0x1c # CHECK: bltzalc $2, -20
0x40 0x00 0x05 0x5c # CHECK: bgtzc $5, 260
0xfa 0xff 0x05 0x5c # CHECK: bgtzc $5, -20
0x20 0x20 0x02 0x7c # CHECK: bitswap $4, $2 0x20 0x20 0x02 0x7c # CHECK: bitswap $4, $2
0x4d 0x01 0x02 0x18 # CHECK: blezalc $2, 1332 0x4d 0x01 0x02 0x18 # CHECK: blezalc $2, 1336
0x40 0x00 0xa6 0x5c # CHECK: bltc $5, $6, 256 0xfa 0xff 0x02 0x18 # CHECK: blezalc $2, -20
0x40 0x00 0xa6 0x1c # CHECK: bltuc $5, $6, 256 0x40 0x00 0xa6 0x5c # CHECK: bltc $5, $6, 260
0x01 0x00 0x00 0x60 # CHECK: bnvc $zero, $zero, 4 0xfa 0xff 0xa6 0x5c # CHECK: bltc $5, $6, -20
0x01 0x00 0x40 0x60 # CHECK: bnvc $2, $zero, 4 0x40 0x00 0xa6 0x1c # CHECK: bltuc $5, $6, 260
0x01 0x00 0x82 0x60 # CHECK: bnvc $4, $2, 4 0xfa 0xff 0xa6 0x1c # CHECK: bltuc $5, $6, -20
0x01 0x00 0x00 0x20 # CHECK: bovc $zero, $zero, 4 0x01 0x00 0x00 0x60 # CHECK: bnvc $zero, $zero, 8
0x01 0x00 0x40 0x20 # CHECK: bovc $2, $zero, 4 0x01 0x00 0x40 0x60 # CHECK: bnvc $2, $zero, 8
0x01 0x00 0x82 0x20 # CHECK: bovc $4, $2, 4 0x01 0x00 0x82 0x60 # CHECK: bnvc $4, $2, 8
0x01 0x00 0x00 0x20 # CHECK: bovc $zero, $zero, 8
0x01 0x00 0x40 0x20 # CHECK: bovc $2, $zero, 8
0x01 0x00 0x82 0x20 # CHECK: bovc $4, $2, 8
0x80 0x18 0x84 0x46 # CHECK: cmp.af.s $f2, $f3, $f4 0x80 0x18 0x84 0x46 # CHECK: cmp.af.s $f2, $f3, $f4
0x80 0x18 0xa4 0x46 # CHECK: cmp.af.d $f2, $f3, $f4 0x80 0x18 0xa4 0x46 # CHECK: cmp.af.d $f2, $f3, $f4
0x81 0x18 0x84 0x46 # CHECK: cmp.un.s $f2, $f3, $f4 0x81 0x18 0x84 0x46 # CHECK: cmp.un.s $f2, $f3, $f4
0x81 0x18 0xa4 0x46 # CHECK: cmp.un.d $f2, $f3, $f4 0x81 0x18 0xa4 0x46 # CHECK: cmp.un.d $f2, $f3, $f4
0x82 0x18 0x84 0x46 # CHECK: cmp.eq.s $f2, $f3, $f4 0x82 0x18 0x84 0x46 # CHECK: cmp.eq.s $f2, $f3, $f4
0x82 0x18 0xa4 0x46 # CHECK: cmp.eq.d $f2, $f3, $f4 0x82 0x18 0xa4 0x46 # CHECK: cmp.eq.d $f2, $f3, $f4
0x83 0x18 0x84 0x46 # CHECK: cmp.ueq.s $f2, $f3, $f4 0x83 0x18 0x84 0x46 # CHECK: cmp.ueq.s $f2, $f3, $f4
0x83 0x18 0xa4 0x46 # CHECK: cmp.ueq.d $f2, $f3, $f4 0x83 0x18 0xa4 0x46 # CHECK: cmp.ueq.d $f2, $f3, $f4
▲ Show 20 Lines • Show All 98 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt

Show All 27 Lines
0x00 0xea 0x00 0x30 # CHECK: tge $7, $10 0x00 0xea 0x00 0x30 # CHECK: tge $7, $10
0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16 0x01 0x70 0x00 0x33 # CHECK: tltu $11, $16
0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13 0x01 0xed 0x00 0x32 # CHECK: tlt $15, $13
0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016 0x02 0x1d 0xfe 0x33 # CHECK: tltu $16, $sp, 1016
0x02 0x8e 0x5e 0xf1 # CHECK: tgeu $20, $14, 379 0x02 0x8e 0x5e 0xf1 # CHECK: tgeu $20, $14, 379
0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp 0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp
0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp 0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
0x04 0x11 0x14 0x9b # CHECK: bal 21104 0x04 0x11 0x14 0x9b # CHECK: bal 21104
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
dsandersUnsubmitted
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Are these FIXME's still true? If you assemble the mnemonics from the disassembler do you get the same opcodes?
I suspect this change may have fixed the ones next to the tests you've updated.

dsanders: Are these FIXME's still true? If you assemble the mnemonics from the disassembler do you get…
nitesh.jainAuthorUnsubmitted
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The encoding and decoding are not inverse of each other. Since while decoding the offset is left shifted by 2 and then 4 is added but in case of encoding it will just right shift by 2. Thus for example

encoding 0x18 0x42 0x01 0x4d -->disassemble -->bgezalc $2, 1336
bgezalc $2, 1336-->assemble-->0x18 0x42 0x01 0x4e
0x18 0x42 0x01 0x4e-->disassemble-->bgezalc $2, 1340.

So these FIXME's will always be true

nitesh.jain: The encoding and decoding are not inverse of each other. Since while decoding the offset is…
dsandersUnsubmitted
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That's definitely a bug, they should be inverses of each other.

I've just looked at the encode function and I think it's wrong for the path this test will use. The immediate path is just 'X >> 2' but the symbol reference path is '(X - 4) >> 2'. Would you be willing to fix the immediate-encode path as part of this patch? That way we can drop these FIXME's.

dsanders: That's definitely a bug, they should be inverses of each other. I've just looked at the encode…
dsandersUnsubmitted
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It appears I'm mistaken on this but we think the current behaviour is weird/wrong in both GAS and IAS. In GAS, immediates are absolute addresses that are modified with +4 for unknown reasons. In IAS, immediates are currently offsets and are not modified.

Your change matches GAS's behaviour so: LGTM with the 'FIXME: ' comments changed to '# The encode/decode functions are not inverses of each other in the immediate case'

dsanders: It appears I'm mistaken on this but we think the current behaviour is weird/wrong in both GAS…
0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1332 0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1336
0x18 0x02 0xff 0xfa # CHECk: blezalc $2, -20
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1332 0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1336
0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 256 0x18 0x42 0xff 0xfa # CHECK: bgezalc $2, -20
# FIXME: The encode/decode functions are not inverses of each other. 0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 260
0x1c 0x02 0x01 0x4d # CHECK: bgtzalc $2, 1332 0x18 0x43 0xff 0xfa # CHECK: bgeuc $2, $3, -20
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, 1332 0x1c 0x02 0x01 0x4d # CHECK: bgtzalc $2, 1336
0x1c 0xa6 0x00 0x40 # CHECK: bltuc $5, $6, 256 0x1c 0x02 0xff 0xfa # CHECK: bgtzalc $2, -20
0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 4 # FIXME: The encode/decode functions are not inverses of each other.
# FIXME: The encode/decode functions are not inverses of each other. 0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, 1336
0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, 1332 0x1c 0x42 0xff 0xfa # CHECK: bltzalc $2, -20
0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 4 0x1c 0xa6 0x00 0x40 # CHECK: bltuc $5, $6, 260
0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 4 0x1c 0xa6 0xff 0xfa # CHECK: bltuc $5, $6, -20
0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256 0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 8
# FIXME: The encode/decode functions are not inverses of each other.
0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, 1336
0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 8
0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 8
0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 260
0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10 0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10
0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4
0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4 0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4
0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23 0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23
0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1 0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
0x40 0x08 0x80 0x03 # CHECK: mfc0 $8, $16, 3 0x40 0x08 0x80 0x03 # CHECK: mfc0 $8, $16, 3
0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1 0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
0x41 0x60 0x60 0x00 # CHECK: di 0x41 0x60 0x60 0x00 # CHECK: di
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# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12 # The immediate should be 8 but the disassembler currently emits 12
0x49 0xa0 0x00 0x02 # CHECK: bc2nez $0, 12 0x49 0xa0 0x00 0x02 # CHECK: bc2nez $0, 12
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12 # The immediate should be 8 but the disassembler currently emits 12
0x49 0xbf 0x00 0x02 # CHECK: bc2nez $31, 12 0x49 0xbf 0x00 0x02 # CHECK: bc2nez $31, 12
0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1) 0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1)
0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18) 0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18)
0x58 0x05 0x00 0x40 # CHECK: blezc $5, 256 0x58 0x05 0x00 0x40 # CHECK: blezc $5, 260
0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 256 0x58 0x05 0xff 0xfa # CHECk: blezc $5, -20
0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 256 0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 260
0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 256 0x58 0x43 0xff 0xfa # CHECK: bgec $2, $3, -20
0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 256 0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 260
0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 256 0x58 0xa5 0xff 0xfa # CHECK: bgezc $5, -20
0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4 0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 260
# FIXME: The encode/decode functions are not inverses of each other. 0x5c 0x05 0xff 0xfa # CHECk: bgtzc $5, -20
0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, 1332 0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 260
0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 4 0x5c 0xa5 0xff 0xfa # CHECK: bltzc $5, -20
0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 4 0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 260
0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256 0x5c 0xa6 0xff 0xfa # CHECK: bltc $5, $6, -20
0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 8
# FIXME: The encode/decode functions are not inverses of each other.
0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, 1336
0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 8
0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 8
0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 260
0x60 0x43 0xff 0xfa # CHECK: bnec $2, $3, -20
0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2 0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2
0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2 0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2
0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5) 0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5) 0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18) 0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18)
0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19) 0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19)
0xc8 0x37 0x96 0xb8 # CHECK: bc 14572256 0xc8 0x37 0x96 0xb8 # CHECK: bc 14572260
0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256 0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72256 0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72260
0xe8 0x37 0x96 0xb8 # CHECK: balc 14572256 0xd8 0x5f 0xff 0xfa # CHECK: beqzc $2, -20
0xe8 0x37 0x96 0xb8 # CHECK: balc 14572260
0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268 0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268
0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268 0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268
0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1 0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1
0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100 0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100
0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256 0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256 0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72260
0xf8 0x5f 0xff 0xfa # CHECK: bnezc $2, -20

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt

# RUN: llvm-mc %s -disassemble -triple=mipsel-unknown-linux -mcpu=mips64r6 | FileCheck %s # RUN: llvm-mc %s -disassemble -triple=mipsel-unknown-linux -mcpu=mips64r6 | FileCheck %s
0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10 0x0a 0x00 0x29 0x25 # CHECK: addiu $9, $9, 10
0x19 0x00 0x80 0xec # CHECK: addiupc $4, 100 0x19 0x00 0x80 0xec # CHECK: addiupc $4, 100
0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2 0xa0 0x22 0x43 0x7c # CHECK: align $4, $2, $3, 2
0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56 0x38 0x00 0x7f 0xec # CHECK: aluipc $3, 56
0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4 0x04 0x00 0x42 0x30 # CHECK: andi $2, $2, 4
0xe9 0xff 0x62 0x3c # CHECK: aui $3, $2, -23 0xe9 0xff 0x62 0x3c # CHECK: aui $3, $2, -23
0xff 0xff 0x7e 0xec # CHECK: auipc $3, -1 0xff 0xff 0x7e 0xec # CHECK: auipc $3, -1
0x9b 0x14 0x11 0x04 # CHECK: bal 21104 0x9b 0x14 0x11 0x04 # CHECK: bal 21104
0xb8 0x96 0x37 0xe8 # CHECK: balc 14572256 0xb8 0x96 0x37 0xe8 # CHECK: balc 14572260
0xb8 0x96 0x37 0xc8 # CHECK: bc 14572256 0xb8 0x96 0x37 0xc8 # CHECK: bc 14572260
0x01 0x00 0x20 0x45 # CHECK: bc1eqz $f0, 8 0x01 0x00 0x20 0x45 # CHECK: bc1eqz $f0, 8
0x01 0x00 0x3f 0x45 # CHECK: bc1eqz $f31, 8 0x01 0x00 0x3f 0x45 # CHECK: bc1eqz $f31, 8
0x01 0x00 0xa0 0x45 # CHECK: bc1nez $f0, 8 0x01 0x00 0xa0 0x45 # CHECK: bc1nez $f0, 8
0x01 0x00 0xbf 0x45 # CHECK: bc1nez $f31, 8 0x01 0x00 0xbf 0x45 # CHECK: bc1nez $f31, 8
0x02 0x00 0x20 0x49 # CHECK: bc2eqz $0, 12 0x02 0x00 0x20 0x49 # CHECK: bc2eqz $0, 12
0x02 0x00 0x3f 0x49 # CHECK: bc2eqz $31, 12 0x02 0x00 0x3f 0x49 # CHECK: bc2eqz $31, 12
0x02 0x00 0xa0 0x49 # CHECK: bc2nez $0, 12 0x02 0x00 0xa0 0x49 # CHECK: bc2nez $0, 12
0x02 0x00 0xbf 0x49 # CHECK: bc2nez $31, 12 0x02 0x00 0xbf 0x49 # CHECK: bc2nez $31, 12
0x40 0x00 0xa6 0x20 # CHECK: beqc $5, $6, 256 0x40 0x00 0xa6 0x20 # CHECK: beqc $5, $6, 260
0x4d 0x01 0x02 0x20 # CHECK: beqzalc $2, 1332 0x4d 0x01 0x02 0x20 # CHECK: beqzalc $2, 1336
0x90 0x46 0xa0 0xd8 # CHECK: beqzc $5, 72256 0x90 0x46 0xa0 0xd8 # CHECK: beqzc $5, 72260
0x40 0x00 0x43 0x58 # CHECK: bgec $2, $3, 256 0xfa 0xff 0x5f 0xd8 # CHECK: beqzc $2, -20
0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 256 0x40 0x00 0x43 0x58 # CHECK: bgec $2, $3, 260
0x4d 0x01 0x42 0x18 # CHECK: bgezalc $2, 1332 0xfa 0xff 0x43 0x58 # CHECK: bgec $2, $3, -20
0x40 0x00 0xa5 0x58 # CHECK: bgezc $5, 256 0x40 0x00 0x43 0x18 # CHECK: bgeuc $2, $3, 260
0x4d 0x01 0x02 0x1c # CHECK: bgtzalc $2, 1332 0xfa 0xff 0x43 0x18 # CHECK: bgeuc $2, $3, -20
0x40 0x00 0x05 0x5c # CHECK: bgtzc $5, 256 0x4d 0x01 0x42 0x18 # CHECK: bgezalc $2, 1336
0xfa 0xff 0x42 0x18 # CHECK: bgezalc $2, -20
0x40 0x00 0xa5 0x58 # CHECK: bgezc $5, 260
0xfa 0xff 0xa5 0x58 # CHECK: bgezc $5, -20
0x4d 0x01 0x02 0x1c # CHECK: bgtzalc $2, 1336
0xfa 0xff 0x02 0x1c # CHECK: bgtzalc $2, -20
0x40 0x00 0x05 0x5c # CHECK: bgtzc $5, 260
0xfa 0xff 0x05 0x5c # CHECK: bgtzc $5, -20
0x20 0x20 0x02 0x7c # CHECK: bitswap $4, $2 0x20 0x20 0x02 0x7c # CHECK: bitswap $4, $2
0x4d 0x01 0x02 0x18 # CHECK: blezalc $2, 1332 0x4d 0x01 0x02 0x18 # CHECK: blezalc $2, 1336
0x40 0x00 0x05 0x58 # CHECK: blezc $5, 256 0xfa 0xff 0x02 0x18 # CHECK: blezalc $2, -20
0x40 0x00 0xa6 0x5c # CHECK: bltc $5, $6, 256 0x40 0x00 0x05 0x58 # CHECK: blezc $5, 260
0x40 0x00 0xa6 0x1c # CHECK: bltuc $5, $6, 256 0xfa 0xff 0x05 0x58 # CHECK: blezc $5, -20
0x4d 0x01 0x42 0x1c # CHECK: bltzalc $2, 1332 0x40 0x00 0xa6 0x5c # CHECK: bltc $5, $6, 260
0x40 0x00 0xa5 0x5c # CHECK: bltzc $5, 256 0xfa 0xff 0xa6 0x5c # CHECK: bltc $5, $6, -20
0x40 0x00 0xa6 0x60 # CHECK: bnec $5, $6, 256 0x40 0x00 0xa6 0x1c # CHECK: bltuc $5, $6, 260
0x4d 0x01 0x02 0x60 # CHECK: bnezalc $2, 1332 0xfa 0xff 0xa6 0x1c # CHECK: bltuc $5, $6, -20
0x90 0x46 0xa0 0xf8 # CHECK: bnezc $5, 72256 0x4d 0x01 0x42 0x1c # CHECK: bltzalc $2, 1336
0x01 0x00 0x40 0x60 # CHECK: bnvc $2, $zero, 4 0xfa 0xff 0x42 0x1c # CHECK: bltzalc $2, -20
0x01 0x00 0x82 0x60 # CHECK: bnvc $4, $2, 4 0x40 0x00 0xa5 0x5c # CHECK: bltzc $5, 260
0x01 0x00 0x00 0x60 # CHECK: bnvc $zero, $zero, 4 0xfa 0xff 0xa5 0x5c # CHECK: bltzc $5, -20
0x01 0x00 0x40 0x20 # CHECK: bovc $2, $zero, 4 0x40 0x00 0xa6 0x60 # CHECK: bnec $5, $6, 260
0x01 0x00 0x82 0x20 # CHECK: bovc $4, $2, 4 0xfa 0xff 0x43 0x60 # CHECK: bnec $2, $3, -20
0x01 0x00 0x00 0x20 # CHECK: bovc $zero, $zero, 4 0x4d 0x01 0x02 0x60 # CHECK: bnezalc $2, 1336
0x90 0x46 0xa0 0xf8 # CHECK: bnezc $5, 72260
0xfa 0xff 0x5f 0xf8 # CHECK: bnezc $2, -20
0x01 0x00 0x40 0x60 # CHECK: bnvc $2, $zero, 8
0x01 0x00 0x82 0x60 # CHECK: bnvc $4, $2, 8
0x01 0x00 0x00 0x60 # CHECK: bnvc $zero, $zero, 8
0x01 0x00 0x40 0x20 # CHECK: bovc $2, $zero, 8
0x01 0x00 0x82 0x20 # CHECK: bovc $4, $2, 8
0x01 0x00 0x00 0x20 # CHECK: bovc $zero, $zero, 8
0x25 0x04 0xa1 0x7c # CHECK: cache 1, 8($5) 0x25 0x04 0xa1 0x7c # CHECK: cache 1, 8($5)
0x9b 0x20 0x20 0x46 # CHECK: class.d $f2, $f4 0x9b 0x20 0x20 0x46 # CHECK: class.d $f2, $f4
0x9b 0x20 0x00 0x46 # CHECK: class.s $f2, $f4 0x9b 0x20 0x00 0x46 # CHECK: class.s $f2, $f4
0x51 0x58 0xa0 0x00 # CHECK: clo $11, $5 0x51 0x58 0xa0 0x00 # CHECK: clo $11, $5
0x50 0xe8 0x80 0x03 # CHECK: clz $sp, $gp 0x50 0xe8 0x80 0x03 # CHECK: clz $sp, $gp
0x80 0x18 0xa4 0x46 # CHECK: cmp.af.d $f2, $f3, $f4 0x80 0x18 0xa4 0x46 # CHECK: cmp.af.d $f2, $f3, $f4
0x80 0x18 0x84 0x46 # CHECK: cmp.af.s $f2, $f3, $f4 0x80 0x18 0x84 0x46 # CHECK: cmp.af.s $f2, $f3, $f4
0x82 0x18 0xa4 0x46 # CHECK: cmp.eq.d $f2, $f3, $f4 0x82 0x18 0xa4 0x46 # CHECK: cmp.eq.d $f2, $f3, $f4
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test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt

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0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25 0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25
0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp 0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra 0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra
0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra 0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra
0x04 0x11 0x14 0x9b # CHECK: bal 21104 0x04 0x11 0x14 0x9b # CHECK: bal 21104
0x04 0x66 0x56 0x78 # CHECK: dahi $3, 22136 0x04 0x66 0x56 0x78 # CHECK: dahi $3, 22136
0x04 0x7e 0xab 0xcd # CHECK: dati $3, -21555 0x04 0x7e 0xab 0xcd # CHECK: dati $3, -21555
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1332 0x18 0x02 0x01 0x4d # CHECK: blezalc $2, 1336
0x18 0x02 0xff 0xfa # CHECk: blezalc $2, -20
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1332 0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 1336
0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 256 0x18 0x42 0xff 0xfa # CHECK: bgezalc $2, -20
# FIXME: The encode/decode functions are not inverses of each other. 0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 260
0x1c 0x02 0x01 0x4d # CHECK: bgtzalc $2, 1332 0x18 0x43 0xff 0xfa # CHECK: bgeuc $2, $3, -20
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, 1332 0x1c 0x02 0x01 0x4d # CHECK: bgtzalc $2, 1336
0x1c 0xa6 0x00 0x40 # CHECK: bltuc $5, $6, 256 0x1c 0x02 0xff 0xfa # CHECK: bgtzalc $2, -20
0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 4 # FIXME: The encode/decode functions are not inverses of each other.
# FIXME: The encode/decode functions are not inverses of each other. 0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, 1336
0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, 1332 0x1c 0x42 0xff 0xfa # CHECK: bltzalc $2, -20
0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 4 0x1c 0xa6 0x00 0x40 # CHECK: bltuc $5, $6, 260
0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 4 0x1c 0xa6 0xff 0xfa # CHECK: bltuc $5, $6, -20
0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256 0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 8
# FIXME: The encode/decode functions are not inverses of each other.
0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, 1336
0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 8
0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 8
0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 260
0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10 0x25 0x29 0x00 0x0a # CHECK: addiu $9, $9, 10
0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4 0x30 0x42 0x00 0x04 # CHECK: andi $2, $2, 4
0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4 0x34 0x42 0x00 0x04 # CHECK: ori $2, $2, 4
0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23 0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23
0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1 0x40 0x08 0x78 0x01 # CHECK: mfc0 $8, $15, 1
0x40 0x08 0x80 0x03 # CHECK: mfc0 $8, $16, 3 0x40 0x08 0x80 0x03 # CHECK: mfc0 $8, $16, 3
0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0 0x40 0x38 0x50 0x00 # CHECK: dmfc0 $24, $10, 0
0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1 0x40 0x89 0x78 0x01 # CHECK: mtc0 $9, $15, 1
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# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12 # The immediate should be 8 but the disassembler currently emits 12
0x49 0xa0 0x00 0x02 # CHECK: bc2nez $0, 12 0x49 0xa0 0x00 0x02 # CHECK: bc2nez $0, 12
# FIXME: The encode/decode functions are not inverses of each other. # FIXME: The encode/decode functions are not inverses of each other.
# The immediate should be 8 but the disassembler currently emits 12 # The immediate should be 8 but the disassembler currently emits 12
0x49 0xbf 0x00 0x02 # CHECK: bc2nez $31, 12 0x49 0xbf 0x00 0x02 # CHECK: bc2nez $31, 12
0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1) 0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1)
0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18) 0x49 0xf4 0x92 0x75 # CHECK: sdc2 $20, 629($18)
0x58 0x05 0x00 0x40 # CHECK: blezc $5, 256 0x58 0x05 0x00 0x40 # CHECK: blezc $5, 260
0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 256 0x58 0x05 0xff 0xfa # CHECk: blezc $5, -20
0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 256 0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 260
0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 256 0x58 0x43 0xff 0xfa # CHECK: bgec $2, $3, -20
0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 256 0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 260
0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 256 0x58 0xa5 0xff 0xfa # CHECK: bgezc $5, -20
0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4 0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 260
# FIXME: The encode/decode functions are not inverses of each other. 0x5c 0x05 0xff 0xfa # CHECk: bgtzc $5, -20
0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, 1332 0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 260
0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 4 0x5c 0xa5 0xff 0xfa # CHECK: bltzc $5, -20
0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 4 0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 260
0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256 0x5c 0xa6 0xff 0xfa # CHECK: bltc $5, $6, -20
0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 8
# FIXME: The encode/decode functions are not inverses of each other.
0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, 1336
0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 8
0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 8
0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 260
0x60 0x43 0xff 0xfa # CHECK: bnec $2, $3, -20
0x74 0x62 0x12 0x34 # CHECK: daui $3, $2, 4660 0x74 0x62 0x12 0x34 # CHECK: daui $3, $2, 4660
0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2 0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2
0x7c 0x02 0x20 0x24 # CHECK: dbitswap $4, $2 0x7c 0x02 0x20 0x24 # CHECK: dbitswap $4, $2
0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2 0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2
0x7c 0x43 0x23 0x64 # CHECK: dalign $4, $2, $3, 5 0x7c 0x43 0x23 0x64 # CHECK: dalign $4, $2, $3, 5
0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5) 0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5) 0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18) 0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18)
0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19) 0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19)
0x7f 0xaf 0xe6 0xa7 # CHECK: scd $15, -51($sp) 0x7f 0xaf 0xe6 0xa7 # CHECK: scd $15, -51($sp)
0x7f 0xe0 0x38 0x37 # CHECK: lld $zero, 112($ra) 0x7f 0xe0 0x38 0x37 # CHECK: lld $zero, 112($ra)
0xc8 0x37 0x96 0xb8 # CHECK: bc 14572256 0xc8 0x37 0x96 0xb8 # CHECK: bc 14572260
0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256 0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72256 0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72260
0xd8 0x5f 0xff 0xfa # CHECK: beqzc $2, -20
0xe8 0x37 0x96 0xb8 # CHECK: balc 14572256 0xe8 0x37 0x96 0xb8 # CHECK: balc 14572256
0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268 0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268
0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268 0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268
0xec 0x58 0x3c 0x48 # CHECK: ldpc $2, 123456 0xec 0x58 0x3c 0x48 # CHECK: ldpc $2, 123456
0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1 0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1
0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100 0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100
0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256 0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256 0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256
0xf8 0x5f 0xff 0xfa # CHECK: bnezc $2, -20

test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt

# Instructions that should be valid but currently fail for known reasons (e.g. # Instructions that should be valid but currently fail for known reasons (e.g.
# they aren't implemented yet). # they aren't implemented yet).
# #
# RUN: llvm-mc %s -disassemble -triple=mips-unknown-linux -mcpu=mips64r6 | FileCheck %s # RUN: llvm-mc %s -disassemble -triple=mips-unknown-linux -mcpu=mips64r6 | FileCheck %s
# XFAIL: * # XFAIL: *
0x20 0x40 0x00 0x01 # CHECK: bovc $0, $2, 4 0x20 0x40 0x00 0x01 # CHECK: bovc $0, $2, 8
0x20 0x82 0x00 0x01 # CHECK: bovc $2, $4, 4 0x20 0x82 0x00 0x01 # CHECK: bovc $2, $4, 8
0x60 0x40 0x00 0x01 # CHECK: bnvc $0, $2, 4 0x60 0x40 0x00 0x01 # CHECK: bnvc $0, $2, 8
0x60 0x82 0x00 0x01 # CHECK: bnvc $2, $4, 4 0x60 0x82 0x00 0x01 # CHECK: bnvc $2, $4, 8
0x20 0xc0 0x00 0x40 # CHECK: beqc $6, $zero, 256 0x20 0xc0 0x00 0x40 # CHECK: beqc $6, $zero, 260
0x20 0xa0 0x00 0x40 # CHECK: beqc $5, $zero, 256 0x20 0xa0 0x00 0x40 # CHECK: beqc $5, $zero, 260
0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256 0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 260
0x60 0xc0 0x00 0x40 # CHECK: bnec $6, $zero, 256 0x60 0xc0 0x00 0x40 # CHECK: bnec $6, $zero, 260
0x60 0xa0 0x00 0x40 # CHECK: bnec $5, $zero, 256 0x60 0xa0 0x00 0x40 # CHECK: bnec $5, $zero, 260
0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256 0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 260
0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079 0x64 0x58 0x46 0x9f # CHECK: daddiu $24, $2, 18079
0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943 0x66 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943
0x65 0x6f 0xec 0x5f # CHECK: daddiu $15, $11, -5025 0x65 0x6f 0xec 0x5f # CHECK: daddiu $15, $11, -5025
0x65 0xce 0x11 0xea # CHECK: daddiu $14, $14, 4586 0x65 0xce 0x11 0xea # CHECK: daddiu $14, $14, 4586
0x04 0x7e 0xab 0xcd # CHECK: dati $3, 43981 0x04 0x7e 0xab 0xcd # CHECK: dati $3, 43981