[X86] Add address space for SS segment

[mlemay-intel]

Summary

This patch adds support for address space #258 to refer to the stack
segment (SS). It is analogous to address spaces #256 and #257, which
refer to the GS and FS segments, respectively. This can be used to
direct data accesses to the stack segment, which may be necessary when
a multi-segment memory model is in use.

For example, if the stack segment has a different base address than
the data segment, then it is necessary to output a segment override
prefix to direct a stack access to the stack segment if the memory
operand uses a base address register other than ESP or EBP.
Otherwise, the memory access would be directed to the data segment by
default, which would result in the wrong linear memory address being
accessed.

An example of a system configuration that would result in using
different base addresses for stack and data segments is one in which
the stack and data segments are separated to prevent accesses to the
data segment from corrupting a safe stack that is setup and maintained
by the SafeStack instrumentation pass in Clang. See the SafeStack
runtime library source comments for more details.

Note that although this patch provides the basic support for the stack
segment address space, it does not perform any address space casts
into this address space.

[delena]

test/CodeGen/X86/movss.ll

2

Please use FileCheck instead of grep

[mlemay-intel]

Use FileCheck instead of grep in test.

[mkuper]

lib/Target/X86/X86ISelDAGToDAG.cpp

1429

There's also similar code in X86DAGToDAGISel::matchLoadInAddress().
Did you leave that unchanged on purpose?

If yes, perhaps it's worth adding a comment there for why. If not, perhaps factor it out into a separate function instead of having it duplicated 3 times?

test/CodeGen/X86/movss.ll

6

Can you make the test slightly more explicit?
The current check would match a "movss" instruction, for example.

Also, it would be nice to make it slightly smaller, e.g. something like

define i32 @foo(i32 addrspace(258)* %p) {
  %tmp = load i32, i32 addrspace(258)* %p
  ret i32 %tmp
}

[mlemay-intel]

Added comment to make it clear that a related piece of code was not overlooked.
Streamlined test and made it more precise.

[mlemay-intel]

Update documentation.

[mkuper]

LGTM

[mlemay-intel]

In D17093#410046, @mkuper wrote:

LGTM

@mkuper: Can you please land this and D19458? Thanks!

docs/CodeGenerator.rst

 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 x86 has a feature which provides the ability to perform loads and stores to
 different address spaces via the x86 segment registers.  A segment override
 prefix byte on an instruction causes the instruction's memory access to go to
 the specified segment.  LLVM address space 0 is the default address space, which
 includes the stack, and any unqualified memory accesses in a program.  Address
 spaces 1-255 are currently reserved for user-defined code.  The GS-segment is
-represented by address space 256, while the FS-segment is represented by address
-space 257. Other x86 segments have yet to be allocated address space
-numbers.
+represented by address space 256, the FS-segment is represented by address space
+257, and the SS-segment is represented by address space 258. Other x86 segments
+have yet to be allocated address space numbers.
 
 While these address spaces may seem similar to TLS via the ``thread_local``
 keyword, and often use the same underlying hardware, there are some fundamental
 differences.
 
 The ``thread_local`` keyword applies to global variables and specifies that they
 are to be allocated in thread-local memory. There are no type qualifiers
 involved, and these variables can be pointed to with normal pointers and

lib/Target/X86/X86ISelDAGToDAG.cpp

if (C->getSExtValue() == 0 && AM.Segment.getNode() == nullptr &&
         Subtarget->isTargetLinux())
       switch (N->getPointerInfo().getAddrSpace()) {
       case 256:
         AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
         return false;
       case 257:
         AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
         return false;
+      // Address space 258 is not handled here, because it is not used to
+      // address TLS areas.
       }
 
   return true;
 }
 
 /// Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes into an addressing
 /// mode. These wrap things that will resolve down into a symbol reference.
 /// If no match is possible, this returns true, otherwise it returns false.
bool X86DAGToDAGISel::selectVectorAddr(SDNode *Parent, SDValue N, SDValue &Base,
                                       SDValue &Scale, SDValue &Index,
                                       SDValue &Disp, SDValue &Segment) {
 
   MaskedGatherScatterSDNode *Mgs = dyn_cast<MaskedGatherScatterSDNode>(Parent);
   if (!Mgs)
     return false;
   X86ISelAddressMode AM;
   unsigned AddrSpace = Mgs->getPointerInfo().getAddrSpace();
-  // AddrSpace 256 -> GS, 257 -> FS.
+  // AddrSpace 256 -> GS, 257 -> FS, 258 -> SS.
   if (AddrSpace == 256)
     AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
   if (AddrSpace == 257)
     AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
+  if (AddrSpace == 258)
+    AM.Segment = CurDAG->getRegister(X86::SS, MVT::i16);
 
   SDLoc DL(N);
   Base = Mgs->getBasePtr();
   Index = Mgs->getIndex();
   unsigned ScalarSize = Mgs->getValue().getValueType().getScalarSizeInBits();
   Scale = getI8Imm(ScalarSize/8, DL);
 
   // If Base is 0, the whole address is in index and the Scale is 1
if (Parent &&
       // that are not a MemSDNode, and thus don't have proper addrspace info.
       Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
       Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
       Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
       Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
       Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
     unsigned AddrSpace =
       cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
-    // AddrSpace 256 -> GS, 257 -> FS.
+    // AddrSpace 256 -> GS, 257 -> FS, 258 -> SS.
     if (AddrSpace == 256)
       AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
     if (AddrSpace == 257)
       AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
+    if (AddrSpace == 258)
+      AM.Segment = CurDAG->getRegister(X86::SS, MVT::i16);
   }
 
   if (matchAddress(N, AM))
     return false;
 
   MVT VT = N.getSimpleValueType();
   if (AM.BaseType == X86ISelAddressMode::RegBase) {
     if (!AM.Base_Reg.getNode())

test/CodeGen/X86/movss.ll

+; RUN: llc < %s -march=x86 | FileCheck %s
+
+define i32 @foo(i32 addrspace(258)* %p) {
+entry:
+; CHECK: movl %ss:
+  %tmp = load i32, i32 addrspace(258)* %p
+  ret i32 %tmp
+}