[llvm-readobj][ELF] Teach llvm-readobj to show arch specific ELF section's flags

[atanasyan]

Summary

Some architecture specific ELF section flags might have the same value (for example SHF_X86_64_LARGE and SHF_HEX_GPREL) and we have to check machine architectures to select an appropriate set of possible flags.

The patch selects architecture specific flags into separate arrays ElfxxxSectionFlags and combines ElfSectionFlags and ElfxxxSectionFlags before pass to the StreamWriter::printFlags() method.

[davide]

The readobj changes look fine, modulo comment.

tools/llvm-readobj/ELFDumper.cpp

1161 ↗

(On Diff #45097)

Missing default case I guess?

[davide]

Just one thing: I don't know AMDGPU target at all. I think the changes there are correct but I'd be happier if Tom or Matt can sign-off the AMDGPU specific bits of this patch.

[atanasyan]

tools/llvm-readobj/ELFDumper.cpp

1161 ↗

(On Diff #45097)

By default we do not need to add any additional flags to the SectionFlags container. Is it okay to put the following a bit redundant code here?

default:
  break;

[davide]

tools/llvm-readobj/ELFDumper.cpp

1161 ↗

(On Diff #45097)

I'm fine with less code (and happier, in general) but please make sure neither gcc or clang will complain with "non all cases covered in switch statement".

[atanasyan]

Tom, Matt do you have any notes/objections on AMDGPU part of the patch?

[• tstellarAMD]

AMDGPU changes LGTM.

[• rafael]

LGTM assuming no warnings.

llvm/trunk/lib/Object/ELFYAML.cpp

case ELF::EM_AVR:
     BCase(EF_AVR_ARCH_XMEGA1)
     BCase(EF_AVR_ARCH_XMEGA2)
     BCase(EF_AVR_ARCH_XMEGA3)
     BCase(EF_AVR_ARCH_XMEGA4)
     BCase(EF_AVR_ARCH_XMEGA5)
     BCase(EF_AVR_ARCH_XMEGA6)
     BCase(EF_AVR_ARCH_XMEGA7)
     break;
+  case ELF::EM_AMDGPU:
+  case ELF::EM_X86_64:
+    break;
   default:
     llvm_unreachable("Unsupported architecture");
   }
 #undef BCase
 #undef BCaseMask
 }
 
 void ScalarEnumerationTraits<ELFYAML::ELF_SHT>::enumeration(
#define BCase(X) IO.bitSetCase(Value, #X, ELF::X);
   BCase(SHF_TLS)
   switch(Object->Header.Machine) {
   case ELF::EM_AMDGPU:
     BCase(SHF_AMDGPU_HSA_GLOBAL)
     BCase(SHF_AMDGPU_HSA_READONLY)
     BCase(SHF_AMDGPU_HSA_CODE)
     BCase(SHF_AMDGPU_HSA_AGENT)
     break;
+  case ELF::EM_HEXAGON:
+    BCase(SHF_HEX_GPREL)
+    break;
+  case ELF::EM_MIPS:
+    BCase(SHF_MIPS_NODUPES)
+    BCase(SHF_MIPS_NAMES)
+    BCase(SHF_MIPS_LOCAL)
+    BCase(SHF_MIPS_NOSTRIP)
+    BCase(SHF_MIPS_GPREL)
+    BCase(SHF_MIPS_MERGE)
+    BCase(SHF_MIPS_ADDR)
+    BCase(SHF_MIPS_STRING)
+    break;
+  case ELF::EM_X86_64:
+    BCase(SHF_X86_64_LARGE)
+    break;
   default:
     // Nothing to do.
     break;
   }
 #undef BCase
 }
 
 void ScalarEnumerationTraits<ELFYAML::ELF_STT>::enumeration(

llvm/trunk/test/Object/obj2yaml.test

 ELF-MIPS64EL-NEXT:         Symbol:          zed
 ELF-MIPS64EL-NEXT:         Type:            R_MIPS_64
 ELF-MIPS64EL-NEXT:   - Name:            .bss
 ELF-MIPS64EL-NEXT:     Type:            SHT_NOBITS
 ELF-MIPS64EL-NEXT:     Flags:           [ SHF_WRITE, SHF_ALLOC ]
 ELF-MIPS64EL-NEXT:     AddressAlign:    0x0000000000000010
 ELF-MIPS64EL-NEXT:   - Name:            .MIPS.options
 ELF-MIPS64EL-NEXT:     Type:            SHT_MIPS_OPTIONS
-ELF-MIPS64EL-NEXT:     Flags:           [ SHF_ALLOC ]
+ELF-MIPS64EL-NEXT:     Flags:           [ SHF_ALLOC, SHF_MIPS_NOSTRIP ]
 ELF-MIPS64EL-NEXT:     AddressAlign:    0x0000000000000008
 ELF-MIPS64EL-NEXT:     Content:         '01280000000000000000000000000000000000000000000000000000000000000000000000000000'
 ELF-MIPS64EL-NEXT:   - Name:            .pdr
 ELF-MIPS64EL-NEXT:     Type:            SHT_PROGBITS
 ELF-MIPS64EL-NEXT:     AddressAlign:    0x0000000000000004
 ELF-MIPS64EL-NEXT:     Content:         ''
 ELF-MIPS64EL-NEXT: Symbols:
 ELF-MIPS64EL-NEXT:   Local:

llvm/trunk/test/tools/llvm-readobj/elf-sec-flags.test

+# Check that llvm-readobj shows arch specific ELF section flags.
+
+# RUN: yaml2obj -format=elf -docnum 1 %s > %t-amdgpu.o
+# RUN: llvm-readobj -s %t-amdgpu.o | FileCheck -check-prefix=AMD %s
+
+# AMD:      Flags [ (0x300000)
+# AMD-NEXT:   SHF_AMDGPU_HSA_GLOBAL (0x100000)
+# AMD-NEXT:   SHF_AMDGPU_HSA_READONLY (0x200000)
+# AMD-NEXT: ]
+
+# amdgpu.o
+---
+FileHeader:
+  Class:    ELFCLASS64
+  Data:     ELFDATA2LSB
+  OSABI:    ELFOSABI_GNU
+  Type:     ET_REL
+  Machine:  EM_AMDGPU
+  Flags:    []
+Sections:
+  - Name:   .amdgpu
+    Type:   SHT_PROGBITS
+    Flags:  [SHF_AMDGPU_HSA_GLOBAL, SHF_AMDGPU_HSA_READONLY]
+    Size:   4
+
+# RUN: yaml2obj -format=elf -docnum 2 %s > %t-hex.o
+# RUN: llvm-readobj -s %t-hex.o | FileCheck -check-prefix=HEX %s
+
+# HEX:      Flags [ (0x10000000)
+# HEX-NEXT:   SHF_HEX_GPREL (0x10000000)
+# HEX-NEXT: ]
+
+# hex.o
+---
+FileHeader:
+  Class:    ELFCLASS32
+  Data:     ELFDATA2LSB
+  Type:     ET_REL
+  Machine:  EM_HEXAGON
+  Flags:    []
+Sections:
+  - Name:   .hex
+    Type:   SHT_PROGBITS
+    Flags:  [SHF_HEX_GPREL]
+    Size:   4
+
+# RUN: yaml2obj -format=elf -docnum 3 %s > %t-mips.o
+# RUN: llvm-readobj -s %t-mips.o | FileCheck -check-prefix=MIPS %s
+
+# MIPS:      Flags [ (0x38000000)
+# MIPS-NEXT:   SHF_MIPS_GPREL (0x10000000)
+# MIPS-NEXT:   SHF_MIPS_MERGE (0x20000000)
+# MIPS-NEXT:   SHF_MIPS_NOSTRIP (0x8000000)
+# MIPS-NEXT: ]
+
+# mips.o
+---
+FileHeader:
+  Class:    ELFCLASS32
+  Data:     ELFDATA2LSB
+  Type:     ET_REL
+  Machine:  EM_MIPS
+  Flags:    []
+Sections:
+  - Name:   .mips
+    Type:   SHT_PROGBITS
+    Flags:  [SHF_MIPS_GPREL, SHF_MIPS_MERGE, SHF_MIPS_NOSTRIP]
+    Size:   4
+
+# RUN: yaml2obj -format=elf -docnum 4 %s > %t-x86_64.o
+# RUN: llvm-readobj -s %t-x86_64.o | FileCheck -check-prefix=X86_64 %s
+
+# X86_64:      Flags [ (0x10000000)
+# X86_64-NEXT:   SHF_X86_64_LARGE (0x10000000)
+# X86_64-NEXT: ]
+
+# x86_64.o
+---
+FileHeader:
+  Class:    ELFCLASS64
+  Data:     ELFDATA2LSB
+  Type:     ET_REL
+  Machine:  EM_X86_64
+  Flags:    []
+Sections:
+  - Name:   .x86_64
+    Type:   SHT_PROGBITS
+    Flags:  [SHF_X86_64_LARGE]
+    Size:   4
+...

llvm/trunk/tools/llvm-readobj/ELFDumper.cpp

static const EnumEntry<unsigned> ElfSectionFlags[] = {
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_STRINGS         ),
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_INFO_LINK       ),
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_LINK_ORDER      ),
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_OS_NONCONFORMING),
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_GROUP           ),
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_TLS             ),
   LLVM_READOBJ_ENUM_ENT(ELF, XCORE_SHF_CP_SECTION),
   LLVM_READOBJ_ENUM_ENT(ELF, XCORE_SHF_DP_SECTION),
-  LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_NOSTRIP    ),
+};
+
+static const EnumEntry<unsigned> ElfAMDGPUSectionFlags[] = {
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_AMDGPU_HSA_GLOBAL),
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_AMDGPU_HSA_READONLY),
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_AMDGPU_HSA_CODE),
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_AMDGPU_HSA_AGENT)
 };
 
+static const EnumEntry<unsigned> ElfHexagonSectionFlags[] = {
+  LLVM_READOBJ_ENUM_ENT(ELF, SHF_HEX_GPREL)
+};
+
+static const EnumEntry<unsigned> ElfMipsSectionFlags[] = {
+  LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_NODUPES),
+  LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_NAMES  ),
+  LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_LOCAL  ),
+  LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_NOSTRIP),
+  LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_GPREL  ),
+  LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_MERGE  ),
+  LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_ADDR   ),
+  LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_STRING )
+};
+
+static const EnumEntry<unsigned> ElfX86_64SectionFlags[] = {
+  LLVM_READOBJ_ENUM_ENT(ELF, SHF_X86_64_LARGE)
+};
+
 static const char *getElfSegmentType(unsigned Arch, unsigned Type) {
   // Check potentially overlapped processor-specific
   // program header type.
   switch (Arch) {
   case ELF::EM_AMDGPU:
     switch (Type) {
     LLVM_READOBJ_ENUM_CASE(ELF, PT_AMDGPU_HSA_LOAD_GLOBAL_PROGRAM);
     LLVM_READOBJ_ENUM_CASE(ELF, PT_AMDGPU_HSA_LOAD_GLOBAL_AGENT);
for (const Elf_Shdr &Sec : Obj->sections()) {
     StringRef Name = errorOrDefault(Obj->getSectionName(&Sec));
 
     DictScope SectionD(W, "Section");
     W.printNumber("Index", SectionIndex);
     W.printNumber("Name", Name, Sec.sh_name);
     W.printHex("Type",
                getElfSectionType(Obj->getHeader()->e_machine, Sec.sh_type),
                Sec.sh_type);
-    W.printFlags("Flags", Sec.sh_flags, makeArrayRef(ElfSectionFlags));
+    std::vector<EnumEntry<unsigned>> SectionFlags(std::begin(ElfSectionFlags),
+                                                  std::end(ElfSectionFlags));
+    switch (Obj->getHeader()->e_machine) {
+    case EM_AMDGPU:
+      SectionFlags.insert(SectionFlags.end(), std::begin(ElfAMDGPUSectionFlags),
+                          std::end(ElfAMDGPUSectionFlags));
+      break;
+    case EM_HEXAGON:
+      SectionFlags.insert(SectionFlags.end(),
+                          std::begin(ElfHexagonSectionFlags),
+                          std::end(ElfHexagonSectionFlags));
+      break;
+    case EM_MIPS:
+      SectionFlags.insert(SectionFlags.end(), std::begin(ElfMipsSectionFlags),
+                          std::end(ElfMipsSectionFlags));
+      break;
+    case EM_X86_64:
+      SectionFlags.insert(SectionFlags.end(), std::begin(ElfX86_64SectionFlags),
+                          std::end(ElfX86_64SectionFlags));
+      break;
+    default:
+      // Nothing to do.
+      break;
+    }
+    W.printFlags("Flags", Sec.sh_flags, makeArrayRef(SectionFlags));
     W.printHex("Address", Sec.sh_addr);
     W.printHex("Offset", Sec.sh_offset);
     W.printNumber("Size", Sec.sh_size);
     W.printNumber("Link", Sec.sh_link);
     W.printNumber("Info", Sec.sh_info);
     W.printNumber("AddressAlignment", Sec.sh_addralign);
     W.printNumber("EntrySize", Sec.sh_entsize);