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[AArch64] Multiply extended 32-bit ints with `[U|S]MADDL'.
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Authored by chrisdiamand_arm on Jan 14 2016, 9:10 AM.

Details

Summary

During instruction selection, the AArch64 backend can recognise the
following pattern and generate an [U|S]MADDL instruction, i.e. a
multiply of two 32-bit operands with a 64-bit result:

(mul (sext i32), (sext i32))

However, when one of the operands is constant, the sign extension
gets folded into the constant in SelectionDAG::getNode(). This means
that the instruction selection sees this:

(mul (sext i32), i64)

...which doesn't match the pattern. Sign-extension and 64-bit
multiply instructions are generated, which are slower than one 32-bit
multiply.

Add a pattern to match this and generate the correct instruction, for
both signed and unsigned multiplies.

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Event Timeline

chrisdiamand_arm retitled this revision from to [AArch64] Multiply extended 32-bit ints with `[U|S]MADDL'..
chrisdiamand_arm updated this object.
chrisdiamand_arm added a subscriber: llvm-commits.
t.p.northover edited edge metadata.Jan 14 2016, 9:25 AM

It's probably worth adding patterns for the non-XZR case too while we're at it (the basic ones are in AArch64InstrFormats.td around WideMulAccum, but since that's only a class we can't add them there).

chrisdiamand_arm edited edge metadata.

Good point - I've updated the patch to handle those cases.

Thanks!
Chris

Hi,

Did anyone get a chance to look at the updated patch?

Cheers,
Chris

jmolloy accepted this revision.Jan 26 2016, 8:06 AM
jmolloy edited edge metadata.

Hi Chris,

I think this looks good to me.

Cheers,

James

This revision is now accepted and ready to land.Jan 26 2016, 8:06 AM

Thanks James. Tim - do you think this is ready to be merged?

Cheers!
Chris