This is an archive of the discontinued LLVM Phabricator instance.

Differential D15848

Fix several accidental DOS line endings in source files
ClosedPublic

Authored by dim on Jan 3 2016, 3:14 AM.

Details

Reviewers
aaron.ballman
joerg
Commits
rG227b928abce1: Fix several accidental DOS line endings in source files
rL256707: Fix several accidental DOS line endings in source files
Summary

There are a number of files in the tree which have been accidentally checked in with DOS line endings. Convert these to native line endings.

There are also a few files which have DOS line endings on purpose, and I have set the svn:eol-style property to 'CRLF' on those.

Diff Detail

Event Timeline

dim updated this revision to Diff 43856.Jan 3 2016, 3:14 AM
dim retitled this revision from to Fix several accidental DOS line endings in source files.
dim updated this object.
dim added a reviewer: joerg.
dim added a subscriber: llvm-commits.
Herald added subscribers: dsanders, sanjoy. · View Herald TranscriptJan 3 2016, 3:14 AM
aaron.ballman accepted this revision.Jan 3 2016, 9:10 AM
aaron.ballman added a reviewer: aaron.ballman.
aaron.ballman added a subscriber: aaron.ballman.

LGTM, thank you!

This revision is now accepted and ready to land.Jan 3 2016, 9:10 AM
dim closed this revision.Jan 3 2016, 9:25 AM

Revision Contents

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docs/
360 lines
include/
llvm/
DebugInfo/
DWARF/
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lib/
DebugInfo/
CodeView/
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DWARF/
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Target/
X86/
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test/
CodeGen/
AArch64/
54 lines
ARM/
34 lines
X86/
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DebugInfo/
Inputs/
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FileCheck/
JitListener/
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10 lines
MC/
ARM/
14 lines
Disassembler/
Mips/
mips4/
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Hexagon/
6 lines
X86/
14 lines
Object/
Inputs/
Transforms/
EarlyCSE/
AArch64/
36 lines
PlaceSafepoints/
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tools/
llvm-pdbdump/
Inputs/
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llvm-symbolizer/
pdb/
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unittests/
IR/
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Diff 43856

docs/MCJITDesignAndImplementation.rst

=============================== ===============================
MCJIT Design and Implementation MCJIT Design and Implementation
=============================== ===============================
Introduction Introduction
============ ============
This document describes the internal workings of the MCJIT execution This document describes the internal workings of the MCJIT execution
engine and the RuntimeDyld component. It is intended as a high level engine and the RuntimeDyld component. It is intended as a high level
overview of the implementation, showing the flow and interactions of overview of the implementation, showing the flow and interactions of
objects throughout the code generation and dynamic loading process. objects throughout the code generation and dynamic loading process.
Engine Creation Engine Creation
=============== ===============
In most cases, an EngineBuilder object is used to create an instance of In most cases, an EngineBuilder object is used to create an instance of
the MCJIT execution engine. The EngineBuilder takes an llvm::Module the MCJIT execution engine. The EngineBuilder takes an llvm::Module
object as an argument to its constructor. The client may then set various object as an argument to its constructor. The client may then set various
options that we control the later be passed along to the MCJIT engine, options that we control the later be passed along to the MCJIT engine,
including the selection of MCJIT as the engine type to be created. including the selection of MCJIT as the engine type to be created.
Of particular interest is the EngineBuilder::setMCJITMemoryManager Of particular interest is the EngineBuilder::setMCJITMemoryManager
function. If the client does not explicitly create a memory manager at function. If the client does not explicitly create a memory manager at
this time, a default memory manager (specifically SectionMemoryManager) this time, a default memory manager (specifically SectionMemoryManager)
will be created when the MCJIT engine is instantiated. will be created when the MCJIT engine is instantiated.
Once the options have been set, a client calls EngineBuilder::create to Once the options have been set, a client calls EngineBuilder::create to
create an instance of the MCJIT engine. If the client does not use the create an instance of the MCJIT engine. If the client does not use the
form of this function that takes a TargetMachine as a parameter, a new form of this function that takes a TargetMachine as a parameter, a new
TargetMachine will be created based on the target triple associated with TargetMachine will be created based on the target triple associated with
the Module that was used to create the EngineBuilder. the Module that was used to create the EngineBuilder.
.. image:: MCJIT-engine-builder.png .. image:: MCJIT-engine-builder.png
EngineBuilder::create will call the static MCJIT::createJIT function, EngineBuilder::create will call the static MCJIT::createJIT function,
passing in its pointers to the module, memory manager and target machine passing in its pointers to the module, memory manager and target machine
objects, all of which will subsequently be owned by the MCJIT object. objects, all of which will subsequently be owned by the MCJIT object.
The MCJIT class has a member variable, Dyld, which contains an instance of The MCJIT class has a member variable, Dyld, which contains an instance of
the RuntimeDyld wrapper class. This member will be used for the RuntimeDyld wrapper class. This member will be used for
communications between MCJIT and the actual RuntimeDyldImpl object that communications between MCJIT and the actual RuntimeDyldImpl object that
gets created when an object is loaded. gets created when an object is loaded.
.. image:: MCJIT-creation.png .. image:: MCJIT-creation.png
Upon creation, MCJIT holds a pointer to the Module object that it received Upon creation, MCJIT holds a pointer to the Module object that it received
from EngineBuilder but it does not immediately generate code for this from EngineBuilder but it does not immediately generate code for this
module. Code generation is deferred until either the module. Code generation is deferred until either the
MCJIT::finalizeObject method is called explicitly or a function such as MCJIT::finalizeObject method is called explicitly or a function such as
MCJIT::getPointerToFunction is called which requires the code to have been MCJIT::getPointerToFunction is called which requires the code to have been
generated. generated.
Code Generation Code Generation
=============== ===============
When code generation is triggered, as described above, MCJIT will first When code generation is triggered, as described above, MCJIT will first
attempt to retrieve an object image from its ObjectCache member, if one attempt to retrieve an object image from its ObjectCache member, if one
has been set. If a cached object image cannot be retrieved, MCJIT will has been set. If a cached object image cannot be retrieved, MCJIT will
call its emitObject method. MCJIT::emitObject uses a local PassManager call its emitObject method. MCJIT::emitObject uses a local PassManager
instance and creates a new ObjectBufferStream instance, both of which it instance and creates a new ObjectBufferStream instance, both of which it
passes to TargetMachine::addPassesToEmitMC before calling PassManager::run passes to TargetMachine::addPassesToEmitMC before calling PassManager::run
on the Module with which it was created. on the Module with which it was created.
.. image:: MCJIT-load.png .. image:: MCJIT-load.png
The PassManager::run call causes the MC code generation mechanisms to emit The PassManager::run call causes the MC code generation mechanisms to emit
a complete relocatable binary object image (either in either ELF or MachO a complete relocatable binary object image (either in either ELF or MachO
format, depending on the target) into the ObjectBufferStream object, which format, depending on the target) into the ObjectBufferStream object, which
is flushed to complete the process. If an ObjectCache is being used, the is flushed to complete the process. If an ObjectCache is being used, the
image will be passed to the ObjectCache here. image will be passed to the ObjectCache here.
At this point, the ObjectBufferStream contains the raw object image. At this point, the ObjectBufferStream contains the raw object image.
Before the code can be executed, the code and data sections from this Before the code can be executed, the code and data sections from this
image must be loaded into suitable memory, relocations must be applied and image must be loaded into suitable memory, relocations must be applied and
memory permission and code cache invalidation (if required) must be completed. memory permission and code cache invalidation (if required) must be completed.
Object Loading Object Loading
============== ==============
Once an object image has been obtained, either through code generation or Once an object image has been obtained, either through code generation or
having been retrieved from an ObjectCache, it is passed to RuntimeDyld to having been retrieved from an ObjectCache, it is passed to RuntimeDyld to
be loaded. The RuntimeDyld wrapper class examines the object to determine be loaded. The RuntimeDyld wrapper class examines the object to determine
its file format and creates an instance of either RuntimeDyldELF or its file format and creates an instance of either RuntimeDyldELF or
RuntimeDyldMachO (both of which derive from the RuntimeDyldImpl base RuntimeDyldMachO (both of which derive from the RuntimeDyldImpl base
class) and calls the RuntimeDyldImpl::loadObject method to perform that class) and calls the RuntimeDyldImpl::loadObject method to perform that
actual loading. actual loading.
.. image:: MCJIT-dyld-load.png .. image:: MCJIT-dyld-load.png
RuntimeDyldImpl::loadObject begins by creating an ObjectImage instance RuntimeDyldImpl::loadObject begins by creating an ObjectImage instance
from the ObjectBuffer it received. ObjectImage, which wraps the from the ObjectBuffer it received. ObjectImage, which wraps the
ObjectFile class, is a helper class which parses the binary object image ObjectFile class, is a helper class which parses the binary object image
and provides access to the information contained in the format-specific and provides access to the information contained in the format-specific
headers, including section, symbol and relocation information. headers, including section, symbol and relocation information.
RuntimeDyldImpl::loadObject then iterates through the symbols in the RuntimeDyldImpl::loadObject then iterates through the symbols in the
image. Information about common symbols is collected for later use. For image. Information about common symbols is collected for later use. For
each function or data symbol, the associated section is loaded into memory each function or data symbol, the associated section is loaded into memory
and the symbol is stored in a symbol table map data structure. When the and the symbol is stored in a symbol table map data structure. When the
iteration is complete, a section is emitted for the common symbols. iteration is complete, a section is emitted for the common symbols.
Next, RuntimeDyldImpl::loadObject iterates through the sections in the Next, RuntimeDyldImpl::loadObject iterates through the sections in the
object image and for each section iterates through the relocations for object image and for each section iterates through the relocations for
that sections. For each relocation, it calls the format-specific that sections. For each relocation, it calls the format-specific
processRelocationRef method, which will examine the relocation and store processRelocationRef method, which will examine the relocation and store
it in one of two data structures, a section-based relocation list map and it in one of two data structures, a section-based relocation list map and
an external symbol relocation map. an external symbol relocation map.
.. image:: MCJIT-load-object.png .. image:: MCJIT-load-object.png
When RuntimeDyldImpl::loadObject returns, all of the code and data When RuntimeDyldImpl::loadObject returns, all of the code and data
sections for the object will have been loaded into memory allocated by the sections for the object will have been loaded into memory allocated by the
memory manager and relocation information will have been prepared, but the memory manager and relocation information will have been prepared, but the
relocations have not yet been applied and the generated code is still not relocations have not yet been applied and the generated code is still not
ready to be executed. ready to be executed.
[Currently (as of August 2013) the MCJIT engine will immediately apply [Currently (as of August 2013) the MCJIT engine will immediately apply
relocations when loadObject completes. However, this shouldn't be relocations when loadObject completes. However, this shouldn't be
happening. Because the code may have been generated for a remote target, happening. Because the code may have been generated for a remote target,
the client should be given a chance to re-map the section addresses before the client should be given a chance to re-map the section addresses before
relocations are applied. It is possible to apply relocations multiple relocations are applied. It is possible to apply relocations multiple
times, but in the case where addresses are to be re-mapped, this first times, but in the case where addresses are to be re-mapped, this first
application is wasted effort.] application is wasted effort.]
Address Remapping Address Remapping
================= =================
At any time after initial code has been generated and before At any time after initial code has been generated and before
finalizeObject is called, the client can remap the address of sections in finalizeObject is called, the client can remap the address of sections in
the object. Typically this is done because the code was generated for an the object. Typically this is done because the code was generated for an
external process and is being mapped into that process' address space. external process and is being mapped into that process' address space.
The client remaps the section address by calling MCJIT::mapSectionAddress. The client remaps the section address by calling MCJIT::mapSectionAddress.
This should happen before the section memory is copied to its new This should happen before the section memory is copied to its new
location. location.
When MCJIT::mapSectionAddress is called, MCJIT passes the call on to When MCJIT::mapSectionAddress is called, MCJIT passes the call on to
RuntimeDyldImpl (via its Dyld member). RuntimeDyldImpl stores the new RuntimeDyldImpl (via its Dyld member). RuntimeDyldImpl stores the new
address in an internal data structure but does not update the code at this address in an internal data structure but does not update the code at this
time, since other sections are likely to change. time, since other sections are likely to change.
When the client is finished remapping section addresses, it will call When the client is finished remapping section addresses, it will call
MCJIT::finalizeObject to complete the remapping process. MCJIT::finalizeObject to complete the remapping process.
Final Preparations Final Preparations
================== ==================
When MCJIT::finalizeObject is called, MCJIT calls When MCJIT::finalizeObject is called, MCJIT calls
RuntimeDyld::resolveRelocations. This function will attempt to locate any RuntimeDyld::resolveRelocations. This function will attempt to locate any
external symbols and then apply all relocations for the object. external symbols and then apply all relocations for the object.
External symbols are resolved by calling the memory manager's External symbols are resolved by calling the memory manager's
getPointerToNamedFunction method. The memory manager will return the getPointerToNamedFunction method. The memory manager will return the
address of the requested symbol in the target address space. (Note, this address of the requested symbol in the target address space. (Note, this
may not be a valid pointer in the host process.) RuntimeDyld will then may not be a valid pointer in the host process.) RuntimeDyld will then
iterate through the list of relocations it has stored which are associated iterate through the list of relocations it has stored which are associated
with this symbol and invoke the resolveRelocation method which, through an with this symbol and invoke the resolveRelocation method which, through an
format-specific implementation, will apply the relocation to the loaded format-specific implementation, will apply the relocation to the loaded
section memory. section memory.
Next, RuntimeDyld::resolveRelocations iterates through the list of Next, RuntimeDyld::resolveRelocations iterates through the list of
sections and for each section iterates through a list of relocations that sections and for each section iterates through a list of relocations that
have been saved which reference that symbol and call resolveRelocation for have been saved which reference that symbol and call resolveRelocation for
each entry in this list. The relocation list here is a list of each entry in this list. The relocation list here is a list of
relocations for which the symbol associated with the relocation is located relocations for which the symbol associated with the relocation is located
in the section associated with the list. Each of these locations will in the section associated with the list. Each of these locations will
have a target location at which the relocation will be applied that is have a target location at which the relocation will be applied that is
likely located in a different section. likely located in a different section.
.. image:: MCJIT-resolve-relocations.png .. image:: MCJIT-resolve-relocations.png
Once relocations have been applied as described above, MCJIT calls Once relocations have been applied as described above, MCJIT calls
RuntimeDyld::getEHFrameSection, and if a non-zero result is returned RuntimeDyld::getEHFrameSection, and if a non-zero result is returned
passes the section data to the memory manager's registerEHFrames method. passes the section data to the memory manager's registerEHFrames method.
This allows the memory manager to call any desired target-specific This allows the memory manager to call any desired target-specific
functions, such as registering the EH frame information with a debugger. functions, such as registering the EH frame information with a debugger.
Finally, MCJIT calls the memory manager's finalizeMemory method. In this Finally, MCJIT calls the memory manager's finalizeMemory method. In this
method, the memory manager will invalidate the target code cache, if method, the memory manager will invalidate the target code cache, if
necessary, and apply final permissions to the memory pages it has necessary, and apply final permissions to the memory pages it has
allocated for code and data memory. allocated for code and data memory.

include/llvm/DebugInfo/DWARF/DWARFDebugMacro.h

//===-- DWARFDebugMacro.h ---------------------------------------*- C++ -*-===// //===-- DWARFDebugMacro.h ---------------------------------------*- C++ -*-===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#ifndef LLVM_DEBUGINFO_DWARF_DWARFDEBUGMACRO_H #ifndef LLVM_DEBUGINFO_DWARF_DWARFDEBUGMACRO_H
#define LLVM_DEBUGINFO_DWARF_DWARFDEBUGMACRO_H #define LLVM_DEBUGINFO_DWARF_DWARFDEBUGMACRO_H
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
#include "llvm/Support/DataExtractor.h" #include "llvm/Support/DataExtractor.h"
#include "llvm/Support/Dwarf.h" #include "llvm/Support/Dwarf.h"
namespace llvm { namespace llvm {
class raw_ostream; class raw_ostream;
class DWARFDebugMacro { class DWARFDebugMacro {
/// A single macro entry within a macro list. /// A single macro entry within a macro list.
struct Entry { struct Entry {
/// The type of the macro entry. /// The type of the macro entry.
uint32_t Type; uint32_t Type;
union { union {
/// The source line where the macro is defined. /// The source line where the macro is defined.
uint64_t Line; uint64_t Line;
/// Vendor extension constant value. /// Vendor extension constant value.
uint64_t ExtConstant; uint64_t ExtConstant;
}; };
union { union {
/// The string (name, value) of the macro entry. /// The string (name, value) of the macro entry.
const char *MacroStr; const char *MacroStr;
// An unsigned integer indicating the identity of the source file. // An unsigned integer indicating the identity of the source file.
uint64_t File; uint64_t File;
/// Vendor extension string. /// Vendor extension string.
const char *ExtStr; const char *ExtStr;
}; };
}; };
typedef SmallVector<Entry, 4> MacroList; typedef SmallVector<Entry, 4> MacroList;
/// A list of all the macro entries in the debug_macinfo section. /// A list of all the macro entries in the debug_macinfo section.
MacroList Macros; MacroList Macros;
public: public:
DWARFDebugMacro() {} DWARFDebugMacro() {}
/// Print the macro list found within the debug_macinfo section. /// Print the macro list found within the debug_macinfo section.
void dump(raw_ostream &OS) const; void dump(raw_ostream &OS) const;
/// Parse the debug_macinfo section accessible via the 'data' parameter. /// Parse the debug_macinfo section accessible via the 'data' parameter.
void parse(DataExtractor data); void parse(DataExtractor data);
}; };
} }
#endif #endif

lib/DebugInfo/CodeView/Makefile

##===- lib/DebugInfo/CodeView/Makefile ---------------------*- Makefile -*-===## ##===- lib/DebugInfo/CodeView/Makefile ---------------------*- Makefile -*-===##
# #
# The LLVM Compiler Infrastructure # The LLVM Compiler Infrastructure
# #
# This file is distributed under the University of Illinois Open Source # This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details. # License. See LICENSE.TXT for details.
# #
##===----------------------------------------------------------------------===## ##===----------------------------------------------------------------------===##
LEVEL = ../../.. LEVEL = ../../..
LIBRARYNAME = LLVMDebugInfoCodeView LIBRARYNAME = LLVMDebugInfoCodeView
BUILD_ARCHIVE := 1 BUILD_ARCHIVE := 1
include $(LEVEL)/Makefile.common include $(LEVEL)/Makefile.common

lib/DebugInfo/DWARF/DWARFDebugMacro.cpp

//===-- DWARFDebugMacro.cpp -----------------------------------------------===// //===-- DWARFDebugMacro.cpp -----------------------------------------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "SyntaxHighlighting.h" #include "SyntaxHighlighting.h"
#include "llvm/DebugInfo/DWARF/DWARFDebugMacro.h" #include "llvm/DebugInfo/DWARF/DWARFDebugMacro.h"
#include "llvm/Support/Compiler.h" #include "llvm/Support/Compiler.h"
#include "llvm/Support/Dwarf.h" #include "llvm/Support/Dwarf.h"
#include "llvm/Support/Format.h" #include "llvm/Support/Format.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
using namespace llvm; using namespace llvm;
using namespace dwarf; using namespace dwarf;
using namespace syntax; using namespace syntax;
void DWARFDebugMacro::dump(raw_ostream &OS) const { void DWARFDebugMacro::dump(raw_ostream &OS) const {
unsigned IndLevel = 0; unsigned IndLevel = 0;
for (const Entry &E : Macros) { for (const Entry &E : Macros) {
// There should not be DW_MACINFO_end_file when IndLevel is Zero. However, // There should not be DW_MACINFO_end_file when IndLevel is Zero. However,
// this check handles the case of corrupted ".debug_macinfo" section. // this check handles the case of corrupted ".debug_macinfo" section.
if (IndLevel > 0) if (IndLevel > 0)
IndLevel -= (E.Type == DW_MACINFO_end_file); IndLevel -= (E.Type == DW_MACINFO_end_file);
// Print indentation. // Print indentation.
for (unsigned I = 0; I < IndLevel; I++) for (unsigned I = 0; I < IndLevel; I++)
OS << " "; OS << " ";
IndLevel += (E.Type == DW_MACINFO_start_file); IndLevel += (E.Type == DW_MACINFO_start_file);
WithColor(OS, syntax::Macro).get() << MacinfoString(E.Type); WithColor(OS, syntax::Macro).get() << MacinfoString(E.Type);
switch (E.Type) { switch (E.Type) {
default: default:
// Got a corrupted ".debug_macinfo" section (invalid macinfo type). // Got a corrupted ".debug_macinfo" section (invalid macinfo type).
break; break;
case DW_MACINFO_define: case DW_MACINFO_define:
case DW_MACINFO_undef: case DW_MACINFO_undef:
OS << " - lineno: " << E.Line; OS << " - lineno: " << E.Line;
OS << " macro: " << E.MacroStr; OS << " macro: " << E.MacroStr;
break; break;
case DW_MACINFO_start_file: case DW_MACINFO_start_file:
OS << " - lineno: " << E.Line; OS << " - lineno: " << E.Line;
OS << " filenum: " << E.File; OS << " filenum: " << E.File;
break; break;
case DW_MACINFO_end_file: case DW_MACINFO_end_file:
break; break;
case DW_MACINFO_vendor_ext: case DW_MACINFO_vendor_ext:
OS << " - constant: " << E.ExtConstant; OS << " - constant: " << E.ExtConstant;
OS << " string: " << E.ExtStr; OS << " string: " << E.ExtStr;
break; break;
} }
OS << "\n"; OS << "\n";
} }
} }
void DWARFDebugMacro::parse(DataExtractor data) { void DWARFDebugMacro::parse(DataExtractor data) {
uint32_t Offset = 0; uint32_t Offset = 0;
while (data.isValidOffset(Offset)) { while (data.isValidOffset(Offset)) {
// A macro list entry consists of: // A macro list entry consists of:
Entry E; Entry E;
// 1. Macinfo type // 1. Macinfo type
E.Type = data.getULEB128(&Offset); E.Type = data.getULEB128(&Offset);
if (E.Type == 0) { if (E.Type == 0) {
// Reached end of ".debug_macinfo" section. // Reached end of ".debug_macinfo" section.
return; return;
} }
switch (E.Type) { switch (E.Type) {
default: default:
// Got a corrupted ".debug_macinfo" section (invalid macinfo type). // Got a corrupted ".debug_macinfo" section (invalid macinfo type).
// Push the corrupted entry to the list and halt parsing. // Push the corrupted entry to the list and halt parsing.
E.Type = DW_MACINFO_invalid; E.Type = DW_MACINFO_invalid;
Macros.push_back(E); Macros.push_back(E);
return; return;
case DW_MACINFO_define: case DW_MACINFO_define:
case DW_MACINFO_undef: case DW_MACINFO_undef:
// 2. Source line // 2. Source line
E.Line = data.getULEB128(&Offset); E.Line = data.getULEB128(&Offset);
// 3. Macro string // 3. Macro string
E.MacroStr = data.getCStr(&Offset); E.MacroStr = data.getCStr(&Offset);
break; break;
case DW_MACINFO_start_file: case DW_MACINFO_start_file:
// 2. Source line // 2. Source line
E.Line = data.getULEB128(&Offset); E.Line = data.getULEB128(&Offset);
// 3. Source file id // 3. Source file id
E.File = data.getULEB128(&Offset); E.File = data.getULEB128(&Offset);
break; break;
case DW_MACINFO_end_file: case DW_MACINFO_end_file:
break; break;
case DW_MACINFO_vendor_ext: case DW_MACINFO_vendor_ext:
// 2. Vendor extension constant // 2. Vendor extension constant
E.ExtConstant = data.getULEB128(&Offset); E.ExtConstant = data.getULEB128(&Offset);
// 3. Vendor extension string // 3. Vendor extension string
E.ExtStr = data.getCStr(&Offset); E.ExtStr = data.getCStr(&Offset);
break; break;
} }
Macros.push_back(E); Macros.push_back(E);
} }
} }

lib/Target/X86/X86FastISel.cpp

Show First 20 Lines • Show All 1,092 Lines • ▼ Show 20 Lines if (!SrcRC->contains(DstReg))
return false; return false;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg); TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
// Add register to return instruction. // Add register to return instruction.
RetRegs.push_back(VA.getLocReg()); RetRegs.push_back(VA.getLocReg());
} }
// All x86 ABIs require that for returning structs by value we copy // All x86 ABIs require that for returning structs by value we copy
// the sret argument into %rax/%eax (depending on ABI) for the return. // the sret argument into %rax/%eax (depending on ABI) for the return.
// We saved the argument into a virtual register in the entry block, // We saved the argument into a virtual register in the entry block,
// so now we copy the value out and into %rax/%eax. // so now we copy the value out and into %rax/%eax.
if (F.hasStructRetAttr()) { if (F.hasStructRetAttr()) {
unsigned Reg = X86MFInfo->getSRetReturnReg(); unsigned Reg = X86MFInfo->getSRetReturnReg();
assert(Reg && assert(Reg &&
"SRetReturnReg should have been set in LowerFormalArguments()!"); "SRetReturnReg should have been set in LowerFormalArguments()!");
unsigned RetReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; unsigned RetReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::COPY), RetReg).addReg(Reg); TII.get(TargetOpcode::COPY), RetReg).addReg(Reg);
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test/CodeGen/AArch64/arm64-vector-ext.ll

; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
;CHECK: @func30 ;CHECK: @func30
;CHECK: movi.4h v1, #0x1 ;CHECK: movi.4h v1, #0x1
;CHECK: and.8b v0, v0, v1 ;CHECK: and.8b v0, v0, v1
;CHECK: ushll.4s v0, v0, #0 ;CHECK: ushll.4s v0, v0, #0
;CHECK: str q0, [x0] ;CHECK: str q0, [x0]
;CHECK: ret ;CHECK: ret
%T0_30 = type <4 x i1> %T0_30 = type <4 x i1>
%T1_30 = type <4 x i32> %T1_30 = type <4 x i32>
define void @func30(%T0_30 %v0, %T1_30* %p1) { define void @func30(%T0_30 %v0, %T1_30* %p1) {
%r = zext %T0_30 %v0 to %T1_30 %r = zext %T0_30 %v0 to %T1_30
store %T1_30 %r, %T1_30* %p1 store %T1_30 %r, %T1_30* %p1
ret void ret void
} }
; Extend from v1i1 was crashing things (PR20791). Make sure we do something ; Extend from v1i1 was crashing things (PR20791). Make sure we do something
; sensible instead. ; sensible instead.
define <1 x i32> @autogen_SD7918() { define <1 x i32> @autogen_SD7918() {
; CHECK-LABEL: autogen_SD7918 ; CHECK-LABEL: autogen_SD7918
; CHECK: movi d0, #0000000000000000 ; CHECK: movi d0, #0000000000000000
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%I29 = insertelement <1 x i1> zeroinitializer, i1 false, i32 0 %I29 = insertelement <1 x i1> zeroinitializer, i1 false, i32 0
%ZE = zext <1 x i1> %I29 to <1 x i32> %ZE = zext <1 x i1> %I29 to <1 x i32>
ret <1 x i32> %ZE ret <1 x i32> %ZE
} }

test/CodeGen/ARM/debugtrap.ll

; This test ensures the @llvm.debugtrap() call is not removed when generating ; This test ensures the @llvm.debugtrap() call is not removed when generating
; the 'pop' instruction to restore the callee saved registers on ARM. ; the 'pop' instruction to restore the callee saved registers on ARM.
; RUN: llc < %s -mtriple=armv7 -O0 -filetype=asm | FileCheck %s ; RUN: llc < %s -mtriple=armv7 -O0 -filetype=asm | FileCheck %s
declare void @llvm.debugtrap() nounwind declare void @llvm.debugtrap() nounwind
declare void @foo() nounwind declare void @foo() nounwind
define void @test() nounwind { define void @test() nounwind {
entry: entry:
; CHECK: bl foo ; CHECK: bl foo
; CHECK-NEXT: pop ; CHECK-NEXT: pop
; CHECK-NEXT: trap ; CHECK-NEXT: trap
call void @foo() call void @foo()
call void @llvm.debugtrap() call void @llvm.debugtrap()
ret void ret void
} }

test/CodeGen/X86/2011-11-30-or.ll

; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s ; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
target triple = "x86_64-apple-macosx10.6.6" target triple = "x86_64-apple-macosx10.6.6"
; Test that the order of operands is correct ; Test that the order of operands is correct
; CHECK: select_func ; CHECK: select_func
; CHECK: pblendvb {{LCPI0_[0-9]*}}(%rip), %xmm1 ; CHECK: pblendvb {{LCPI0_[0-9]*}}(%rip), %xmm1
; CHECK: ret ; CHECK: ret
define void @select_func(<8 x i16> %in) { define void @select_func(<8 x i16> %in) {
entry: entry:
%c.lobit.i.i.i = ashr <8 x i16> %in, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> %c.lobit.i.i.i = ashr <8 x i16> %in, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
%and.i56.i.i.i = and <8 x i16> %c.lobit.i.i.i, <i16 25, i16 8, i16 65, i16 25, i16 8, i16 95, i16 15, i16 45> %and.i56.i.i.i = and <8 x i16> %c.lobit.i.i.i, <i16 25, i16 8, i16 65, i16 25, i16 8, i16 95, i16 15, i16 45>
%and.i5.i.i.i = bitcast <8 x i16> %and.i56.i.i.i to <2 x i64> %and.i5.i.i.i = bitcast <8 x i16> %and.i56.i.i.i to <2 x i64>
%neg.i.i.i.i = xor <8 x i16> %c.lobit.i.i.i, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> %neg.i.i.i.i = xor <8 x i16> %c.lobit.i.i.i, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
%and.i.i.i = and <8 x i16> %neg.i.i.i.i, <i16 45, i16 15, i16 95, i16 8, i16 25, i16 65, i16 8, i16 25> %and.i.i.i = and <8 x i16> %neg.i.i.i.i, <i16 45, i16 15, i16 95, i16 8, i16 25, i16 65, i16 8, i16 25>
%and.i2.i.i.i = bitcast <8 x i16> %and.i.i.i to <2 x i64> %and.i2.i.i.i = bitcast <8 x i16> %and.i.i.i to <2 x i64>
%or.i.i.i.i = or <2 x i64> %and.i2.i.i.i, %and.i5.i.i.i %or.i.i.i.i = or <2 x i64> %and.i2.i.i.i, %and.i5.i.i.i
%a37 = bitcast <2 x i64> %or.i.i.i.i to <8 x i16> %a37 = bitcast <2 x i64> %or.i.i.i.i to <8 x i16>
store <8 x i16> %a37, <8 x i16> addrspace(1)* undef, align 4 store <8 x i16> %a37, <8 x i16> addrspace(1)* undef, align 4
ret void ret void
} }

test/CodeGen/X86/avx512cd-intrinsics.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512cd | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512cd | FileCheck %s
define <16 x i32> @test_x86_vbroadcastmw_512(i16 %a0) { define <16 x i32> @test_x86_vbroadcastmw_512(i16 %a0) {
; CHECK: test_x86_vbroadcastmw_512 ; CHECK: test_x86_vbroadcastmw_512
; CHECK: vpbroadcastmw2d %k0, %zmm0 ; CHECK: vpbroadcastmw2d %k0, %zmm0
%res = call <16 x i32> @llvm.x86.avx512.broadcastmw.512(i16 %a0) ; %res = call <16 x i32> @llvm.x86.avx512.broadcastmw.512(i16 %a0) ;
ret <16 x i32> %res ret <16 x i32> %res
} }
declare <16 x i32> @llvm.x86.avx512.broadcastmw.512(i16) declare <16 x i32> @llvm.x86.avx512.broadcastmw.512(i16)
define <8 x i64> @test_x86_broadcastmb_512(i8 %a0) { define <8 x i64> @test_x86_broadcastmb_512(i8 %a0) {
; CHECK: test_x86_broadcastmb_512 ; CHECK: test_x86_broadcastmb_512
; CHECK: vpbroadcastmb2q %k0, %zmm0 ; CHECK: vpbroadcastmb2q %k0, %zmm0
%res = call <8 x i64> @llvm.x86.avx512.broadcastmb.512(i8 %a0) ; %res = call <8 x i64> @llvm.x86.avx512.broadcastmb.512(i8 %a0) ;
ret <8 x i64> %res ret <8 x i64> %res
} }
declare <8 x i64> @llvm.x86.avx512.broadcastmb.512(i8) declare <8 x i64> @llvm.x86.avx512.broadcastmb.512(i8)

test/CodeGen/X86/fpcmp-soft-fp.ll

; RUN: llc < %s -march=x86 -mcpu=pentium -mtriple=x86-linux-gnu -float-abi=soft | FileCheck %s ; RUN: llc < %s -march=x86 -mcpu=pentium -mtriple=x86-linux-gnu -float-abi=soft | FileCheck %s
define i1 @test1(double %d) #0 { define i1 @test1(double %d) #0 {
entry: entry:
%cmp = fcmp ule double %d, 0.000000e+00 %cmp = fcmp ule double %d, 0.000000e+00
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: calll __gtdf2 ; CHECK: calll __gtdf2
; CHECK: setle ; CHECK: setle
; CHECK: retl ; CHECK: retl
define i1 @test2(double %d) #0 { define i1 @test2(double %d) #0 {
entry: entry:
%cmp = fcmp ult double %d, 0.000000e+00 %cmp = fcmp ult double %d, 0.000000e+00
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: calll __gedf2 ; CHECK: calll __gedf2
; CHECK: sets ; CHECK: sets
; CHECK: retl ; CHECK: retl
define i1 @test3(double %d) #0 { define i1 @test3(double %d) #0 {
entry: entry:
%cmp = fcmp ugt double %d, 0.000000e+00 %cmp = fcmp ugt double %d, 0.000000e+00
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: calll __ledf2 ; CHECK: calll __ledf2
; CHECK: setg ; CHECK: setg
; CHECK: retl ; CHECK: retl
define i1 @test4(double %d) #0 { define i1 @test4(double %d) #0 {
entry: entry:
%cmp = fcmp uge double %d, 0.000000e+00 %cmp = fcmp uge double %d, 0.000000e+00
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: test4: ; CHECK-LABEL: test4:
; CHECK: calll __ltdf2 ; CHECK: calll __ltdf2
; CHECK: setns ; CHECK: setns
; CHECK: retl ; CHECK: retl
define i1 @test5(double %d) #0 { define i1 @test5(double %d) #0 {
entry: entry:
%cmp = fcmp ole double %d, 0.000000e+00 %cmp = fcmp ole double %d, 0.000000e+00
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: test5: ; CHECK-LABEL: test5:
; CHECK: calll __ledf2 ; CHECK: calll __ledf2
; CHECK: setle ; CHECK: setle
; CHECK: retl ; CHECK: retl
define i1 @test6(double %d) #0 { define i1 @test6(double %d) #0 {
entry: entry:
%cmp = fcmp olt double %d, 0.000000e+00 %cmp = fcmp olt double %d, 0.000000e+00
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: test6: ; CHECK-LABEL: test6:
; CHECK: calll __ltdf2 ; CHECK: calll __ltdf2
; CHECK: sets ; CHECK: sets
; CHECK: retl ; CHECK: retl
define i1 @test7(double %d) #0 { define i1 @test7(double %d) #0 {
entry: entry:
%cmp = fcmp ogt double %d, 0.000000e+00 %cmp = fcmp ogt double %d, 0.000000e+00
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: test7: ; CHECK-LABEL: test7:
; CHECK: calll __gtdf2 ; CHECK: calll __gtdf2
; CHECK: setg ; CHECK: setg
; CHECK: retl ; CHECK: retl
define i1 @test8(double %d) #0 { define i1 @test8(double %d) #0 {
entry: entry:
%cmp = fcmp oge double %d, 0.000000e+00 %cmp = fcmp oge double %d, 0.000000e+00
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: test8: ; CHECK-LABEL: test8:
; CHECK: calll __gedf2 ; CHECK: calll __gedf2
; CHECK: setns ; CHECK: setns
; CHECK: retl ; CHECK: retl
define i1 @test9(double %d) #0 { define i1 @test9(double %d) #0 {
entry: entry:
%cmp = fcmp oeq double %d, 0.000000e+00 %cmp = fcmp oeq double %d, 0.000000e+00
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: test9: ; CHECK-LABEL: test9:
; CHECK: calll __eqdf2 ; CHECK: calll __eqdf2
; CHECK: sete ; CHECK: sete
; CHECK: retl ; CHECK: retl
define i1 @test10(double %d) #0 { define i1 @test10(double %d) #0 {
entry: entry:
%cmp = fcmp ueq double %d, 0.000000e+00 %cmp = fcmp ueq double %d, 0.000000e+00
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: test10: ; CHECK-LABEL: test10:
; CHECK: calll __eqdf2 ; CHECK: calll __eqdf2
; CHECK: sete ; CHECK: sete
; CHECK: calll __unorddf2 ; CHECK: calll __unorddf2
; CHECK: setne ; CHECK: setne
; CHECK: retl ; CHECK: retl
define i1 @test11(double %d) #0 { define i1 @test11(double %d) #0 {
entry: entry:
%cmp = fcmp one double %d, 0.000000e+00 %cmp = fcmp one double %d, 0.000000e+00
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: test11: ; CHECK-LABEL: test11:
; CHECK: calll __gtdf2 ; CHECK: calll __gtdf2
; CHECK: setg ; CHECK: setg
; CHECK: calll __ltdf2 ; CHECK: calll __ltdf2
; CHECK: sets ; CHECK: sets
; CHECK: retl ; CHECK: retl
define i1 @test12(double %d) #0 { define i1 @test12(double %d) #0 {
entry: entry:
%cmp = fcmp une double %d, 0.000000e+00 %cmp = fcmp une double %d, 0.000000e+00
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: test12: ; CHECK-LABEL: test12:
; CHECK: calll __nedf2 ; CHECK: calll __nedf2
; CHECK: setne ; CHECK: setne
; CHECK: retl ; CHECK: retl
attributes #0 = { "use-soft-float"="true" } attributes #0 = { "use-soft-float"="true" }

test/CodeGen/X86/pku.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s
declare i32 @llvm.x86.rdpkru() declare i32 @llvm.x86.rdpkru()
declare void @llvm.x86.wrpkru(i32) declare void @llvm.x86.wrpkru(i32)
define void @test_x86_wrpkru(i32 %src) { define void @test_x86_wrpkru(i32 %src) {
; CHECK-LABEL: test_x86_wrpkru: ; CHECK-LABEL: test_x86_wrpkru:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: wrpkru ; CHECK-NEXT: wrpkru
; CHECK-NEXT: retq ; CHECK-NEXT: retq
call void @llvm.x86.wrpkru(i32 %src) call void @llvm.x86.wrpkru(i32 %src)
ret void ret void
} }
define i32 @test_x86_rdpkru() { define i32 @test_x86_rdpkru() {
; CHECK-LABEL: test_x86_rdpkru: ; CHECK-LABEL: test_x86_rdpkru:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: xorl %ecx, %ecx ; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: rdpkru ; CHECK-NEXT: rdpkru
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%res = call i32 @llvm.x86.rdpkru() %res = call i32 @llvm.x86.rdpkru()
ret i32 %res ret i32 %res
} }

test/CodeGen/X86/pr21792.ll

; RUN: llc -mtriple=x86_64-linux -mcpu=corei7 < %s | FileCheck %s ; RUN: llc -mtriple=x86_64-linux -mcpu=corei7 < %s | FileCheck %s
; This fixes a missing cases in the MI scheduler's constrainLocalCopy exposed by ; This fixes a missing cases in the MI scheduler's constrainLocalCopy exposed by
; PR21792 ; PR21792
@stuff = external constant [256 x double], align 16 @stuff = external constant [256 x double], align 16
define void @func(<4 x float> %vx) { define void @func(<4 x float> %vx) {
entry: entry:
%tmp2 = bitcast <4 x float> %vx to <2 x i64> %tmp2 = bitcast <4 x float> %vx to <2 x i64>
%and.i = and <2 x i64> %tmp2, <i64 8727373547504, i64 8727373547504> %and.i = and <2 x i64> %tmp2, <i64 8727373547504, i64 8727373547504>
%tmp3 = bitcast <2 x i64> %and.i to <4 x i32> %tmp3 = bitcast <2 x i64> %and.i to <4 x i32>
%index.sroa.0.0.vec.extract = extractelement <4 x i32> %tmp3, i32 0 %index.sroa.0.0.vec.extract = extractelement <4 x i32> %tmp3, i32 0
%idx.ext = sext i32 %index.sroa.0.0.vec.extract to i64 %idx.ext = sext i32 %index.sroa.0.0.vec.extract to i64
%add.ptr = getelementptr inbounds i8, i8* bitcast ([256 x double]* @stuff to i8*), i64 %idx.ext %add.ptr = getelementptr inbounds i8, i8* bitcast ([256 x double]* @stuff to i8*), i64 %idx.ext
%tmp4 = bitcast i8* %add.ptr to double* %tmp4 = bitcast i8* %add.ptr to double*
%index.sroa.0.4.vec.extract = extractelement <4 x i32> %tmp3, i32 1 %index.sroa.0.4.vec.extract = extractelement <4 x i32> %tmp3, i32 1
%idx.ext5 = sext i32 %index.sroa.0.4.vec.extract to i64 %idx.ext5 = sext i32 %index.sroa.0.4.vec.extract to i64
%add.ptr6 = getelementptr inbounds i8, i8* bitcast ([256 x double]* @stuff to i8*), i64 %idx.ext5 %add.ptr6 = getelementptr inbounds i8, i8* bitcast ([256 x double]* @stuff to i8*), i64 %idx.ext5
%tmp5 = bitcast i8* %add.ptr6 to double* %tmp5 = bitcast i8* %add.ptr6 to double*
%index.sroa.0.8.vec.extract = extractelement <4 x i32> %tmp3, i32 2 %index.sroa.0.8.vec.extract = extractelement <4 x i32> %tmp3, i32 2
%idx.ext14 = sext i32 %index.sroa.0.8.vec.extract to i64 %idx.ext14 = sext i32 %index.sroa.0.8.vec.extract to i64
%add.ptr15 = getelementptr inbounds i8, i8* bitcast ([256 x double]* @stuff to i8*), i64 %idx.ext14 %add.ptr15 = getelementptr inbounds i8, i8* bitcast ([256 x double]* @stuff to i8*), i64 %idx.ext14
%tmp6 = bitcast i8* %add.ptr15 to double* %tmp6 = bitcast i8* %add.ptr15 to double*
%index.sroa.0.12.vec.extract = extractelement <4 x i32> %tmp3, i32 3 %index.sroa.0.12.vec.extract = extractelement <4 x i32> %tmp3, i32 3
%idx.ext19 = sext i32 %index.sroa.0.12.vec.extract to i64 %idx.ext19 = sext i32 %index.sroa.0.12.vec.extract to i64
%add.ptr20 = getelementptr inbounds i8, i8* bitcast ([256 x double]* @stuff to i8*), i64 %idx.ext19 %add.ptr20 = getelementptr inbounds i8, i8* bitcast ([256 x double]* @stuff to i8*), i64 %idx.ext19
%tmp7 = bitcast i8* %add.ptr20 to double* %tmp7 = bitcast i8* %add.ptr20 to double*
%add.ptr46 = getelementptr inbounds i8, i8* bitcast (double* getelementptr inbounds ([256 x double], [256 x double]* @stuff, i64 0, i64 1) to i8*), i64 %idx.ext %add.ptr46 = getelementptr inbounds i8, i8* bitcast (double* getelementptr inbounds ([256 x double], [256 x double]* @stuff, i64 0, i64 1) to i8*), i64 %idx.ext
%tmp16 = bitcast i8* %add.ptr46 to double* %tmp16 = bitcast i8* %add.ptr46 to double*
%add.ptr51 = getelementptr inbounds i8, i8* bitcast (double* getelementptr inbounds ([256 x double], [256 x double]* @stuff, i64 0, i64 1) to i8*), i64 %idx.ext5 %add.ptr51 = getelementptr inbounds i8, i8* bitcast (double* getelementptr inbounds ([256 x double], [256 x double]* @stuff, i64 0, i64 1) to i8*), i64 %idx.ext5
%tmp17 = bitcast i8* %add.ptr51 to double* %tmp17 = bitcast i8* %add.ptr51 to double*
call void @toto(double* %tmp4, double* %tmp5, double* %tmp6, double* %tmp7, double* %tmp16, double* %tmp17) call void @toto(double* %tmp4, double* %tmp5, double* %tmp6, double* %tmp7, double* %tmp16, double* %tmp17)
ret void ret void
; CHECK-LABEL: func: ; CHECK-LABEL: func:
; CHECK: pextrq $1, %xmm0, ; CHECK: pextrq $1, %xmm0,
; CHECK-NEXT: movd %xmm0, %r[[AX:..]] ; CHECK-NEXT: movd %xmm0, %r[[AX:..]]
; CHECK-NEXT: movslq %e[[AX]], ; CHECK-NEXT: movslq %e[[AX]],
; CHECK-NEXT: sarq $32, %r[[AX]] ; CHECK-NEXT: sarq $32, %r[[AX]]
} }
declare void @toto(double*, double*, double*, double*, double*, double*) declare void @toto(double*, double*, double*, double*, double*, double*)

test/CodeGen/X86/pr24139.ll

; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
; Check that we do not get excessive spilling from splitting of constant live ranges. ; Check that we do not get excessive spilling from splitting of constant live ranges.
; CHECK-LABEL: PR24139: ; CHECK-LABEL: PR24139:
; CHECK: # 16-byte Spill ; CHECK: # 16-byte Spill
; CHECK-NOT: # 16-byte Spill ; CHECK-NOT: # 16-byte Spill
; CHECK: retq ; CHECK: retq
define <2 x double> @PR24139(<2 x double> %arg, <2 x double> %arg1, <2 x double> %arg2) { define <2 x double> @PR24139(<2 x double> %arg, <2 x double> %arg1, <2 x double> %arg2) {
%tmp = bitcast <2 x double> %arg to <4 x float> %tmp = bitcast <2 x double> %arg to <4 x float>
%tmp3 = fmul <4 x float> %tmp, <float 0x3FE45F3060000000, float 0x3FE45F3060000000, float 0x3FE45F3060000000, float 0x3FE45F3060000000> %tmp3 = fmul <4 x float> %tmp, <float 0x3FE45F3060000000, float 0x3FE45F3060000000, float 0x3FE45F3060000000, float 0x3FE45F3060000000>
%tmp4 = bitcast <2 x double> %arg to <4 x i32> %tmp4 = bitcast <2 x double> %arg to <4 x i32>
%tmp5 = and <4 x i32> %tmp4, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> %tmp5 = and <4 x i32> %tmp4, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
%tmp6 = or <4 x i32> %tmp5, <i32 1056964608, i32 1056964608, i32 1056964608, i32 1056964608> %tmp6 = or <4 x i32> %tmp5, <i32 1056964608, i32 1056964608, i32 1056964608, i32 1056964608>
%tmp7 = bitcast <4 x i32> %tmp6 to <4 x float> %tmp7 = bitcast <4 x i32> %tmp6 to <4 x float>
%tmp8 = fadd <4 x float> %tmp3, %tmp7 %tmp8 = fadd <4 x float> %tmp3, %tmp7
%tmp9 = tail call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %tmp8) #2 %tmp9 = tail call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %tmp8) #2
%tmp10 = bitcast <4 x i32> %tmp9 to <2 x i64> %tmp10 = bitcast <4 x i32> %tmp9 to <2 x i64>
%tmp11 = tail call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %tmp9) #2 %tmp11 = tail call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %tmp9) #2
%tmp12 = fmul <4 x float> %tmp11, <float 0x3FF921FB40000000, float 0x3FF921FB40000000, float 0x3FF921FB40000000, float 0x3FF921FB40000000> %tmp12 = fmul <4 x float> %tmp11, <float 0x3FF921FB40000000, float 0x3FF921FB40000000, float 0x3FF921FB40000000, float 0x3FF921FB40000000>
%tmp13 = fsub <4 x float> %tmp, %tmp12 %tmp13 = fsub <4 x float> %tmp, %tmp12
%tmp14 = fmul <4 x float> %tmp11, <float 0x3E74442D00000000, float 0x3E74442D00000000, float 0x3E74442D00000000, float 0x3E74442D00000000> %tmp14 = fmul <4 x float> %tmp11, <float 0x3E74442D00000000, float 0x3E74442D00000000, float 0x3E74442D00000000, float 0x3E74442D00000000>
%tmp15 = fsub <4 x float> %tmp13, %tmp14 %tmp15 = fsub <4 x float> %tmp13, %tmp14
%tmp16 = fmul <4 x float> %tmp15, %tmp15 %tmp16 = fmul <4 x float> %tmp15, %tmp15
%tmp17 = fmul <4 x float> %tmp15, %tmp16 %tmp17 = fmul <4 x float> %tmp15, %tmp16
%tmp18 = fmul <4 x float> %tmp16, <float 0xBF56493260000000, float 0xBF56493260000000, float 0xBF56493260000000, float 0xBF56493260000000> %tmp18 = fmul <4 x float> %tmp16, <float 0xBF56493260000000, float 0xBF56493260000000, float 0xBF56493260000000, float 0xBF56493260000000>
%tmp19 = fadd <4 x float> %tmp18, <float 0x3FA55406C0000000, float 0x3FA55406C0000000, float 0x3FA55406C0000000, float 0x3FA55406C0000000> %tmp19 = fadd <4 x float> %tmp18, <float 0x3FA55406C0000000, float 0x3FA55406C0000000, float 0x3FA55406C0000000, float 0x3FA55406C0000000>
%tmp20 = fmul <4 x float> %tmp16, <float 0xBF29918DC0000000, float 0xBF29918DC0000000, float 0xBF29918DC0000000, float 0xBF29918DC0000000> %tmp20 = fmul <4 x float> %tmp16, <float 0xBF29918DC0000000, float 0xBF29918DC0000000, float 0xBF29918DC0000000, float 0xBF29918DC0000000>
%tmp21 = fadd <4 x float> %tmp20, <float 0x3F81106840000000, float 0x3F81106840000000, float 0x3F81106840000000, float 0x3F81106840000000> %tmp21 = fadd <4 x float> %tmp20, <float 0x3F81106840000000, float 0x3F81106840000000, float 0x3F81106840000000, float 0x3F81106840000000>
%tmp22 = fmul <4 x float> %tmp16, %tmp19 %tmp22 = fmul <4 x float> %tmp16, %tmp19
%tmp23 = fadd <4 x float> %tmp22, <float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000> %tmp23 = fadd <4 x float> %tmp22, <float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000>
%tmp24 = fmul <4 x float> %tmp16, %tmp21 %tmp24 = fmul <4 x float> %tmp16, %tmp21
%tmp25 = fadd <4 x float> %tmp24, <float 0xBFC5555420000000, float 0xBFC5555420000000, float 0xBFC5555420000000, float 0xBFC5555420000000> %tmp25 = fadd <4 x float> %tmp24, <float 0xBFC5555420000000, float 0xBFC5555420000000, float 0xBFC5555420000000, float 0xBFC5555420000000>
%tmp26 = fmul <4 x float> %tmp16, %tmp23 %tmp26 = fmul <4 x float> %tmp16, %tmp23
%tmp27 = fadd <4 x float> %tmp26, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> %tmp27 = fadd <4 x float> %tmp26, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
%tmp28 = fmul <4 x float> %tmp17, %tmp25 %tmp28 = fmul <4 x float> %tmp17, %tmp25
%tmp29 = fadd <4 x float> %tmp15, %tmp28 %tmp29 = fadd <4 x float> %tmp15, %tmp28
%tmp30 = and <2 x i64> %tmp10, <i64 4294967297, i64 4294967297> %tmp30 = and <2 x i64> %tmp10, <i64 4294967297, i64 4294967297>
%tmp31 = bitcast <2 x i64> %tmp30 to <4 x i32> %tmp31 = bitcast <2 x i64> %tmp30 to <4 x i32>
%tmp32 = icmp eq <4 x i32> %tmp31, zeroinitializer %tmp32 = icmp eq <4 x i32> %tmp31, zeroinitializer
%tmp33 = sext <4 x i1> %tmp32 to <4 x i32> %tmp33 = sext <4 x i1> %tmp32 to <4 x i32>
%tmp34 = bitcast <4 x i32> %tmp33 to <4 x float> %tmp34 = bitcast <4 x i32> %tmp33 to <4 x float>
%tmp35 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %tmp27, <4 x float> %tmp29, <4 x float> %tmp34) #2 %tmp35 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %tmp27, <4 x float> %tmp29, <4 x float> %tmp34) #2
%tmp36 = and <2 x i64> %tmp10, <i64 8589934594, i64 8589934594> %tmp36 = and <2 x i64> %tmp10, <i64 8589934594, i64 8589934594>
%tmp37 = bitcast <2 x i64> %tmp36 to <4 x i32> %tmp37 = bitcast <2 x i64> %tmp36 to <4 x i32>
%tmp38 = icmp eq <4 x i32> %tmp37, zeroinitializer %tmp38 = icmp eq <4 x i32> %tmp37, zeroinitializer
%tmp39 = sext <4 x i1> %tmp38 to <4 x i32> %tmp39 = sext <4 x i1> %tmp38 to <4 x i32>
%tmp40 = bitcast <4 x float> %tmp35 to <4 x i32> %tmp40 = bitcast <4 x float> %tmp35 to <4 x i32>
%tmp41 = xor <4 x i32> %tmp40, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> %tmp41 = xor <4 x i32> %tmp40, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
%tmp42 = bitcast <4 x i32> %tmp41 to <4 x float> %tmp42 = bitcast <4 x i32> %tmp41 to <4 x float>
%tmp43 = bitcast <4 x i32> %tmp39 to <4 x float> %tmp43 = bitcast <4 x i32> %tmp39 to <4 x float>
%tmp44 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %tmp42, <4 x float> %tmp35, <4 x float> %tmp43) #2 %tmp44 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %tmp42, <4 x float> %tmp35, <4 x float> %tmp43) #2
%tmp45 = bitcast <2 x double> %arg1 to <4 x float> %tmp45 = bitcast <2 x double> %arg1 to <4 x float>
%tmp46 = fmul <4 x float> %tmp45, <float 0x3FE45F3060000000, float 0x3FE45F3060000000, float 0x3FE45F3060000000, float 0x3FE45F3060000000> %tmp46 = fmul <4 x float> %tmp45, <float 0x3FE45F3060000000, float 0x3FE45F3060000000, float 0x3FE45F3060000000, float 0x3FE45F3060000000>
%tmp47 = bitcast <2 x double> %arg1 to <4 x i32> %tmp47 = bitcast <2 x double> %arg1 to <4 x i32>
%tmp48 = and <4 x i32> %tmp47, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> %tmp48 = and <4 x i32> %tmp47, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
%tmp49 = or <4 x i32> %tmp48, <i32 1056964608, i32 1056964608, i32 1056964608, i32 1056964608> %tmp49 = or <4 x i32> %tmp48, <i32 1056964608, i32 1056964608, i32 1056964608, i32 1056964608>
%tmp50 = bitcast <4 x i32> %tmp49 to <4 x float> %tmp50 = bitcast <4 x i32> %tmp49 to <4 x float>
%tmp51 = fadd <4 x float> %tmp46, %tmp50 %tmp51 = fadd <4 x float> %tmp46, %tmp50
%tmp52 = tail call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %tmp51) #2 %tmp52 = tail call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %tmp51) #2
%tmp53 = bitcast <4 x i32> %tmp52 to <2 x i64> %tmp53 = bitcast <4 x i32> %tmp52 to <2 x i64>
%tmp54 = tail call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %tmp52) #2 %tmp54 = tail call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %tmp52) #2
%tmp55 = fmul <4 x float> %tmp54, <float 0x3FF921FB40000000, float 0x3FF921FB40000000, float 0x3FF921FB40000000, float 0x3FF921FB40000000> %tmp55 = fmul <4 x float> %tmp54, <float 0x3FF921FB40000000, float 0x3FF921FB40000000, float 0x3FF921FB40000000, float 0x3FF921FB40000000>
%tmp56 = fsub <4 x float> %tmp45, %tmp55 %tmp56 = fsub <4 x float> %tmp45, %tmp55
%tmp57 = fmul <4 x float> %tmp54, <float 0x3E74442D00000000, float 0x3E74442D00000000, float 0x3E74442D00000000, float 0x3E74442D00000000> %tmp57 = fmul <4 x float> %tmp54, <float 0x3E74442D00000000, float 0x3E74442D00000000, float 0x3E74442D00000000, float 0x3E74442D00000000>
%tmp58 = fsub <4 x float> %tmp56, %tmp57 %tmp58 = fsub <4 x float> %tmp56, %tmp57
%tmp59 = fmul <4 x float> %tmp58, %tmp58 %tmp59 = fmul <4 x float> %tmp58, %tmp58
%tmp60 = fmul <4 x float> %tmp58, %tmp59 %tmp60 = fmul <4 x float> %tmp58, %tmp59
%tmp61 = fmul <4 x float> %tmp59, <float 0xBF56493260000000, float 0xBF56493260000000, float 0xBF56493260000000, float 0xBF56493260000000> %tmp61 = fmul <4 x float> %tmp59, <float 0xBF56493260000000, float 0xBF56493260000000, float 0xBF56493260000000, float 0xBF56493260000000>
%tmp62 = fadd <4 x float> %tmp61, <float 0x3FA55406C0000000, float 0x3FA55406C0000000, float 0x3FA55406C0000000, float 0x3FA55406C0000000> %tmp62 = fadd <4 x float> %tmp61, <float 0x3FA55406C0000000, float 0x3FA55406C0000000, float 0x3FA55406C0000000, float 0x3FA55406C0000000>
%tmp63 = fmul <4 x float> %tmp59, <float 0xBF29918DC0000000, float 0xBF29918DC0000000, float 0xBF29918DC0000000, float 0xBF29918DC0000000> %tmp63 = fmul <4 x float> %tmp59, <float 0xBF29918DC0000000, float 0xBF29918DC0000000, float 0xBF29918DC0000000, float 0xBF29918DC0000000>
%tmp64 = fadd <4 x float> %tmp63, <float 0x3F81106840000000, float 0x3F81106840000000, float 0x3F81106840000000, float 0x3F81106840000000> %tmp64 = fadd <4 x float> %tmp63, <float 0x3F81106840000000, float 0x3F81106840000000, float 0x3F81106840000000, float 0x3F81106840000000>
%tmp65 = fmul <4 x float> %tmp59, %tmp62 %tmp65 = fmul <4 x float> %tmp59, %tmp62
%tmp66 = fadd <4 x float> %tmp65, <float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000> %tmp66 = fadd <4 x float> %tmp65, <float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000>
%tmp67 = fmul <4 x float> %tmp59, %tmp64 %tmp67 = fmul <4 x float> %tmp59, %tmp64
%tmp68 = fadd <4 x float> %tmp67, <float 0xBFC5555420000000, float 0xBFC5555420000000, float 0xBFC5555420000000, float 0xBFC5555420000000> %tmp68 = fadd <4 x float> %tmp67, <float 0xBFC5555420000000, float 0xBFC5555420000000, float 0xBFC5555420000000, float 0xBFC5555420000000>
%tmp69 = fmul <4 x float> %tmp59, %tmp66 %tmp69 = fmul <4 x float> %tmp59, %tmp66
%tmp70 = fadd <4 x float> %tmp69, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> %tmp70 = fadd <4 x float> %tmp69, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
%tmp71 = fmul <4 x float> %tmp60, %tmp68 %tmp71 = fmul <4 x float> %tmp60, %tmp68
%tmp72 = fadd <4 x float> %tmp58, %tmp71 %tmp72 = fadd <4 x float> %tmp58, %tmp71
%tmp73 = and <2 x i64> %tmp53, <i64 4294967297, i64 4294967297> %tmp73 = and <2 x i64> %tmp53, <i64 4294967297, i64 4294967297>
%tmp74 = bitcast <2 x i64> %tmp73 to <4 x i32> %tmp74 = bitcast <2 x i64> %tmp73 to <4 x i32>
%tmp75 = icmp eq <4 x i32> %tmp74, zeroinitializer %tmp75 = icmp eq <4 x i32> %tmp74, zeroinitializer
%tmp76 = sext <4 x i1> %tmp75 to <4 x i32> %tmp76 = sext <4 x i1> %tmp75 to <4 x i32>
%tmp77 = bitcast <4 x i32> %tmp76 to <4 x float> %tmp77 = bitcast <4 x i32> %tmp76 to <4 x float>
%tmp78 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %tmp70, <4 x float> %tmp72, <4 x float> %tmp77) #2 %tmp78 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %tmp70, <4 x float> %tmp72, <4 x float> %tmp77) #2
%tmp79 = and <2 x i64> %tmp53, <i64 8589934594, i64 8589934594> %tmp79 = and <2 x i64> %tmp53, <i64 8589934594, i64 8589934594>
%tmp80 = bitcast <2 x i64> %tmp79 to <4 x i32> %tmp80 = bitcast <2 x i64> %tmp79 to <4 x i32>
%tmp81 = icmp eq <4 x i32> %tmp80, zeroinitializer %tmp81 = icmp eq <4 x i32> %tmp80, zeroinitializer
%tmp82 = sext <4 x i1> %tmp81 to <4 x i32> %tmp82 = sext <4 x i1> %tmp81 to <4 x i32>
%tmp83 = bitcast <4 x float> %tmp78 to <4 x i32> %tmp83 = bitcast <4 x float> %tmp78 to <4 x i32>
%tmp84 = xor <4 x i32> %tmp83, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> %tmp84 = xor <4 x i32> %tmp83, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
%tmp85 = bitcast <4 x i32> %tmp84 to <4 x float> %tmp85 = bitcast <4 x i32> %tmp84 to <4 x float>
%tmp86 = bitcast <4 x i32> %tmp82 to <4 x float> %tmp86 = bitcast <4 x i32> %tmp82 to <4 x float>
%tmp87 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %tmp85, <4 x float> %tmp78, <4 x float> %tmp86) #2 %tmp87 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %tmp85, <4 x float> %tmp78, <4 x float> %tmp86) #2
%tmp88 = fadd <4 x float> %tmp44, %tmp87 %tmp88 = fadd <4 x float> %tmp44, %tmp87
%tmp89 = bitcast <2 x double> %arg2 to <4 x float> %tmp89 = bitcast <2 x double> %arg2 to <4 x float>
%tmp90 = fmul <4 x float> %tmp89, <float 0x3FE45F3060000000, float 0x3FE45F3060000000, float 0x3FE45F3060000000, float 0x3FE45F3060000000> %tmp90 = fmul <4 x float> %tmp89, <float 0x3FE45F3060000000, float 0x3FE45F3060000000, float 0x3FE45F3060000000, float 0x3FE45F3060000000>
%tmp91 = bitcast <2 x double> %arg2 to <4 x i32> %tmp91 = bitcast <2 x double> %arg2 to <4 x i32>
%tmp92 = and <4 x i32> %tmp91, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> %tmp92 = and <4 x i32> %tmp91, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
%tmp93 = or <4 x i32> %tmp92, <i32 1056964608, i32 1056964608, i32 1056964608, i32 1056964608> %tmp93 = or <4 x i32> %tmp92, <i32 1056964608, i32 1056964608, i32 1056964608, i32 1056964608>
%tmp94 = bitcast <4 x i32> %tmp93 to <4 x float> %tmp94 = bitcast <4 x i32> %tmp93 to <4 x float>
%tmp95 = fadd <4 x float> %tmp90, %tmp94 %tmp95 = fadd <4 x float> %tmp90, %tmp94
%tmp96 = tail call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %tmp95) #2 %tmp96 = tail call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %tmp95) #2
%tmp97 = bitcast <4 x i32> %tmp96 to <2 x i64> %tmp97 = bitcast <4 x i32> %tmp96 to <2 x i64>
%tmp98 = tail call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %tmp96) #2 %tmp98 = tail call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %tmp96) #2
%tmp99 = fmul <4 x float> %tmp98, <float 0x3FF921FB40000000, float 0x3FF921FB40000000, float 0x3FF921FB40000000, float 0x3FF921FB40000000> %tmp99 = fmul <4 x float> %tmp98, <float 0x3FF921FB40000000, float 0x3FF921FB40000000, float 0x3FF921FB40000000, float 0x3FF921FB40000000>
%tmp100 = fsub <4 x float> %tmp89, %tmp99 %tmp100 = fsub <4 x float> %tmp89, %tmp99
%tmp101 = fmul <4 x float> %tmp98, <float 0x3E74442D00000000, float 0x3E74442D00000000, float 0x3E74442D00000000, float 0x3E74442D00000000> %tmp101 = fmul <4 x float> %tmp98, <float 0x3E74442D00000000, float 0x3E74442D00000000, float 0x3E74442D00000000, float 0x3E74442D00000000>
%tmp102 = fsub <4 x float> %tmp100, %tmp101 %tmp102 = fsub <4 x float> %tmp100, %tmp101
%tmp103 = fmul <4 x float> %tmp102, %tmp102 %tmp103 = fmul <4 x float> %tmp102, %tmp102
%tmp104 = fmul <4 x float> %tmp102, %tmp103 %tmp104 = fmul <4 x float> %tmp102, %tmp103
%tmp105 = fmul <4 x float> %tmp103, <float 0xBF56493260000000, float 0xBF56493260000000, float 0xBF56493260000000, float 0xBF56493260000000> %tmp105 = fmul <4 x float> %tmp103, <float 0xBF56493260000000, float 0xBF56493260000000, float 0xBF56493260000000, float 0xBF56493260000000>
%tmp106 = fadd <4 x float> %tmp105, <float 0x3FA55406C0000000, float 0x3FA55406C0000000, float 0x3FA55406C0000000, float 0x3FA55406C0000000> %tmp106 = fadd <4 x float> %tmp105, <float 0x3FA55406C0000000, float 0x3FA55406C0000000, float 0x3FA55406C0000000, float 0x3FA55406C0000000>
%tmp107 = fmul <4 x float> %tmp103, <float 0xBF29918DC0000000, float 0xBF29918DC0000000, float 0xBF29918DC0000000, float 0xBF29918DC0000000> %tmp107 = fmul <4 x float> %tmp103, <float 0xBF29918DC0000000, float 0xBF29918DC0000000, float 0xBF29918DC0000000, float 0xBF29918DC0000000>
%tmp108 = fadd <4 x float> %tmp107, <float 0x3F81106840000000, float 0x3F81106840000000, float 0x3F81106840000000, float 0x3F81106840000000> %tmp108 = fadd <4 x float> %tmp107, <float 0x3F81106840000000, float 0x3F81106840000000, float 0x3F81106840000000, float 0x3F81106840000000>
%tmp109 = fmul <4 x float> %tmp103, %tmp106 %tmp109 = fmul <4 x float> %tmp103, %tmp106
%tmp110 = fadd <4 x float> %tmp109, <float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000> %tmp110 = fadd <4 x float> %tmp109, <float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000, float 0xBFDFFFFBE0000000>
%tmp111 = fmul <4 x float> %tmp103, %tmp108 %tmp111 = fmul <4 x float> %tmp103, %tmp108
%tmp112 = fadd <4 x float> %tmp111, <float 0xBFC5555420000000, float 0xBFC5555420000000, float 0xBFC5555420000000, float 0xBFC5555420000000> %tmp112 = fadd <4 x float> %tmp111, <float 0xBFC5555420000000, float 0xBFC5555420000000, float 0xBFC5555420000000, float 0xBFC5555420000000>
%tmp113 = fmul <4 x float> %tmp103, %tmp110 %tmp113 = fmul <4 x float> %tmp103, %tmp110
%tmp114 = fadd <4 x float> %tmp113, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> %tmp114 = fadd <4 x float> %tmp113, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
%tmp115 = fmul <4 x float> %tmp104, %tmp112 %tmp115 = fmul <4 x float> %tmp104, %tmp112
%tmp116 = fadd <4 x float> %tmp102, %tmp115 %tmp116 = fadd <4 x float> %tmp102, %tmp115
%tmp117 = and <2 x i64> %tmp97, <i64 4294967297, i64 4294967297> %tmp117 = and <2 x i64> %tmp97, <i64 4294967297, i64 4294967297>
%tmp118 = bitcast <2 x i64> %tmp117 to <4 x i32> %tmp118 = bitcast <2 x i64> %tmp117 to <4 x i32>
%tmp119 = icmp eq <4 x i32> %tmp118, zeroinitializer %tmp119 = icmp eq <4 x i32> %tmp118, zeroinitializer
%tmp120 = sext <4 x i1> %tmp119 to <4 x i32> %tmp120 = sext <4 x i1> %tmp119 to <4 x i32>
%tmp121 = bitcast <4 x i32> %tmp120 to <4 x float> %tmp121 = bitcast <4 x i32> %tmp120 to <4 x float>
%tmp122 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %tmp114, <4 x float> %tmp116, <4 x float> %tmp121) #2 %tmp122 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %tmp114, <4 x float> %tmp116, <4 x float> %tmp121) #2
%tmp123 = and <2 x i64> %tmp97, <i64 8589934594, i64 8589934594> %tmp123 = and <2 x i64> %tmp97, <i64 8589934594, i64 8589934594>
%tmp124 = bitcast <2 x i64> %tmp123 to <4 x i32> %tmp124 = bitcast <2 x i64> %tmp123 to <4 x i32>
%tmp125 = icmp eq <4 x i32> %tmp124, zeroinitializer %tmp125 = icmp eq <4 x i32> %tmp124, zeroinitializer
%tmp126 = sext <4 x i1> %tmp125 to <4 x i32> %tmp126 = sext <4 x i1> %tmp125 to <4 x i32>
%tmp127 = bitcast <4 x float> %tmp122 to <4 x i32> %tmp127 = bitcast <4 x float> %tmp122 to <4 x i32>
%tmp128 = xor <4 x i32> %tmp127, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> %tmp128 = xor <4 x i32> %tmp127, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
%tmp129 = bitcast <4 x i32> %tmp128 to <4 x float> %tmp129 = bitcast <4 x i32> %tmp128 to <4 x float>
%tmp130 = bitcast <4 x i32> %tmp126 to <4 x float> %tmp130 = bitcast <4 x i32> %tmp126 to <4 x float>
%tmp131 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %tmp129, <4 x float> %tmp122, <4 x float> %tmp130) #2 %tmp131 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %tmp129, <4 x float> %tmp122, <4 x float> %tmp130) #2
%tmp132 = fadd <4 x float> %tmp88, %tmp131 %tmp132 = fadd <4 x float> %tmp88, %tmp131
%tmp133 = bitcast <4 x float> %tmp132 to <2 x double> %tmp133 = bitcast <4 x float> %tmp132 to <2 x double>
ret <2 x double> %tmp133 ret <2 x double> %tmp133
} }
declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>)
declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>)
declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>) declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>)

test/CodeGen/X86/statepoint-far-call.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc < %s | FileCheck %s
; Test to check that Statepoints with X64 far-immediate targets ; Test to check that Statepoints with X64 far-immediate targets
; are lowered correctly to an indirect call via a scratch register. ; are lowered correctly to an indirect call via a scratch register.
target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-pc-win64" target triple = "x86_64-pc-win64"
define void @test_far_call() gc "statepoint-example" { define void @test_far_call() gc "statepoint-example" {
; CHECK-LABEL: test_far_call ; CHECK-LABEL: test_far_call
; CHECK: pushq %rax ; CHECK: pushq %rax
; CHECK: movabsq $140727162896504, %rax ; CHECK: movabsq $140727162896504, %rax
; CHECK: callq *%rax ; CHECK: callq *%rax
; CHECK: popq %rax ; CHECK: popq %rax
; CHECK: retq ; CHECK: retq
entry: entry:
%safepoint_token = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* inttoptr (i64 140727162896504 to void ()*), i32 0, i32 0, i32 0, i32 0) %safepoint_token = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* inttoptr (i64 140727162896504 to void ()*), i32 0, i32 0, i32 0, i32 0)
ret void ret void
} }
declare token @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...) declare token @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...)

test/CodeGen/X86/system-intrinsics-64-xsave.ll

; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xsave | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xsave | FileCheck %s
define void @test_xsave(i8* %ptr, i32 %hi, i32 %lo) { define void @test_xsave(i8* %ptr, i32 %hi, i32 %lo) {
; CHECK-LABEL: test_xsave ; CHECK-LABEL: test_xsave
; CHECK: movl %edx, %eax ; CHECK: movl %edx, %eax
; CHECK: movl %esi, %edx ; CHECK: movl %esi, %edx
; CHECK: xsave (%rdi) ; CHECK: xsave (%rdi)
call void @llvm.x86.xsave(i8* %ptr, i32 %hi, i32 %lo) call void @llvm.x86.xsave(i8* %ptr, i32 %hi, i32 %lo)
ret void; ret void;
} }
declare void @llvm.x86.xsave(i8*, i32, i32) declare void @llvm.x86.xsave(i8*, i32, i32)
define void @test_xsave64(i8* %ptr, i32 %hi, i32 %lo) { define void @test_xsave64(i8* %ptr, i32 %hi, i32 %lo) {
; CHECK-LABEL: test_xsave64 ; CHECK-LABEL: test_xsave64
; CHECK: movl %edx, %eax ; CHECK: movl %edx, %eax
; CHECK: movl %esi, %edx ; CHECK: movl %esi, %edx
; CHECK: xsave64 (%rdi) ; CHECK: xsave64 (%rdi)
call void @llvm.x86.xsave64(i8* %ptr, i32 %hi, i32 %lo) call void @llvm.x86.xsave64(i8* %ptr, i32 %hi, i32 %lo)
ret void; ret void;
} }
declare void @llvm.x86.xsave64(i8*, i32, i32) declare void @llvm.x86.xsave64(i8*, i32, i32)
define void @test_xrstor(i8* %ptr, i32 %hi, i32 %lo) { define void @test_xrstor(i8* %ptr, i32 %hi, i32 %lo) {
; CHECK-LABEL: test_xrstor ; CHECK-LABEL: test_xrstor
; CHECK: movl %edx, %eax ; CHECK: movl %edx, %eax
; CHECK: movl %esi, %edx ; CHECK: movl %esi, %edx
; CHECK: xrstor (%rdi) ; CHECK: xrstor (%rdi)
call void @llvm.x86.xrstor(i8* %ptr, i32 %hi, i32 %lo) call void @llvm.x86.xrstor(i8* %ptr, i32 %hi, i32 %lo)
ret void; ret void;
} }
declare void @llvm.x86.xrstor(i8*, i32, i32) declare void @llvm.x86.xrstor(i8*, i32, i32)
define void @test_xrstor64(i8* %ptr, i32 %hi, i32 %lo) { define void @test_xrstor64(i8* %ptr, i32 %hi, i32 %lo) {
; CHECK-LABEL: test_xrstor64 ; CHECK-LABEL: test_xrstor64
; CHECK: movl %edx, %eax ; CHECK: movl %edx, %eax
; CHECK: movl %esi, %edx ; CHECK: movl %esi, %edx
; CHECK: xrstor64 (%rdi) ; CHECK: xrstor64 (%rdi)
call void @llvm.x86.xrstor64(i8* %ptr, i32 %hi, i32 %lo) call void @llvm.x86.xrstor64(i8* %ptr, i32 %hi, i32 %lo)
ret void; ret void;
} }
declare void @llvm.x86.xrstor64(i8*, i32, i32) declare void @llvm.x86.xrstor64(i8*, i32, i32)

test/CodeGen/X86/system-intrinsics-64-xsavec.ll

; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xsave,+xsavec | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xsave,+xsavec | FileCheck %s
define void @test_xsavec(i8* %ptr, i32 %hi, i32 %lo) { define void @test_xsavec(i8* %ptr, i32 %hi, i32 %lo) {
; CHECK-LABEL: test_xsavec ; CHECK-LABEL: test_xsavec
; CHECK: movl %edx, %eax ; CHECK: movl %edx, %eax
; CHECK: movl %esi, %edx ; CHECK: movl %esi, %edx
; CHECK: xsavec (%rdi) ; CHECK: xsavec (%rdi)
call void @llvm.x86.xsavec(i8* %ptr, i32 %hi, i32 %lo) call void @llvm.x86.xsavec(i8* %ptr, i32 %hi, i32 %lo)
ret void; ret void;
} }
declare void @llvm.x86.xsavec(i8*, i32, i32) declare void @llvm.x86.xsavec(i8*, i32, i32)
define void @test_xsavec64(i8* %ptr, i32 %hi, i32 %lo) { define void @test_xsavec64(i8* %ptr, i32 %hi, i32 %lo) {
; CHECK-LABEL: test_xsavec64 ; CHECK-LABEL: test_xsavec64
; CHECK: movl %edx, %eax ; CHECK: movl %edx, %eax
; CHECK: movl %esi, %edx ; CHECK: movl %esi, %edx
; CHECK: xsavec64 (%rdi) ; CHECK: xsavec64 (%rdi)
call void @llvm.x86.xsavec64(i8* %ptr, i32 %hi, i32 %lo) call void @llvm.x86.xsavec64(i8* %ptr, i32 %hi, i32 %lo)
ret void; ret void;
} }
declare void @llvm.x86.xsavec64(i8*, i32, i32) declare void @llvm.x86.xsavec64(i8*, i32, i32)

test/CodeGen/X86/system-intrinsics-64-xsaveopt.ll

; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xsaveopt | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xsaveopt | FileCheck %s
define void @test_xsaveopt(i8* %ptr, i32 %hi, i32 %lo) { define void @test_xsaveopt(i8* %ptr, i32 %hi, i32 %lo) {
; CHECK-LABEL: test_xsaveopt ; CHECK-LABEL: test_xsaveopt
; CHECK: movl %edx, %eax ; CHECK: movl %edx, %eax
; CHECK: movl %esi, %edx ; CHECK: movl %esi, %edx
; CHECK: xsaveopt (%rdi) ; CHECK: xsaveopt (%rdi)
call void @llvm.x86.xsaveopt(i8* %ptr, i32 %hi, i32 %lo) call void @llvm.x86.xsaveopt(i8* %ptr, i32 %hi, i32 %lo)
ret void; ret void;
} }
declare void @llvm.x86.xsaveopt(i8*, i32, i32) declare void @llvm.x86.xsaveopt(i8*, i32, i32)
define void @test_xsaveopt64(i8* %ptr, i32 %hi, i32 %lo) { define void @test_xsaveopt64(i8* %ptr, i32 %hi, i32 %lo) {
; CHECK-LABEL: test_xsaveopt64 ; CHECK-LABEL: test_xsaveopt64
; CHECK: movl %edx, %eax ; CHECK: movl %edx, %eax
; CHECK: movl %esi, %edx ; CHECK: movl %esi, %edx
; CHECK: xsaveopt64 (%rdi) ; CHECK: xsaveopt64 (%rdi)
call void @llvm.x86.xsaveopt64(i8* %ptr, i32 %hi, i32 %lo) call void @llvm.x86.xsaveopt64(i8* %ptr, i32 %hi, i32 %lo)
ret void; ret void;
} }
declare void @llvm.x86.xsaveopt64(i8*, i32, i32) declare void @llvm.x86.xsaveopt64(i8*, i32, i32)

test/CodeGen/X86/system-intrinsics-64-xsaves.ll

; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xsave,+xsaves | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xsave,+xsaves | FileCheck %s
define void @test_xsaves(i8* %ptr, i32 %hi, i32 %lo) { define void @test_xsaves(i8* %ptr, i32 %hi, i32 %lo) {
; CHECK-LABEL: test_xsaves ; CHECK-LABEL: test_xsaves
; CHECK: movl %edx, %eax ; CHECK: movl %edx, %eax
; CHECK: movl %esi, %edx ; CHECK: movl %esi, %edx
; CHECK: xsaves (%rdi) ; CHECK: xsaves (%rdi)
call void @llvm.x86.xsaves(i8* %ptr, i32 %hi, i32 %lo) call void @llvm.x86.xsaves(i8* %ptr, i32 %hi, i32 %lo)
ret void; ret void;
} }
declare void @llvm.x86.xsaves(i8*, i32, i32) declare void @llvm.x86.xsaves(i8*, i32, i32)
define void @test_xsaves64(i8* %ptr, i32 %hi, i32 %lo) { define void @test_xsaves64(i8* %ptr, i32 %hi, i32 %lo) {
; CHECK-LABEL: test_xsaves64 ; CHECK-LABEL: test_xsaves64
; CHECK: movl %edx, %eax ; CHECK: movl %edx, %eax
; CHECK: movl %esi, %edx ; CHECK: movl %esi, %edx
; CHECK: xsaves64 (%rdi) ; CHECK: xsaves64 (%rdi)
call void @llvm.x86.xsaves64(i8* %ptr, i32 %hi, i32 %lo) call void @llvm.x86.xsaves64(i8* %ptr, i32 %hi, i32 %lo)
ret void; ret void;
} }
declare void @llvm.x86.xsaves64(i8*, i32, i32) declare void @llvm.x86.xsaves64(i8*, i32, i32)
define void @test_xrstors(i8* %ptr, i32 %hi, i32 %lo) { define void @test_xrstors(i8* %ptr, i32 %hi, i32 %lo) {
; CHECK-LABEL: test_xrstors ; CHECK-LABEL: test_xrstors
; CHECK: movl %edx, %eax ; CHECK: movl %edx, %eax
; CHECK: movl %esi, %edx ; CHECK: movl %esi, %edx
; CHECK: xrstors (%rdi) ; CHECK: xrstors (%rdi)
call void @llvm.x86.xrstors(i8* %ptr, i32 %hi, i32 %lo) call void @llvm.x86.xrstors(i8* %ptr, i32 %hi, i32 %lo)
ret void; ret void;
} }
declare void @llvm.x86.xrstors(i8*, i32, i32) declare void @llvm.x86.xrstors(i8*, i32, i32)
define void @test_xrstors64(i8* %ptr, i32 %hi, i32 %lo) { define void @test_xrstors64(i8* %ptr, i32 %hi, i32 %lo) {
; CHECK-LABEL: test_xrstors64 ; CHECK-LABEL: test_xrstors64
; CHECK: movl %edx, %eax ; CHECK: movl %edx, %eax
; CHECK: movl %esi, %edx ; CHECK: movl %esi, %edx
; CHECK: xrstors64 (%rdi) ; CHECK: xrstors64 (%rdi)
call void @llvm.x86.xrstors64(i8* %ptr, i32 %hi, i32 %lo) call void @llvm.x86.xrstors64(i8* %ptr, i32 %hi, i32 %lo)
ret void; ret void;
} }
declare void @llvm.x86.xrstors64(i8*, i32, i32) declare void @llvm.x86.xrstors64(i8*, i32, i32)

test/CodeGen/X86/system-intrinsics-xsave.ll

; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+xsave | FileCheck %s ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+xsave | FileCheck %s
define void @test_xsave(i8* %ptr, i32 %hi, i32 %lo) { define void @test_xsave(i8* %ptr, i32 %hi, i32 %lo) {
; CHECK-LABEL: test_xsave ; CHECK-LABEL: test_xsave
; CHECK: movl 8(%esp), %edx ; CHECK: movl 8(%esp), %edx
; CHECK: movl 12(%esp), %eax ; CHECK: movl 12(%esp), %eax
; CHECK: movl 4(%esp), %ecx ; CHECK: movl 4(%esp), %ecx
; CHECK: xsave (%ecx) ; CHECK: xsave (%ecx)
call void @llvm.x86.xsave(i8* %ptr, i32 %hi, i32 %lo) call void @llvm.x86.xsave(i8* %ptr, i32 %hi, i32 %lo)
ret void; ret void;
} }
declare void @llvm.x86.xsave(i8*, i32, i32) declare void @llvm.x86.xsave(i8*, i32, i32)
define void @test_xrstor(i8* %ptr, i32 %hi, i32 %lo) { define void @test_xrstor(i8* %ptr, i32 %hi, i32 %lo) {
; CHECK-LABEL: test_xrstor ; CHECK-LABEL: test_xrstor
; CHECK: movl 8(%esp), %edx ; CHECK: movl 8(%esp), %edx
; CHECK: movl 12(%esp), %eax ; CHECK: movl 12(%esp), %eax
; CHECK: movl 4(%esp), %ecx ; CHECK: movl 4(%esp), %ecx
; CHECK: xrstor (%ecx) ; CHECK: xrstor (%ecx)
call void @llvm.x86.xrstor(i8* %ptr, i32 %hi, i32 %lo) call void @llvm.x86.xrstor(i8* %ptr, i32 %hi, i32 %lo)
ret void; ret void;
} }
declare void @llvm.x86.xrstor(i8*, i32, i32) declare void @llvm.x86.xrstor(i8*, i32, i32)

test/CodeGen/X86/system-intrinsics-xsavec.ll

; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+xsave,+xsavec | FileCheck %s ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+xsave,+xsavec | FileCheck %s
define void @test_xsavec(i8* %ptr, i32 %hi, i32 %lo) { define void @test_xsavec(i8* %ptr, i32 %hi, i32 %lo) {
; CHECK-LABEL: test_xsavec ; CHECK-LABEL: test_xsavec
; CHECK: movl 8(%esp), %edx ; CHECK: movl 8(%esp), %edx
; CHECK: movl 12(%esp), %eax ; CHECK: movl 12(%esp), %eax
; CHECK: movl 4(%esp), %ecx ; CHECK: movl 4(%esp), %ecx
; CHECK: xsavec (%ecx) ; CHECK: xsavec (%ecx)
call void @llvm.x86.xsavec(i8* %ptr, i32 %hi, i32 %lo) call void @llvm.x86.xsavec(i8* %ptr, i32 %hi, i32 %lo)
ret void; ret void;
} }
declare void @llvm.x86.xsavec(i8*, i32, i32) declare void @llvm.x86.xsavec(i8*, i32, i32)

test/CodeGen/X86/system-intrinsics-xsaveopt.ll

; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+xsave,+xsaveopt | FileCheck %s ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+xsave,+xsaveopt | FileCheck %s
define void @test_xsaveopt(i8* %ptr, i32 %hi, i32 %lo) { define void @test_xsaveopt(i8* %ptr, i32 %hi, i32 %lo) {
; CHECK-LABEL: test_xsaveopt ; CHECK-LABEL: test_xsaveopt
; CHECK: movl 8(%esp), %edx ; CHECK: movl 8(%esp), %edx
; CHECK: movl 12(%esp), %eax ; CHECK: movl 12(%esp), %eax
; CHECK: movl 4(%esp), %ecx ; CHECK: movl 4(%esp), %ecx
; CHECK: xsaveopt (%ecx) ; CHECK: xsaveopt (%ecx)
call void @llvm.x86.xsaveopt(i8* %ptr, i32 %hi, i32 %lo) call void @llvm.x86.xsaveopt(i8* %ptr, i32 %hi, i32 %lo)
ret void; ret void;
} }
declare void @llvm.x86.xsaveopt(i8*, i32, i32) declare void @llvm.x86.xsaveopt(i8*, i32, i32)

test/CodeGen/X86/system-intrinsics-xsaves.ll

; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+xsave,+xsaves | FileCheck %s ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+xsave,+xsaves | FileCheck %s
define void @test_xsaves(i8* %ptr, i32 %hi, i32 %lo) { define void @test_xsaves(i8* %ptr, i32 %hi, i32 %lo) {
; CHECK-LABEL: test_xsaves ; CHECK-LABEL: test_xsaves
; CHECK: movl 8(%esp), %edx ; CHECK: movl 8(%esp), %edx
; CHECK: movl 12(%esp), %eax ; CHECK: movl 12(%esp), %eax
; CHECK: movl 4(%esp), %ecx ; CHECK: movl 4(%esp), %ecx
; CHECK: xsaves (%ecx) ; CHECK: xsaves (%ecx)
call void @llvm.x86.xsaves(i8* %ptr, i32 %hi, i32 %lo) call void @llvm.x86.xsaves(i8* %ptr, i32 %hi, i32 %lo)
ret void; ret void;
} }
declare void @llvm.x86.xsaves(i8*, i32, i32) declare void @llvm.x86.xsaves(i8*, i32, i32)
define void @test_xrstors(i8* %ptr, i32 %hi, i32 %lo) { define void @test_xrstors(i8* %ptr, i32 %hi, i32 %lo) {
; CHECK-LABEL: test_xrstors ; CHECK-LABEL: test_xrstors
; CHECK: movl 8(%esp), %edx ; CHECK: movl 8(%esp), %edx
; CHECK: movl 12(%esp), %eax ; CHECK: movl 12(%esp), %eax
; CHECK: movl 4(%esp), %ecx ; CHECK: movl 4(%esp), %ecx
; CHECK: xrstors (%ecx) ; CHECK: xrstors (%ecx)
call void @llvm.x86.xrstors(i8* %ptr, i32 %hi, i32 %lo) call void @llvm.x86.xrstors(i8* %ptr, i32 %hi, i32 %lo)
ret void; ret void;
} }
declare void @llvm.x86.xrstors(i8*, i32, i32) declare void @llvm.x86.xrstors(i8*, i32, i32)

test/CodeGen/X86/vec_partial.ll

; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
; PR11580 ; PR11580
define <3 x float> @addf3(<3 x float> %x) { define <3 x float> @addf3(<3 x float> %x) {
; CHECK-LABEL: addf3 ; CHECK-LABEL: addf3
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: addps .LCPI0_0(%rip), %xmm0 ; CHECK-NEXT: addps .LCPI0_0(%rip), %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%add = fadd <3 x float> %x, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> %add = fadd <3 x float> %x, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
ret <3 x float> %add ret <3 x float> %add
} }
; PR11580 ; PR11580
define <4 x float> @cvtf3_f4(<3 x float> %x) { define <4 x float> @cvtf3_f4(<3 x float> %x) {
; CHECK-LABEL: cvtf3_f4 ; CHECK-LABEL: cvtf3_f4
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%extractVec = shufflevector <3 x float> %x, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> %extractVec = shufflevector <3 x float> %x, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
ret <4 x float> %extractVec ret <4 x float> %extractVec
} }
; PR11580 ; PR11580
define <3 x float> @cvtf4_f3(<4 x float> %x) { define <3 x float> @cvtf4_f3(<4 x float> %x) {
; CHECK-LABEL: cvtf4_f3 ; CHECK-LABEL: cvtf4_f3
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%extractVec = shufflevector <4 x float> %x, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> %extractVec = shufflevector <4 x float> %x, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
ret <3 x float> %extractVec ret <3 x float> %extractVec
} }

test/CodeGen/X86/vec_reassociate.ll

; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s
define <4 x i32> @add_4i32(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @add_4i32(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @add_4i32 ;CHECK-LABEL: @add_4i32
;CHECK: # BB#0: ;CHECK: # BB#0:
;CHECK-NEXT: paddd %xmm1, %xmm0 ;CHECK-NEXT: paddd %xmm1, %xmm0
;CHECK-NEXT: retq ;CHECK-NEXT: retq
%1 = add <4 x i32> %a0, <i32 1, i32 -2, i32 3, i32 -4> %1 = add <4 x i32> %a0, <i32 1, i32 -2, i32 3, i32 -4>
%2 = add <4 x i32> %a1, <i32 -1, i32 2, i32 -3, i32 4> %2 = add <4 x i32> %a1, <i32 -1, i32 2, i32 -3, i32 4>
%3 = add <4 x i32> %1, %2 %3 = add <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <4 x i32> @add_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @add_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @add_4i32_commute ;CHECK-LABEL: @add_4i32_commute
;CHECK: # BB#0: ;CHECK: # BB#0:
;CHECK-NEXT: paddd %xmm1, %xmm0 ;CHECK-NEXT: paddd %xmm1, %xmm0
;CHECK-NEXT: retq ;CHECK-NEXT: retq
%1 = add <4 x i32> <i32 1, i32 -2, i32 3, i32 -4>, %a0 %1 = add <4 x i32> <i32 1, i32 -2, i32 3, i32 -4>, %a0
%2 = add <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, %a1 %2 = add <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, %a1
%3 = add <4 x i32> %1, %2 %3 = add <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <4 x i32> @mul_4i32(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @mul_4i32(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @mul_4i32 ;CHECK-LABEL: @mul_4i32
;CHECK: # BB#0: ;CHECK: # BB#0:
;CHECK-NEXT: pmulld %xmm1, %xmm0 ;CHECK-NEXT: pmulld %xmm1, %xmm0
;CHECK-NEXT: pmulld .LCPI2_0(%rip), %xmm0 ;CHECK-NEXT: pmulld .LCPI2_0(%rip), %xmm0
;CHECK-NEXT: retq ;CHECK-NEXT: retq
%1 = mul <4 x i32> %a0, <i32 1, i32 2, i32 3, i32 4> %1 = mul <4 x i32> %a0, <i32 1, i32 2, i32 3, i32 4>
%2 = mul <4 x i32> %a1, <i32 4, i32 3, i32 2, i32 1> %2 = mul <4 x i32> %a1, <i32 4, i32 3, i32 2, i32 1>
%3 = mul <4 x i32> %1, %2 %3 = mul <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <4 x i32> @mul_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @mul_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @mul_4i32_commute ;CHECK-LABEL: @mul_4i32_commute
;CHECK: # BB#0: ;CHECK: # BB#0:
;CHECK-NEXT: pmulld %xmm1, %xmm0 ;CHECK-NEXT: pmulld %xmm1, %xmm0
;CHECK-NEXT: pmulld .LCPI3_0(%rip), %xmm0 ;CHECK-NEXT: pmulld .LCPI3_0(%rip), %xmm0
;CHECK-NEXT: retq ;CHECK-NEXT: retq
%1 = mul <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %a0 %1 = mul <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %a0
%2 = mul <4 x i32> <i32 4, i32 3, i32 2, i32 1>, %a1 %2 = mul <4 x i32> <i32 4, i32 3, i32 2, i32 1>, %a1
%3 = mul <4 x i32> %1, %2 %3 = mul <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <4 x i32> @and_4i32(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @and_4i32(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @and_4i32 ;CHECK-LABEL: @and_4i32
;CHECK: # BB#0: ;CHECK: # BB#0:
;CHECK-NEXT: andps %xmm1, %xmm0 ;CHECK-NEXT: andps %xmm1, %xmm0
;CHECK-NEXT: andps .LCPI4_0(%rip), %xmm0 ;CHECK-NEXT: andps .LCPI4_0(%rip), %xmm0
;CHECK-NEXT: retq ;CHECK-NEXT: retq
%1 = and <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3> %1 = and <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
%2 = and <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1> %2 = and <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
%3 = and <4 x i32> %1, %2 %3 = and <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <4 x i32> @and_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @and_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @and_4i32_commute ;CHECK-LABEL: @and_4i32_commute
;CHECK: # BB#0: ;CHECK: # BB#0:
;CHECK-NEXT: andps %xmm1, %xmm0 ;CHECK-NEXT: andps %xmm1, %xmm0
;CHECK-NEXT: andps .LCPI5_0(%rip), %xmm0 ;CHECK-NEXT: andps .LCPI5_0(%rip), %xmm0
;CHECK-NEXT: retq ;CHECK-NEXT: retq
%1 = and <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0 %1 = and <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
%2 = and <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1 %2 = and <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
%3 = and <4 x i32> %1, %2 %3 = and <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <4 x i32> @or_4i32(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @or_4i32(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @or_4i32 ;CHECK-LABEL: @or_4i32
;CHECK: # BB#0: ;CHECK: # BB#0:
;CHECK-NEXT: orps %xmm1, %xmm0 ;CHECK-NEXT: orps %xmm1, %xmm0
;CHECK-NEXT: orps .LCPI6_0(%rip), %xmm0 ;CHECK-NEXT: orps .LCPI6_0(%rip), %xmm0
;CHECK-NEXT: retq ;CHECK-NEXT: retq
%1 = or <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3> %1 = or <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
%2 = or <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1> %2 = or <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
%3 = or <4 x i32> %1, %2 %3 = or <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <4 x i32> @or_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @or_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @or_4i32_commute ;CHECK-LABEL: @or_4i32_commute
;CHECK: # BB#0: ;CHECK: # BB#0:
;CHECK-NEXT: orps %xmm1, %xmm0 ;CHECK-NEXT: orps %xmm1, %xmm0
;CHECK-NEXT: orps .LCPI7_0(%rip), %xmm0 ;CHECK-NEXT: orps .LCPI7_0(%rip), %xmm0
;CHECK-NEXT: retq ;CHECK-NEXT: retq
%1 = or <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0 %1 = or <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
%2 = or <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1 %2 = or <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
%3 = or <4 x i32> %1, %2 %3 = or <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <4 x i32> @xor_4i32(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @xor_4i32(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @xor_4i32 ;CHECK-LABEL: @xor_4i32
;CHECK: # BB#0: ;CHECK: # BB#0:
;CHECK-NEXT: xorps %xmm1, %xmm0 ;CHECK-NEXT: xorps %xmm1, %xmm0
;CHECK-NEXT: xorps .LCPI8_0(%rip), %xmm0 ;CHECK-NEXT: xorps .LCPI8_0(%rip), %xmm0
;CHECK-NEXT: retq ;CHECK-NEXT: retq
%1 = xor <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3> %1 = xor <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
%2 = xor <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1> %2 = xor <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
%3 = xor <4 x i32> %1, %2 %3 = xor <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <4 x i32> @xor_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @xor_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
;CHECK-LABEL: @xor_4i32_commute ;CHECK-LABEL: @xor_4i32_commute
;CHECK: # BB#0: ;CHECK: # BB#0:
;CHECK-NEXT: xorps %xmm1, %xmm0 ;CHECK-NEXT: xorps %xmm1, %xmm0
;CHECK-NEXT: xorps .LCPI9_0(%rip), %xmm0 ;CHECK-NEXT: xorps .LCPI9_0(%rip), %xmm0
;CHECK-NEXT: retq ;CHECK-NEXT: retq
%1 = xor <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0 %1 = xor <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
%2 = xor <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1 %2 = xor <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
%3 = xor <4 x i32> %1, %2 %3 = xor <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }

test/CodeGen/X86/x86-32-intrcc.ll

; RUN: llc -mtriple=i686-unknown-unknown < %s | FileCheck %s ; RUN: llc -mtriple=i686-unknown-unknown < %s | FileCheck %s
; RUN: llc -mtriple=i686-unknown-unknown -O0 < %s | FileCheck %s -check-prefix=CHECK0 ; RUN: llc -mtriple=i686-unknown-unknown -O0 < %s | FileCheck %s -check-prefix=CHECK0
%struct.interrupt_frame = type { i32, i32, i32, i32, i32 } %struct.interrupt_frame = type { i32, i32, i32, i32, i32 }
@llvm.used = appending global [3 x i8*] [i8* bitcast (void (%struct.interrupt_frame*)* @test_isr_no_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i32)* @test_isr_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i32)* @test_isr_clobbers to i8*)], section "llvm.metadata" @llvm.used = appending global [3 x i8*] [i8* bitcast (void (%struct.interrupt_frame*)* @test_isr_no_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i32)* @test_isr_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i32)* @test_isr_clobbers to i8*)], section "llvm.metadata"
; Spills eax, putting original esp at +4. ; Spills eax, putting original esp at +4.
; No stack adjustment if declared with no error code ; No stack adjustment if declared with no error code
define x86_intrcc void @test_isr_no_ecode(%struct.interrupt_frame* %frame) { define x86_intrcc void @test_isr_no_ecode(%struct.interrupt_frame* %frame) {
; CHECK-LABEL: test_isr_no_ecode: ; CHECK-LABEL: test_isr_no_ecode:
; CHECK: pushl %eax ; CHECK: pushl %eax
; CHECK: movl 12(%esp), %eax ; CHECK: movl 12(%esp), %eax
; CHECK: popl %eax ; CHECK: popl %eax
; CHECK: iretl ; CHECK: iretl
; CHECK0-LABEL: test_isr_no_ecode: ; CHECK0-LABEL: test_isr_no_ecode:
; CHECK0: pushl %eax ; CHECK0: pushl %eax
; CHECK0: leal 4(%esp), %eax ; CHECK0: leal 4(%esp), %eax
; CHECK0: movl 8(%eax), %eax ; CHECK0: movl 8(%eax), %eax
; CHECK0: popl %eax ; CHECK0: popl %eax
; CHECK0: iretl ; CHECK0: iretl
%pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2 %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2
%flags = load i32, i32* %pflags, align 4 %flags = load i32, i32* %pflags, align 4
call void asm sideeffect "", "r"(i32 %flags) call void asm sideeffect "", "r"(i32 %flags)
ret void ret void
} }
; Spills eax and ecx, putting original esp at +8. Stack is adjusted up another 4 bytes ; Spills eax and ecx, putting original esp at +8. Stack is adjusted up another 4 bytes
; before return, popping the error code. ; before return, popping the error code.
define x86_intrcc void @test_isr_ecode(%struct.interrupt_frame* %frame, i32 %ecode) { define x86_intrcc void @test_isr_ecode(%struct.interrupt_frame* %frame, i32 %ecode) {
; CHECK-LABEL: test_isr_ecode ; CHECK-LABEL: test_isr_ecode
; CHECK: pushl %ecx ; CHECK: pushl %ecx
; CHECK: pushl %eax ; CHECK: pushl %eax
; CHECK: movl 8(%esp), %eax ; CHECK: movl 8(%esp), %eax
; CHECK: movl 20(%esp), %ecx ; CHECK: movl 20(%esp), %ecx
; CHECK: popl %eax ; CHECK: popl %eax
; CHECK: popl %ecx ; CHECK: popl %ecx
; CHECK: addl $4, %esp ; CHECK: addl $4, %esp
; CHECK: iretl ; CHECK: iretl
; CHECK0-LABEL: test_isr_ecode ; CHECK0-LABEL: test_isr_ecode
; CHECK0: pushl %ecx ; CHECK0: pushl %ecx
; CHECK0: pushl %eax ; CHECK0: pushl %eax
; CHECK0: movl 8(%esp), %eax ; CHECK0: movl 8(%esp), %eax
; CHECK0: leal 12(%esp), %ecx ; CHECK0: leal 12(%esp), %ecx
; CHECK0: movl 8(%ecx), %ecx ; CHECK0: movl 8(%ecx), %ecx
; CHECK0: popl %eax ; CHECK0: popl %eax
; CHECK0: popl %ecx ; CHECK0: popl %ecx
; CHECK0: addl $4, %esp ; CHECK0: addl $4, %esp
; CHECK0: iretl ; CHECK0: iretl
%pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2 %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2
%flags = load i32, i32* %pflags, align 4 %flags = load i32, i32* %pflags, align 4
call x86_fastcallcc void asm sideeffect "", "r,r"(i32 %flags, i32 %ecode) call x86_fastcallcc void asm sideeffect "", "r,r"(i32 %flags, i32 %ecode)
ret void ret void
} }
; All clobbered registers must be saved ; All clobbered registers must be saved
define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* %frame, i32 %ecode) { define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* %frame, i32 %ecode) {
call void asm sideeffect "", "~{eax},~{ebx},~{ebp}"() call void asm sideeffect "", "~{eax},~{ebx},~{ebp}"()
; CHECK-LABEL: test_isr_clobbers ; CHECK-LABEL: test_isr_clobbers
; CHECK-SSE-NEXT: pushl %ebp ; CHECK-SSE-NEXT: pushl %ebp
; CHECK-SSE-NEXT: pushl %ebx ; CHECK-SSE-NEXT: pushl %ebx
; CHECK-SSE-NEXT; pushl %eax ; CHECK-SSE-NEXT; pushl %eax
; CHECK-SSE-NEXT: popl %eax ; CHECK-SSE-NEXT: popl %eax
; CHECK-SSE-NEXT: popl %ebx ; CHECK-SSE-NEXT: popl %ebx
; CHECK-SSE-NEXT: popl %ebp ; CHECK-SSE-NEXT: popl %ebp
; CHECK-SSE-NEXT: addl $4, %esp ; CHECK-SSE-NEXT: addl $4, %esp
; CHECK-SSE-NEXT: iretl ; CHECK-SSE-NEXT: iretl
; CHECK0-LABEL: test_isr_clobbers ; CHECK0-LABEL: test_isr_clobbers
; CHECK0-SSE-NEXT: pushl %ebp ; CHECK0-SSE-NEXT: pushl %ebp
; CHECK0-SSE-NEXT: pushl %ebx ; CHECK0-SSE-NEXT: pushl %ebx
; CHECK0-SSE-NEXT; pushl %eax ; CHECK0-SSE-NEXT; pushl %eax
; CHECK0-SSE-NEXT: popl %eax ; CHECK0-SSE-NEXT: popl %eax
; CHECK0-SSE-NEXT: popl %ebx ; CHECK0-SSE-NEXT: popl %ebx
; CHECK0-SSE-NEXT: popl %ebp ; CHECK0-SSE-NEXT: popl %ebp
; CHECK0-SSE-NEXT: addl $4, %esp ; CHECK0-SSE-NEXT: addl $4, %esp
; CHECK0-SSE-NEXT: iretl ; CHECK0-SSE-NEXT: iretl
ret void ret void
} }

test/CodeGen/X86/x86-64-intrcc.ll

; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s ; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
; RUN: llc -mtriple=x86_64-unknown-unknown -O0 < %s | FileCheck %s -check-prefix=CHECK0 ; RUN: llc -mtriple=x86_64-unknown-unknown -O0 < %s | FileCheck %s -check-prefix=CHECK0
%struct.interrupt_frame = type { i64, i64, i64, i64, i64 } %struct.interrupt_frame = type { i64, i64, i64, i64, i64 }
@llvm.used = appending global [3 x i8*] [i8* bitcast (void (%struct.interrupt_frame*)* @test_isr_no_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i64)* @test_isr_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i64)* @test_isr_clobbers to i8*)], section "llvm.metadata" @llvm.used = appending global [3 x i8*] [i8* bitcast (void (%struct.interrupt_frame*)* @test_isr_no_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i64)* @test_isr_ecode to i8*), i8* bitcast (void (%struct.interrupt_frame*, i64)* @test_isr_clobbers to i8*)], section "llvm.metadata"
; Spills rax, putting original esp at +8. ; Spills rax, putting original esp at +8.
; No stack adjustment if declared with no error code ; No stack adjustment if declared with no error code
define x86_intrcc void @test_isr_no_ecode(%struct.interrupt_frame* %frame) { define x86_intrcc void @test_isr_no_ecode(%struct.interrupt_frame* %frame) {
; CHECK-LABEL: test_isr_no_ecode: ; CHECK-LABEL: test_isr_no_ecode:
; CHECK: pushq %rax ; CHECK: pushq %rax
; CHECK: movq 24(%rsp), %rax ; CHECK: movq 24(%rsp), %rax
; CHECK: popq %rax ; CHECK: popq %rax
; CHECK: iretq ; CHECK: iretq
; CHECK0-LABEL: test_isr_no_ecode: ; CHECK0-LABEL: test_isr_no_ecode:
; CHECK0: pushq %rax ; CHECK0: pushq %rax
; CHECK0: leaq 8(%rsp), %rax ; CHECK0: leaq 8(%rsp), %rax
; CHECK0: movq 16(%rax), %rax ; CHECK0: movq 16(%rax), %rax
; CHECK0: popq %rax ; CHECK0: popq %rax
; CHECK0: iretq ; CHECK0: iretq
%pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2 %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2
%flags = load i64, i64* %pflags, align 4 %flags = load i64, i64* %pflags, align 4
call void asm sideeffect "", "r"(i64 %flags) call void asm sideeffect "", "r"(i64 %flags)
ret void ret void
} }
; Spills rax and rcx, putting original rsp at +16. Stack is adjusted up another 8 bytes ; Spills rax and rcx, putting original rsp at +16. Stack is adjusted up another 8 bytes
; before return, popping the error code. ; before return, popping the error code.
define x86_intrcc void @test_isr_ecode(%struct.interrupt_frame* %frame, i64 %ecode) { define x86_intrcc void @test_isr_ecode(%struct.interrupt_frame* %frame, i64 %ecode) {
; CHECK-LABEL: test_isr_ecode ; CHECK-LABEL: test_isr_ecode
; CHECK: pushq %rax ; CHECK: pushq %rax
; CHECK: pushq %rcx ; CHECK: pushq %rcx
; CHECK: movq 16(%rsp), %rax ; CHECK: movq 16(%rsp), %rax
; CHECK: movq 40(%rsp), %rcx ; CHECK: movq 40(%rsp), %rcx
; CHECK: popq %rcx ; CHECK: popq %rcx
; CHECK: popq %rax ; CHECK: popq %rax
; CHECK: addq $8, %rsp ; CHECK: addq $8, %rsp
; CHECK: iretq ; CHECK: iretq
; CHECK0-LABEL: test_isr_ecode ; CHECK0-LABEL: test_isr_ecode
; CHECK0: pushq %rax ; CHECK0: pushq %rax
; CHECK0: pushq %rcx ; CHECK0: pushq %rcx
; CHECK0: movq 16(%rsp), %rax ; CHECK0: movq 16(%rsp), %rax
; CHECK0: leaq 24(%rsp), %rcx ; CHECK0: leaq 24(%rsp), %rcx
; CHECK0: movq 16(%rcx), %rcx ; CHECK0: movq 16(%rcx), %rcx
; CHECK0: popq %rcx ; CHECK0: popq %rcx
; CHECK0: popq %rax ; CHECK0: popq %rax
; CHECK0: addq $8, %rsp ; CHECK0: addq $8, %rsp
; CHECK0: iretq ; CHECK0: iretq
%pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2 %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2
%flags = load i64, i64* %pflags, align 4 %flags = load i64, i64* %pflags, align 4
call void asm sideeffect "", "r,r"(i64 %flags, i64 %ecode) call void asm sideeffect "", "r,r"(i64 %flags, i64 %ecode)
ret void ret void
} }
; All clobbered registers must be saved ; All clobbered registers must be saved
define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* %frame, i64 %ecode) { define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* %frame, i64 %ecode) {
call void asm sideeffect "", "~{rax},~{rbx},~{rbp},~{r11},~{xmm0}"() call void asm sideeffect "", "~{rax},~{rbx},~{rbp},~{r11},~{xmm0}"()
; CHECK-LABEL: test_isr_clobbers ; CHECK-LABEL: test_isr_clobbers
; CHECK-SSE-NEXT: pushq %rax ; CHECK-SSE-NEXT: pushq %rax
; CHECK-SSE-NEXT; pushq %r11 ; CHECK-SSE-NEXT; pushq %r11
; CHECK-SSE-NEXT: pushq %rbp ; CHECK-SSE-NEXT: pushq %rbp
; CHECK-SSE-NEXT: pushq %rbx ; CHECK-SSE-NEXT: pushq %rbx
; CHECK-SSE-NEXT: movaps %xmm0 ; CHECK-SSE-NEXT: movaps %xmm0
; CHECK-SSE-NEXT: movaps %xmm0 ; CHECK-SSE-NEXT: movaps %xmm0
; CHECK-SSE-NEXT: popq %rbx ; CHECK-SSE-NEXT: popq %rbx
; CHECK-SSE-NEXT: popq %rbp ; CHECK-SSE-NEXT: popq %rbp
; CHECK-SSE-NEXT: popq %r11 ; CHECK-SSE-NEXT: popq %r11
; CHECK-SSE-NEXT: popq %rax ; CHECK-SSE-NEXT: popq %rax
; CHECK-SSE-NEXT: addq $8, %rsp ; CHECK-SSE-NEXT: addq $8, %rsp
; CHECK-SSE-NEXT: iretq ; CHECK-SSE-NEXT: iretq
; CHECK0-LABEL: test_isr_clobbers ; CHECK0-LABEL: test_isr_clobbers
; CHECK0-SSE-NEXT: pushq %rax ; CHECK0-SSE-NEXT: pushq %rax
; CHECK0-SSE-NEXT; pushq %r11 ; CHECK0-SSE-NEXT; pushq %r11
; CHECK0-SSE-NEXT: pushq %rbp ; CHECK0-SSE-NEXT: pushq %rbp
; CHECK0-SSE-NEXT: pushq %rbx ; CHECK0-SSE-NEXT: pushq %rbx
; CHECK0-SSE-NEXT: movaps %xmm0 ; CHECK0-SSE-NEXT: movaps %xmm0
; CHECK0-SSE-NEXT: movaps %xmm0 ; CHECK0-SSE-NEXT: movaps %xmm0
; CHECK0-SSE-NEXT: popq %rbx ; CHECK0-SSE-NEXT: popq %rbx
; CHECK0-SSE-NEXT: popq %rbp ; CHECK0-SSE-NEXT: popq %rbp
; CHECK0-SSE-NEXT: popq %r11 ; CHECK0-SSE-NEXT: popq %r11
; CHECK0-SSE-NEXT: popq %rax ; CHECK0-SSE-NEXT: popq %rax
; CHECK0-SSE-NEXT: addq $8, %rsp ; CHECK0-SSE-NEXT: addq $8, %rsp
; CHECK0-SSE-NEXT: iretq ; CHECK0-SSE-NEXT: iretq
ret void ret void
} }
No newline at end of file No newline at end of file

test/DebugInfo/Inputs/dwarfdump-macro-cmd.h

#define M4 Value4 #define M4 Value4

test/DebugInfo/Inputs/dwarfdump-macro.h

#undef M1 #undef M1
#define M1 NewValue1 #define M1 NewValue1

test/DebugInfo/Inputs/dwarfdump-macro.cc

#define M1 Value1 #define M1 Value1
#include "dwarfdump-macro.h" #include "dwarfdump-macro.h"
#define M2(x, y) ((x)+(y)* Value2) #define M2(x, y) ((x)+(y)* Value2)
// Built with GCC // Built with GCC
// $ mkdir -p /tmp/dbginfo // $ mkdir -p /tmp/dbginfo
// $ cp dwarfdump-macro.cc /tmp/dbginfo // $ cp dwarfdump-macro.cc /tmp/dbginfo
// $ cp dwarfdump-macro.h /tmp/dbginfo // $ cp dwarfdump-macro.h /tmp/dbginfo
// $ cp dwarfdump-macro-cmd.h /tmp/dbginfo // $ cp dwarfdump-macro-cmd.h /tmp/dbginfo
// $ cd /tmp/dbginfo // $ cd /tmp/dbginfo
// $ g++ -c -g3 -O0 -DM3=Value3 -include dwarfdump-macro-cmd.h dwarfdump-macro.cc -o <output> // $ g++ -c -g3 -O0 -DM3=Value3 -include dwarfdump-macro-cmd.h dwarfdump-macro.cc -o <output>

test/DebugInfo/debugmacinfo.test

RUN: llvm-dwarfdump -debug-dump=macro %p/Inputs/dwarfdump-macro.o \ RUN: llvm-dwarfdump -debug-dump=macro %p/Inputs/dwarfdump-macro.o \
RUN: | FileCheck %s -check-prefix TEST_MACINFO RUN: | FileCheck %s -check-prefix TEST_MACINFO
RUN: llvm-dwarfdump -debug-dump=line %p/Inputs/dwarfdump-macro.o \ RUN: llvm-dwarfdump -debug-dump=line %p/Inputs/dwarfdump-macro.o \
RUN: | FileCheck %s -check-prefix TEST_LINE RUN: | FileCheck %s -check-prefix TEST_LINE
; This test verifies that llvm-dwarfdump tools know how to read .debug_macinfo ; This test verifies that llvm-dwarfdump tools know how to read .debug_macinfo
; section. It also checks that the file numbers fits with those in the ; section. It also checks that the file numbers fits with those in the
; .debug_line section. ; .debug_line section.
TEST_MACINFO: .debug_macinfo contents: TEST_MACINFO: .debug_macinfo contents:
TEST_MACINFO: DW_MACINFO_define - lineno: 0 macro: M3 Value3 TEST_MACINFO: DW_MACINFO_define - lineno: 0 macro: M3 Value3
TEST_MACINFO: DW_MACINFO_start_file - lineno: 0 filenum: 1 TEST_MACINFO: DW_MACINFO_start_file - lineno: 0 filenum: 1
TEST_MACINFO: DW_MACINFO_start_file - lineno: 0 filenum: 2 TEST_MACINFO: DW_MACINFO_start_file - lineno: 0 filenum: 2
TEST_MACINFO: DW_MACINFO_define - lineno: 1 macro: M4 Value4 TEST_MACINFO: DW_MACINFO_define - lineno: 1 macro: M4 Value4
TEST_MACINFO: DW_MACINFO_end_file TEST_MACINFO: DW_MACINFO_end_file
TEST_MACINFO: DW_MACINFO_define - lineno: 1 macro: M1 Value1 TEST_MACINFO: DW_MACINFO_define - lineno: 1 macro: M1 Value1
TEST_MACINFO: DW_MACINFO_start_file - lineno: 2 filenum: 3 TEST_MACINFO: DW_MACINFO_start_file - lineno: 2 filenum: 3
TEST_MACINFO: DW_MACINFO_undef - lineno: 4 macro: M1 TEST_MACINFO: DW_MACINFO_undef - lineno: 4 macro: M1
TEST_MACINFO: DW_MACINFO_define - lineno: 5 macro: M1 NewValue1 TEST_MACINFO: DW_MACINFO_define - lineno: 5 macro: M1 NewValue1
TEST_MACINFO: DW_MACINFO_end_file TEST_MACINFO: DW_MACINFO_end_file
TEST_MACINFO: DW_MACINFO_define - lineno: 3 macro: M2(x,y) ((x)+(y)* Value2) TEST_MACINFO: DW_MACINFO_define - lineno: 3 macro: M2(x,y) ((x)+(y)* Value2)
TEST_MACINFO: DW_MACINFO_end_file TEST_MACINFO: DW_MACINFO_end_file
TEST_LINE: .debug_line contents: TEST_LINE: .debug_line contents:
TEST_LINE: file_names[ 1] 0 0x00000000 0x00000000 dwarfdump-macro.cc TEST_LINE: file_names[ 1] 0 0x00000000 0x00000000 dwarfdump-macro.cc
TEST_LINE: file_names[ 2] 1 0x00000000 0x00000000 dwarfdump-macro-cmd.h TEST_LINE: file_names[ 2] 1 0x00000000 0x00000000 dwarfdump-macro-cmd.h
TEST_LINE: file_names[ 3] 0 0x00000000 0x00000000 dwarfdump-macro.h TEST_LINE: file_names[ 3] 0 0x00000000 0x00000000 dwarfdump-macro.h

test/FileCheck/dos-style-eol.txt

PropertyOld ValueNew Value
svn:eol-stylenullCRLF
\ No newline at end of property
The contents of this file were not changed.

test/JitListener/multiple.ll

; Verify the behavior of the IntelJITEventListener. ; Verify the behavior of the IntelJITEventListener.
; RUN: llvm-jitlistener %s | FileCheck %s ; RUN: llvm-jitlistener %s | FileCheck %s
; This test was created using the following file: ; This test was created using the following file:
; ;
; 1: int foo(int a) { ; 1: int foo(int a) {
; 2: return a; ; 2: return a;
; 3: } ; 3: }
; 4: ; 4:
; 5: int bar(int a) { ; 5: int bar(int a) {
; 6: if (a == 0) { ; 6: if (a == 0) {
; 7: return 0; ; 7: return 0;
; 8: } ; 8: }
; 9: return 100/a; ; 9: return 100/a;
; 10: } ; 10: }
; 11: ; 11:
; 12: int fubar(int a) { ; 12: int fubar(int a) {
; 13: switch (a) { ; 13: switch (a) {
; 14: case 0: ; 14: case 0:
; 15: return 10; ; 15: return 10;
; 16: case 1: ; 16: case 1:
; 17: return 20; ; 17: return 20;
; 18: default: ; 18: default:
; 19: return 30; ; 19: return 30;
; 20: } ; 20: }
; 21: } ; 21: }
; ;
; CHECK: Method load [1]: bar, Size = {{[0-9]+}} ; CHECK: Method load [1]: bar, Size = {{[0-9]+}}
; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[5,6,7,9]}} ; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[5,6,7,9]}}
; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[5,6,7,9]}} ; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[5,6,7,9]}}
; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[5,6,7,9]}} ; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[5,6,7,9]}}
; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[5,6,7,9]}} ; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[5,6,7,9]}}
; CHECK: Method load [2]: foo, Size = {{[0-9]+}} ; CHECK: Method load [2]: foo, Size = {{[0-9]+}}
; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[1,2]}} ; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[1,2]}}
; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[1,2]}} ; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[1,2]}}
; CHECK: Method load [3]: fubar, Size = {{[0-9]+}} ; CHECK: Method load [3]: fubar, Size = {{[0-9]+}}
; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[12,13,15,17,19]}} ; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[12,13,15,17,19]}}
; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[12,13,15,17,19]}} ; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[12,13,15,17,19]}}
; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[12,13,15,17,19]}} ; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[12,13,15,17,19]}}
; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[12,13,15,17,19]}} ; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[12,13,15,17,19]}}
; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[12,13,15,17,19]}} ; CHECK: Line info @ {{[0-9]+}}: multiple.c, line {{[12,13,15,17,19]}}
; CHECK: Method unload [1] ; CHECK: Method unload [1]
; CHECK: Method unload [2] ; CHECK: Method unload [2]
; CHECK: Method unload [3] ; CHECK: Method unload [3]
; ModuleID = 'multiple.c' ; ModuleID = 'multiple.c'
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
define i32 @foo(i32 %a) #0 !dbg !4 { define i32 @foo(i32 %a) #0 !dbg !4 {
entry: entry:
%a.addr = alloca i32, align 4 %a.addr = alloca i32, align 4
▲ Show 20 Lines • Show All 112 Lines • Show Last 20 Lines

test/JitListener/simple.ll

; Verify the behavior of the IntelJITEventListener. ; Verify the behavior of the IntelJITEventListener.
; RUN: llvm-jitlistener %s | FileCheck %s ; RUN: llvm-jitlistener %s | FileCheck %s
; This test was created using the following file: ; This test was created using the following file:
; ;
; 1: int foo(int a) { ; 1: int foo(int a) {
; 2: return a; ; 2: return a;
; 3: } ; 3: }
; ;
; CHECK: Method load [1]: foo, Size = {{[0-9]+}} ; CHECK: Method load [1]: foo, Size = {{[0-9]+}}
; CHECK: Line info @ {{[0-9]+}}: simple.c, line 1 ; CHECK: Line info @ {{[0-9]+}}: simple.c, line 1
; CHECK: Line info @ {{[0-9]+}}: simple.c, line 2 ; CHECK: Line info @ {{[0-9]+}}: simple.c, line 2
; CHECK: Method unload [1] ; CHECK: Method unload [1]
; ModuleID = 'simple.c' ; ModuleID = 'simple.c'
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
define i32 @foo(i32 %a) #0 !dbg !4 { define i32 @foo(i32 %a) #0 !dbg !4 {
entry: entry:
%a.addr = alloca i32, align 4 %a.addr = alloca i32, align 4
Show All 33 Lines

test/MC/ARM/gas-compl-copr-reg.s

@ RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s @ RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s
@ CHECK: ldc p12, c4, [r0, #4] @ encoding: [0x01,0x4c,0x90,0xed] @ CHECK: ldc p12, c4, [r0, #4] @ encoding: [0x01,0x4c,0x90,0xed]
@ CHECK: stc p14, c6, [r2, #-224] @ encoding: [0x38,0x6e,0x02,0xed] @ CHECK: stc p14, c6, [r2, #-224] @ encoding: [0x38,0x6e,0x02,0xed]
ldc p12, cr4, [r0, #4] ldc p12, cr4, [r0, #4]
stc p14, cr6, [r2, #-224] stc p14, cr6, [r2, #-224]
@ RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s @ RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s
@ CHECK: ldc p12, c4, [r0, #4] @ encoding: [0x01,0x4c,0x90,0xed] @ CHECK: ldc p12, c4, [r0, #4] @ encoding: [0x01,0x4c,0x90,0xed]
@ CHECK: stc p14, c6, [r2, #-224] @ encoding: [0x38,0x6e,0x02,0xed] @ CHECK: stc p14, c6, [r2, #-224] @ encoding: [0x38,0x6e,0x02,0xed]
ldc p12, cr4, [r0, #4] ldc p12, cr4, [r0, #4]
stc p14, cr6, [r2, #-224] stc p14, cr6, [r2, #-224]

test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt

# RUN: llvm-mc %s -triple=mips64-unknown-linux -disassemble -mcpu=mips4 | FileCheck %s # RUN: llvm-mc %s -triple=mips64-unknown-linux -disassemble -mcpu=mips4 | FileCheck %s
# XFAIL: * # XFAIL: *
0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15 0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15
0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17 0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17
0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21 0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7 0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7
0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4 0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4
0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3 0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3
0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14 0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14
0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8 0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8
0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23 0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23
0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7 0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7
0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13 0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13
0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31 0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31
0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20 0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20
0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28 0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28
0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7 0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7
0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7 0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7
0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25 0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25
0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25 0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25
0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30 0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30
0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17 0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17
0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10 0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10
0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24 0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24
0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4 0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4
0x4e 0x74 0xd4 0xa1 # CHECK: madd.d $f18, $f19, $f26, $f20 0x4e 0x74 0xd4 0xa1 # CHECK: madd.d $f18, $f19, $f26, $f20
0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25 0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25
0x4c 0x32 0xfa 0xa9 # CHECK: msub.d $f10, $f1, $f31, $f18 0x4c 0x32 0xfa 0xa9 # CHECK: msub.d $f10, $f1, $f31, $f18
0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16 0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16
0x4d 0x33 0x74 0xb1 # CHECK: nmadd.d $f18, $f9, $f14, $f19 0x4d 0x33 0x74 0xb1 # CHECK: nmadd.d $f18, $f9, $f14, $f19
0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4 0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4
0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6 0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6
0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30 0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28 0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28
0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8 0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8

test/MC/Hexagon/test.s

#RUN: llvm-mc -filetype=obj -triple=hexagon -mcpu=hexagonv60 %s #RUN: llvm-mc -filetype=obj -triple=hexagon -mcpu=hexagonv60 %s
{ vmem (r0 + #0) = v0 { vmem (r0 + #0) = v0
r0 = memw(r0) } r0 = memw(r0) }
No newline at end of file No newline at end of file

test/MC/X86/X86_64-pku.s

// RUN: llvm-mc -triple x86_64-unknown-unknown -mattr=+pku --show-encoding < %s | FileCheck %s // RUN: llvm-mc -triple x86_64-unknown-unknown -mattr=+pku --show-encoding < %s | FileCheck %s
// CHECK: rdpkru // CHECK: rdpkru
// CHECK: encoding: [0x0f,0x01,0xee] // CHECK: encoding: [0x0f,0x01,0xee]
rdpkru rdpkru
// CHECK: wrpkru // CHECK: wrpkru
// CHECK: encoding: [0x0f,0x01,0xef] // CHECK: encoding: [0x0f,0x01,0xef]
wrpkru wrpkru
No newline at end of file No newline at end of file

test/Object/Inputs/mri-crlf.mri

PropertyOld ValueNew Value
svn:eol-stylenullCRLF
\ No newline at end of property
The contents of this file were not changed.

test/Transforms/EarlyCSE/AArch64/ldstN.ll

; RUN: opt -S -early-cse < %s | FileCheck %s ; RUN: opt -S -early-cse < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--linux-gnu" target triple = "aarch64--linux-gnu"
declare { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0v4i16(<4 x i16>*) declare { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0v4i16(<4 x i16>*)
; Although the store and the ld4 are using the same pointer, the ; Although the store and the ld4 are using the same pointer, the
; data can not be reused because ld4 accesses multiple elements. ; data can not be reused because ld4 accesses multiple elements.
define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @foo() { define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @foo() {
entry: entry:
store <4 x i16> undef, <4 x i16>* undef, align 8 store <4 x i16> undef, <4 x i16>* undef, align 8
%0 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0v4i16(<4 x i16>* undef) %0 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0v4i16(<4 x i16>* undef)
ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %0 ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %0
; CHECK-LABEL: @foo( ; CHECK-LABEL: @foo(
; CHECK: store ; CHECK: store
; CHECK-NEXT: call ; CHECK-NEXT: call
; CHECK-NEXT: ret ; CHECK-NEXT: ret
} }

test/Transforms/PlaceSafepoints/statepoint-coreclr.ll

; RUN: opt %s -S -place-safepoints | FileCheck %s ; RUN: opt %s -S -place-safepoints | FileCheck %s
; Basic test to make sure that safepoints are placed ; Basic test to make sure that safepoints are placed
; for CoreCLR GC ; for CoreCLR GC
declare void @foo() declare void @foo()
define void @test_simple_call() gc "coreclr" { define void @test_simple_call() gc "coreclr" {
; CHECK-LABEL: test_simple_call ; CHECK-LABEL: test_simple_call
entry: entry:
br label %other br label %other
other: other:
; CHECK-LABEL: other ; CHECK-LABEL: other
; CHECK: statepoint ; CHECK: statepoint
; CHECK-NOT: gc.result ; CHECK-NOT: gc.result
call void @foo() call void @foo()
ret void ret void
} }
; This function is inlined when inserting a poll. To avoid recursive ; This function is inlined when inserting a poll. To avoid recursive
; issues, make sure we don't place safepoints in it. ; issues, make sure we don't place safepoints in it.
declare void @do_safepoint() declare void @do_safepoint()
define void @gc.safepoint_poll() { define void @gc.safepoint_poll() {
; CHECK-LABEL: gc.safepoint_poll ; CHECK-LABEL: gc.safepoint_poll
; CHECK-LABEL: entry ; CHECK-LABEL: entry
; CHECK-NEXT: do_safepoint ; CHECK-NEXT: do_safepoint
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
entry: entry:
call void @do_safepoint() call void @do_safepoint()
ret void ret void
} }

test/tools/llvm-pdbdump/Inputs/ClassLayoutTest.cpp

// Compile with "cl /c /Zi /GR- ClassLayoutTest.cpp" // Compile with "cl /c /Zi /GR- ClassLayoutTest.cpp"
// Link with "link ClassLayoutTest.obj /debug /nodefaultlib /entry:main" // Link with "link ClassLayoutTest.obj /debug /nodefaultlib /entry:main"
namespace MembersTest { namespace MembersTest {
class A { class A {
public: public:
typedef int NestedTypedef; typedef int NestedTypedef;
enum NestedEnum { enum NestedEnum {
NestedEnumValue1 NestedEnumValue1
}; };
void MemberFunc() {} void MemberFunc() {}
private: private:
int IntMemberVar; int IntMemberVar;
double DoubleMemberVar; double DoubleMemberVar;
}; };
} }
namespace GlobalsTest { namespace GlobalsTest {
int IntVar; int IntVar;
double DoubleVar; double DoubleVar;
typedef int Typedef; typedef int Typedef;
enum Enum { enum Enum {
Val1 Val1
} EnumVar; } EnumVar;
Typedef TypedefVar; Typedef TypedefVar;
} }
namespace BaseClassTest { namespace BaseClassTest {
class A {}; class A {};
class B : public virtual A {}; class B : public virtual A {};
class C : public virtual A {}; class C : public virtual A {};
class D : protected B, private C {}; class D : protected B, private C {};
} }
namespace UdtKindTest { namespace UdtKindTest {
struct A {}; struct A {};
class B {}; class B {};
union C {}; union C {};
} }
namespace BitFieldTest { namespace BitFieldTest {
struct A { struct A {
int Bits1 : 1; int Bits1 : 1;
int Bits2 : 2; int Bits2 : 2;
int Bits3 : 3; int Bits3 : 3;
int Bits4 : 4; int Bits4 : 4;
int Bits22 : 22; int Bits22 : 22;
int Offset0x04; int Offset0x04;
}; };
}; };
int main(int argc, char **argv) { int main(int argc, char **argv) {
MembersTest::A v1; MembersTest::A v1;
v1.MemberFunc(); v1.MemberFunc();
BaseClassTest::D v2; BaseClassTest::D v2;
UdtKindTest::A v3; UdtKindTest::A v3;
UdtKindTest::B v4; UdtKindTest::B v4;
UdtKindTest::C v5; UdtKindTest::C v5;
BitFieldTest::A v7; BitFieldTest::A v7;
return 0; return 0;
} }

test/tools/llvm-pdbdump/Inputs/FilterTest.cpp

// Compile with "cl /c /Zi /GR- FilterTest.cpp" // Compile with "cl /c /Zi /GR- FilterTest.cpp"
// Link with "link FilterTest.obj /debug /nodefaultlib /entry:main" // Link with "link FilterTest.obj /debug /nodefaultlib /entry:main"
class FilterTestClass { class FilterTestClass {
public: public:
typedef int NestedTypedef; typedef int NestedTypedef;
enum NestedEnum { enum NestedEnum {
NestedEnumValue1 NestedEnumValue1
}; };
void MemberFunc() {} void MemberFunc() {}
private: private:
int IntMemberVar; int IntMemberVar;
double DoubleMemberVar; double DoubleMemberVar;
}; };
int IntGlobalVar; int IntGlobalVar;
double DoubleGlobalVar; double DoubleGlobalVar;
typedef int GlobalTypedef; typedef int GlobalTypedef;
enum GlobalEnum { enum GlobalEnum {
GlobalEnumVal1 GlobalEnumVal1
} GlobalEnumVar; } GlobalEnumVar;
int main(int argc, char **argv) { int main(int argc, char **argv) {
FilterTestClass TestClass; FilterTestClass TestClass;
GlobalTypedef v1; GlobalTypedef v1;
return 0; return 0;
} }

test/tools/llvm-pdbdump/Inputs/LoadAddressTest.cpp

// Compile with "cl /c /Zi /GR- LoadAddressTest.cpp" // Compile with "cl /c /Zi /GR- LoadAddressTest.cpp"
// Link with "link LoadAddressTest.obj /debug /nodefaultlib /entry:main" // Link with "link LoadAddressTest.obj /debug /nodefaultlib /entry:main"
int main(int argc, char **argv) { int main(int argc, char **argv) {
return 0; return 0;
} }

test/tools/llvm-pdbdump/class-layout.test

; RUN: llvm-pdbdump -all %p/Inputs/ClassLayoutTest.pdb > %t ; RUN: llvm-pdbdump -all %p/Inputs/ClassLayoutTest.pdb > %t
; RUN: FileCheck -input-file=%t %s -check-prefix=GLOBALS_TEST ; RUN: FileCheck -input-file=%t %s -check-prefix=GLOBALS_TEST
; RUN: FileCheck -input-file=%t %s -check-prefix=MEMBERS_TEST ; RUN: FileCheck -input-file=%t %s -check-prefix=MEMBERS_TEST
; RUN: FileCheck -input-file=%t %s -check-prefix=BASE_CLASS_A ; RUN: FileCheck -input-file=%t %s -check-prefix=BASE_CLASS_A
; RUN: FileCheck -input-file=%t %s -check-prefix=BASE_CLASS_B ; RUN: FileCheck -input-file=%t %s -check-prefix=BASE_CLASS_B
; RUN: FileCheck -input-file=%t %s -check-prefix=BASE_CLASS_C ; RUN: FileCheck -input-file=%t %s -check-prefix=BASE_CLASS_C
; RUN: FileCheck -input-file=%t %s -check-prefix=BASE_CLASS_D ; RUN: FileCheck -input-file=%t %s -check-prefix=BASE_CLASS_D
; RUN: FileCheck -input-file=%t %s -check-prefix=UDT_KIND_TEST ; RUN: FileCheck -input-file=%t %s -check-prefix=UDT_KIND_TEST
; RUN: FileCheck -input-file=%t %s -check-prefix=BITFIELD_TEST ; RUN: FileCheck -input-file=%t %s -check-prefix=BITFIELD_TEST
; GLOBALS_TEST: ---GLOBALS--- ; GLOBALS_TEST: ---GLOBALS---
; GLOBALS_TEST-DAG: int GlobalsTest::IntVar ; GLOBALS_TEST-DAG: int GlobalsTest::IntVar
; GLOBALS_TEST-DAG: double GlobalsTest::DoubleVar ; GLOBALS_TEST-DAG: double GlobalsTest::DoubleVar
; GLOBALS_TEST-DAG: GlobalsTest::Enum GlobalsTest::EnumVar ; GLOBALS_TEST-DAG: GlobalsTest::Enum GlobalsTest::EnumVar
; MEMBERS_TEST: ---TYPES--- ; MEMBERS_TEST: ---TYPES---
; MEMBERS_TEST: class MembersTest::A { ; MEMBERS_TEST: class MembersTest::A {
; MEMBERS_TEST-DAG: typedef int NestedTypedef ; MEMBERS_TEST-DAG: typedef int NestedTypedef
; MEMBERS_TEST-DAG: enum NestedEnum ; MEMBERS_TEST-DAG: enum NestedEnum
; MEMBERS_TEST: public: ; MEMBERS_TEST: public:
; MEMBERS_TEST-NEXT: void MemberFunc() ; MEMBERS_TEST-NEXT: void MemberFunc()
; MEMBERS_TEST-NEXT: private: ; MEMBERS_TEST-NEXT: private:
; MEMBERS_TEST-DAG: int IntMemberVar ; MEMBERS_TEST-DAG: int IntMemberVar
; MEMBERS_TEST-DAG: double DoubleMemberVar ; MEMBERS_TEST-DAG: double DoubleMemberVar
; MEMBERS_TEST: } ; MEMBERS_TEST: }
; BASE_CLASS_A: ---TYPES--- ; BASE_CLASS_A: ---TYPES---
; BASE_CLASS_A: class BaseClassTest::A {} ; BASE_CLASS_A: class BaseClassTest::A {}
; BASE_CLASS_B: ---TYPES--- ; BASE_CLASS_B: ---TYPES---
; BASE_CLASS_B: class BaseClassTest::B ; BASE_CLASS_B: class BaseClassTest::B
; BASE_CLASS_B-NEXT: : public virtual BaseClassTest::A { ; BASE_CLASS_B-NEXT: : public virtual BaseClassTest::A {
; BASE_CLASS_C: ---TYPES--- ; BASE_CLASS_C: ---TYPES---
; BASE_CLASS_C: class BaseClassTest::C ; BASE_CLASS_C: class BaseClassTest::C
; BASE_CLASS_C-NEXT: : public virtual BaseClassTest::A { ; BASE_CLASS_C-NEXT: : public virtual BaseClassTest::A {
; BASE_CLASS_D: ---TYPES--- ; BASE_CLASS_D: ---TYPES---
; BASE_CLASS_D: class BaseClassTest::D ; BASE_CLASS_D: class BaseClassTest::D
; BASE_CLASS_D-DAG: protected BaseClassTest::B ; BASE_CLASS_D-DAG: protected BaseClassTest::B
; BASE_CLASS_D-DAG: private BaseClassTest::C ; BASE_CLASS_D-DAG: private BaseClassTest::C
; BASE_CLASS_D-DAG: protected virtual BaseClassTest::A ; BASE_CLASS_D-DAG: protected virtual BaseClassTest::A
; UDT_KIND_TEST: ---TYPES--- ; UDT_KIND_TEST: ---TYPES---
; UDT_KIND_TEST-DAG: union UdtKindTest::C {} ; UDT_KIND_TEST-DAG: union UdtKindTest::C {}
; UDT_KIND_TEST-DAG: class UdtKindTest::B {} ; UDT_KIND_TEST-DAG: class UdtKindTest::B {}
; UDT_KIND_TEST-DAG: struct UdtKindTest::A {} ; UDT_KIND_TEST-DAG: struct UdtKindTest::A {}
; BITFIELD_TEST: ---TYPES--- ; BITFIELD_TEST: ---TYPES---
; BITFIELD_TEST: struct BitFieldTest::A { ; BITFIELD_TEST: struct BitFieldTest::A {
; BITFIELD_TEST-NEXT: public: ; BITFIELD_TEST-NEXT: public:
; BITFIELD_TEST-NEXT: +0x00 int Bits1 : 1 ; BITFIELD_TEST-NEXT: +0x00 int Bits1 : 1
; BITFIELD_TEST-NEXT: +0x00 int Bits2 : 2 ; BITFIELD_TEST-NEXT: +0x00 int Bits2 : 2
; BITFIELD_TEST-NEXT: +0x00 int Bits3 : 3 ; BITFIELD_TEST-NEXT: +0x00 int Bits3 : 3
; BITFIELD_TEST-NEXT: +0x00 int Bits4 : 4 ; BITFIELD_TEST-NEXT: +0x00 int Bits4 : 4
; BITFIELD_TEST-NEXT: +0x00 int Bits22 : 22 ; BITFIELD_TEST-NEXT: +0x00 int Bits22 : 22
; BITFIELD_TEST-NEXT: +0x04 int Offset0x04 ; BITFIELD_TEST-NEXT: +0x04 int Offset0x04

test/tools/llvm-pdbdump/enum-layout.test

; RUN: llvm-pdbdump -types %p/Inputs/ClassLayoutTest.pdb > %t ; RUN: llvm-pdbdump -types %p/Inputs/ClassLayoutTest.pdb > %t
; RUN: FileCheck -input-file=%t %s -check-prefix=GLOBAL_ENUM ; RUN: FileCheck -input-file=%t %s -check-prefix=GLOBAL_ENUM
; RUN: FileCheck -input-file=%t %s -check-prefix=MEMBER_ENUM ; RUN: FileCheck -input-file=%t %s -check-prefix=MEMBER_ENUM
; GLOBAL_ENUM: ---TYPES--- ; GLOBAL_ENUM: ---TYPES---
; GLOBAL_ENUM: Enums: ; GLOBAL_ENUM: Enums:
; GLOBAL_ENUM: enum GlobalsTest::Enum { ; GLOBAL_ENUM: enum GlobalsTest::Enum {
; GLOBAL_ENUM-NEXT: Val1 = 0 ; GLOBAL_ENUM-NEXT: Val1 = 0
; GLOBAL_ENUM-NEXT: } ; GLOBAL_ENUM-NEXT: }
; MEMBER_ENUM: ---TYPES--- ; MEMBER_ENUM: ---TYPES---
; MEMBER_ENUM: Classes: ; MEMBER_ENUM: Classes:
; MEMBER_ENUM: struct __vc_attributes::threadingAttribute { ; MEMBER_ENUM: struct __vc_attributes::threadingAttribute {
; MEMBER_ENUM-NEXT: enum threading_e { ; MEMBER_ENUM-NEXT: enum threading_e {
; MEMBER_ENUM-NEXT: apartment = 1 ; MEMBER_ENUM-NEXT: apartment = 1
; MEMBER_ENUM-NEXT: single = 2 ; MEMBER_ENUM-NEXT: single = 2
; MEMBER_ENUM-NEXT: free = 3 ; MEMBER_ENUM-NEXT: free = 3
; MEMBER_ENUM-NEXT: neutral = 4 ; MEMBER_ENUM-NEXT: neutral = 4
; MEMBER_ENUM-NEXT: both = 5 ; MEMBER_ENUM-NEXT: both = 5
; MEMBER_ENUM-NEXT: } ; MEMBER_ENUM-NEXT: }

test/tools/llvm-pdbdump/load-address.test

; RUN: llvm-pdbdump -externals %p/Inputs/LoadAddressTest.pdb \ ; RUN: llvm-pdbdump -externals %p/Inputs/LoadAddressTest.pdb \
; RUN: | FileCheck --check-prefix=RVA %s ; RUN: | FileCheck --check-prefix=RVA %s
; RUN: llvm-pdbdump -externals -load-address=0x40000000 \ ; RUN: llvm-pdbdump -externals -load-address=0x40000000 \
; RUN: %p/Inputs/LoadAddressTest.pdb | FileCheck --check-prefix=VA %s ; RUN: %p/Inputs/LoadAddressTest.pdb | FileCheck --check-prefix=VA %s
; RVA: ---EXTERNALS--- ; RVA: ---EXTERNALS---
; RVA: [0x00001010] _main ; RVA: [0x00001010] _main
; VA: ---EXTERNALS--- ; VA: ---EXTERNALS---
; VA: [0x40001010] _main ; VA: [0x40001010] _main

test/tools/llvm-symbolizer/pdb/lit.local.cfg

config.unsupported = not config.have_dia_sdk config.unsupported = not config.have_dia_sdk

unittests/IR/TypesTest.cpp

Show All 21 LinesTEST(TypesTest, StructType) {
EXPECT_EQ("FooBar", Struct->getName()); EXPECT_EQ("FooBar", Struct->getName());
Struct->setName(Struct->getName().substr(0, 3)); Struct->setName(Struct->getName().substr(0, 3));
EXPECT_EQ("Foo", Struct->getName()); EXPECT_EQ("Foo", Struct->getName());
Struct->setName(""); Struct->setName("");
EXPECT_TRUE(Struct->getName().empty()); EXPECT_TRUE(Struct->getName().empty());
EXPECT_FALSE(Struct->hasName()); EXPECT_FALSE(Struct->hasName());
} }
TEST(TypesTest, LayoutIdenticalEmptyStructs) { TEST(TypesTest, LayoutIdenticalEmptyStructs) {
LLVMContext C; LLVMContext C;
StructType *Foo = StructType::create(C, "Foo"); StructType *Foo = StructType::create(C, "Foo");
StructType *Bar = StructType::create(C, "Bar"); StructType *Bar = StructType::create(C, "Bar");
EXPECT_TRUE(Foo->isLayoutIdentical(Bar)); EXPECT_TRUE(Foo->isLayoutIdentical(Bar));
} }
} // end anonymous namespace } // end anonymous namespace