[InstCombine] Improve logic for adding flags to shift instructions.

[goldstein.w.n]

Summary

Instead of relying on constant operands, use known bits to do the
computation.

Proofs: https://alive2.llvm.org/ce/z/M-aBnw

[goldstein.w.n]

moving to gh.

llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp

if (!Add->hasOneUse()) {
     replaceInstUsesWith(*AddInst, Builder.CreateZExt(NarrowAdd, Ty));
     eraseInstFromFunction(*AddInst);
   }
 
   // Replace the LShr with a zext of the overflow check.
   return new ZExtInst(Overflow, Ty);
 }
 
+// Try to set nuw/nsw flags on shl or exact flag on lshr/ashr using knownbits.
+static bool setShiftFlags(BinaryOperator &I, const SimplifyQuery &Q) {
+  // We already have all the flags.
+  if (I.getOpcode() == Instruction::Shl) {
+    if (I.hasNoUnsignedWrap() && I.hasNoSignedWrap())
+      return false;
+  } else {
+    if (I.isExact())
+      return false;
+  }
+
+  // Compute what we know about shift count.
+  KnownBits KnownCnt =
+      computeKnownBits(I.getOperand(1), Q.DL, /*Depth*/ 0, Q.AC, Q.CxtI, Q.DT);
+  // If we know nothing about shift count or its a poison shift, we won't be
+  // able to prove anything so return before computing shift amount.
+  if (KnownCnt.isUnknown())
+    return false;
+  unsigned BitWidth = KnownCnt.getBitWidth();
+  APInt MaxCnt = KnownCnt.getMaxValue();
+  if (MaxCnt.uge(BitWidth))
+    return false;
+
+  KnownBits KnownAmt =
+      computeKnownBits(I.getOperand(0), Q.DL, /*Depth*/ 0, Q.AC, Q.CxtI, Q.DT);
+  bool Changed = false;
+
+  if (I.getOpcode() == Instruction::Shl) {
+    // If we have as many leading zeros than maximum shift cnt we have nuw.
+    if (!I.hasNoUnsignedWrap() && MaxCnt.ule(KnownAmt.countMinLeadingZeros())) {
+      I.setHasNoUnsignedWrap();
+      Changed = true;
+    }
+    // If we have more sign bits than maximum shift cnt we have nsw.
+    if (!I.hasNoSignedWrap()) {
+      if (MaxCnt.ult(KnownAmt.countMinSignBits()) ||
+          MaxCnt.ult(ComputeNumSignBits(I.getOperand(0), Q.DL, /*Depth*/ 0,
+                                        Q.AC, Q.CxtI, Q.DT))) {
+        I.setHasNoSignedWrap();
+        Changed = true;
+      }
+    }
+    return Changed;
+  }
+  if (!I.isExact()) {
+    // If we have at least as many trailing zeros as maximum count then we have
+    // exact.
+    Changed = MaxCnt.ule(KnownAmt.countMinTrailingZeros());
+    I.setIsExact(Changed);
+  }
+  return Changed;
+}
+
 Instruction *InstCombinerImpl::visitShl(BinaryOperator &I) {
   const SimplifyQuery Q = SQ.getWithInstruction(&I);
 
   if (Value *V = simplifyShlInst(I.getOperand(0), I.getOperand(1),
                                  I.hasNoSignedWrap(), I.hasNoUnsignedWrap(), Q))
     return replaceInstUsesWith(I, V);
 
   if (Instruction *X = foldVectorBinop(I))
if (match(Op1, m_APInt(C))) {
     }
 
     // (C1 - X) << C --> (C1 << C) - (X << C)
     if (match(Op0, m_OneUse(m_Sub(m_APInt(C1), m_Value(X))))) {
       Constant *NewLHS = ConstantInt::get(Ty, C1->shl(*C));
       Value *NewShift = Builder.CreateShl(X, Op1);
       return BinaryOperator::CreateSub(NewLHS, NewShift);
     }
-
-    // If the shifted-out value is known-zero, then this is a NUW shift.
-    if (!I.hasNoUnsignedWrap() &&
-        MaskedValueIsZero(Op0, APInt::getHighBitsSet(BitWidth, ShAmtC), 0,
-                          &I)) {
-      I.setHasNoUnsignedWrap();
-      return &I;
-    }
 
-    // If the shifted-out value is all signbits, then this is a NSW shift.
-    if (!I.hasNoSignedWrap() && ComputeNumSignBits(Op0, 0, &I) > ShAmtC) {
-      I.setHasNoSignedWrap();
-      return &I;
-    }
-  }
+  if (setShiftFlags(I, Q))
 
   // Transform  (x >> y) << y  to  x & (-1 << y)
   // Valid for any type of right-shift.
   Value *X;
   if (match(Op0, m_OneUse(m_Shr(m_Value(X), m_Specific(Op1))))) {
     Constant *AllOnes = ConstantInt::getAllOnesValue(Ty);
     Value *Mask = Builder.CreateShl(AllOnes, Op1);
     return BinaryOperator::CreateAnd(Mask, X);
if (match(Op1, m_APInt(C))) {
     if (ShAmtC == 1 && match(Op0, m_Add(m_Value(X), m_Value(Y))) &&
         match(X, m_ZExt(m_Value(BoolX))) && match(Y, m_ZExt(m_Value(BoolY))) &&
         BoolX->getType()->isIntOrIntVectorTy(1) &&
         BoolY->getType()->isIntOrIntVectorTy(1) &&
         (X->hasOneUse() || Y->hasOneUse() || Op0->hasOneUse())) {
       Value *And = Builder.CreateAnd(BoolX, BoolY);
       return new ZExtInst(And, Ty);
     }
+  }
 
-    // If the shifted-out value is known-zero, then this is an exact shift.
-    if (!I.isExact() &&
-        MaskedValueIsZero(Op0, APInt::getLowBitsSet(BitWidth, ShAmtC), 0, &I)) {
-      I.setIsExact();
-      return &I;
-    }
-  }
+  const SimplifyQuery Q = SQ.getWithInstruction(&I);
+  if (setShiftFlags(I, Q))
 
   // Transform  (x << y) >> y  to  x & (-1 >> y)
   if (match(Op0, m_OneUse(m_Shl(m_Value(X), m_Specific(Op1))))) {
     Constant *AllOnes = ConstantInt::getAllOnesValue(Ty);
     Value *Mask = Builder.CreateLShr(AllOnes, Op1);
     return BinaryOperator::CreateAnd(Mask, X);
   }
 
if (ShAmt == BitWidth - 1) {
       if (match(Op0, m_OneUse(m_c_Or(m_Neg(m_Value(X)), m_Deferred(X)))))
         return new SExtInst(Builder.CreateIsNotNull(X), Ty);
 
       // ashr i32 (X -nsw Y), 31 --> sext (X < Y)
       Value *Y;
       if (match(Op0, m_OneUse(m_NSWSub(m_Value(X), m_Value(Y)))))
         return new SExtInst(Builder.CreateICmpSLT(X, Y), Ty);
     }
+  }
 
-    // If the shifted-out value is known-zero, then this is an exact shift.
-    if (!I.isExact() &&
-        MaskedValueIsZero(Op0, APInt::getLowBitsSet(BitWidth, ShAmt), 0, &I)) {
-      I.setIsExact();
-      return &I;
-    }
-  }
+  const SimplifyQuery Q = SQ.getWithInstruction(&I);
+  if (setShiftFlags(I, Q))
 
   // Prefer `-(x & 1)` over `(x << (bitwidth(x)-1)) a>> (bitwidth(x)-1)`
   // as the pattern to splat the lowest bit.
   // FIXME: iff X is already masked, we don't need the one-use check.
   Value *X;
   if (match(Op1, m_SpecificIntAllowUndef(BitWidth - 1)) &&
       match(Op0, m_OneUse(m_Shl(m_Value(X),
                                 m_SpecificIntAllowUndef(BitWidth - 1))))) {

llvm/test/Analysis/ValueTracking/known-power-of-two.ll

;
   ret i16 %r
 }
 
 define i1 @mul_is_pow2(i16 %x, i16 %y, i16 %z) {
 ; CHECK-LABEL: define i1 @mul_is_pow2
 ; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]], i16 [[Z:%.*]]) {
 ; CHECK-NEXT:    [[XSMALL:%.*]] = and i16 [[X]], 3
 ; CHECK-NEXT:    [[ZSMALL:%.*]] = and i16 [[Z]], 3
-; CHECK-NEXT:    [[XP2:%.*]] = shl i16 4, [[XSMALL]]
-; CHECK-NEXT:    [[ZP2:%.*]] = shl i16 2, [[ZSMALL]]
-; CHECK-NEXT:    [[XX:%.*]] = mul nuw nsw i16 [[XP2]], [[ZP2]]
+; CHECK-NEXT:    [[ZP2:%.*]] = shl nuw nsw i16 2, [[ZSMALL]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add nuw nsw i16 [[XSMALL]], 2
+; CHECK-NEXT:    [[XX:%.*]] = shl nuw nsw i16 [[ZP2]], [[TMP1]]
 ; CHECK-NEXT:    [[AND:%.*]] = and i16 [[XX]], [[Y]]
-; CHECK-NEXT:    [[R:%.*]] = icmp eq i16 [[AND]], [[XX]]
+; CHECK-NEXT:    [[R:%.*]] = icmp ne i16 [[AND]], 0
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %xsmall = and i16 %x, 3
   %zsmall = and i16 %z, 3
   %xp2 = shl i16 4, %xsmall
   %zp2 = shl i16 2, %zsmall
   %xx = mul i16 %xp2, %zp2
 
   %and = and i16 %y, %xx
   %r = icmp eq i16 %and, %xx
   ret i1 %r
 }
 
 define i1 @mul_is_pow2_fail(i16 %x, i16 %y, i16 %z) {
 ; CHECK-LABEL: define i1 @mul_is_pow2_fail
 ; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]], i16 [[Z:%.*]]) {
 ; CHECK-NEXT:    [[XSMALL:%.*]] = and i16 [[X]], 7
 ; CHECK-NEXT:    [[ZSMALL:%.*]] = and i16 [[Z]], 7
-; CHECK-NEXT:    [[XP2:%.*]] = shl i16 4, [[XSMALL]]
-; CHECK-NEXT:    [[ZP2:%.*]] = shl i16 2, [[ZSMALL]]
-; CHECK-NEXT:    [[XX:%.*]] = mul i16 [[XP2]], [[ZP2]]
+; CHECK-NEXT:    [[ZP2:%.*]] = shl nuw nsw i16 2, [[ZSMALL]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add nuw nsw i16 [[XSMALL]], 2
+; CHECK-NEXT:    [[XX:%.*]] = shl i16 [[ZP2]], [[TMP1]]
 ; CHECK-NEXT:    [[AND:%.*]] = and i16 [[XX]], [[Y]]
 ; CHECK-NEXT:    [[R:%.*]] = icmp eq i16 [[AND]], [[XX]]
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %xsmall = and i16 %x, 7
   %zsmall = and i16 %z, 7
   %xp2 = shl i16 4, %xsmall
   %zp2 = shl i16 2, %zsmall
   %xx = mul i16 %xp2, %zp2
 
   %and = and i16 %y, %xx
   %r = icmp eq i16 %and, %xx
   ret i1 %r
 }
 
 define i1 @mul_is_pow2_fail2(i16 %x, i16 %y, i16 %z) {
 ; CHECK-LABEL: define i1 @mul_is_pow2_fail2
 ; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]], i16 [[Z:%.*]]) {
 ; CHECK-NEXT:    [[XSMALL:%.*]] = and i16 [[X]], 3
 ; CHECK-NEXT:    [[ZSMALL:%.*]] = and i16 [[Z]], 3
-; CHECK-NEXT:    [[XP2:%.*]] = shl i16 3, [[XSMALL]]
-; CHECK-NEXT:    [[ZP2:%.*]] = shl i16 2, [[ZSMALL]]
-; CHECK-NEXT:    [[XX:%.*]] = mul nuw nsw i16 [[XP2]], [[ZP2]]
+; CHECK-NEXT:    [[XP2:%.*]] = shl nuw nsw i16 3, [[XSMALL]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add nuw nsw i16 [[ZSMALL]], 1
+; CHECK-NEXT:    [[XX:%.*]] = shl nuw nsw i16 [[XP2]], [[TMP1]]
 ; CHECK-NEXT:    [[AND:%.*]] = and i16 [[XX]], [[Y]]
 ; CHECK-NEXT:    [[R:%.*]] = icmp eq i16 [[AND]], [[XX]]
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %xsmall = and i16 %x, 3
   %zsmall = and i16 %z, 3
   %xp2 = shl i16 3, %xsmall
   %zp2 = shl i16 2, %zsmall
   %xx = mul i16 %xp2, %zp2
 
   %and = and i16 %y, %xx
   %r = icmp eq i16 %and, %xx
   ret i1 %r
 }
 
 define i1 @shl_is_pow2(i16 %x, i16 %y) {
 ; CHECK-LABEL: define i1 @shl_is_pow2
 ; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]]) {
 ; CHECK-NEXT:    [[XSMALL:%.*]] = and i16 [[X]], 7
-; CHECK-NEXT:    [[XX:%.*]] = shl i16 4, [[XSMALL]]
+; CHECK-NEXT:    [[XX:%.*]] = shl nuw nsw i16 4, [[XSMALL]]
 ; CHECK-NEXT:    [[AND:%.*]] = and i16 [[XX]], [[Y]]
-; CHECK-NEXT:    [[R:%.*]] = icmp eq i16 [[AND]], [[XX]]
+; CHECK-NEXT:    [[R:%.*]] = icmp ne i16 [[AND]], 0
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %xsmall = and i16 %x, 7
   %xx = shl i16 4, %xsmall
 
   %and = and i16 %y, %xx
   %r = icmp eq i16 %and, %xx
   ret i1 %r
;
   %r = icmp eq i16 %and, %xx
   ret i1 %r
 }
 
 define i1 @shl_is_pow2_fail2(i16 %x, i16 %y) {
 ; CHECK-LABEL: define i1 @shl_is_pow2_fail2
 ; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]]) {
 ; CHECK-NEXT:    [[XSMALL:%.*]] = and i16 [[X]], 7
-; CHECK-NEXT:    [[XX:%.*]] = shl i16 5, [[XSMALL]]
+; CHECK-NEXT:    [[XX:%.*]] = shl nuw nsw i16 5, [[XSMALL]]
 ; CHECK-NEXT:    [[AND:%.*]] = and i16 [[XX]], [[Y]]
 ; CHECK-NEXT:    [[R:%.*]] = icmp eq i16 [[AND]], [[XX]]
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %xsmall = and i16 %x, 7
   %xx = shl i16 5, %xsmall
 
   %and = and i16 %y, %xx
   %r = icmp eq i16 %and, %xx
   ret i1 %r
 }
 
 define i1 @lshr_is_pow2(i16 %x, i16 %y) {
 ; CHECK-LABEL: define i1 @lshr_is_pow2
 ; CHECK-SAME: (i16 [[X:%.*]], i16 [[Y:%.*]]) {
 ; CHECK-NEXT:    [[XSMALL:%.*]] = and i16 [[X]], 7
-; CHECK-NEXT:    [[XX:%.*]] = lshr i16 512, [[XSMALL]]
+; CHECK-NEXT:    [[XX:%.*]] = lshr exact i16 512, [[XSMALL]]
 ; CHECK-NEXT:    [[AND:%.*]] = and i16 [[XX]], [[Y]]
-; CHECK-NEXT:    [[R:%.*]] = icmp eq i16 [[AND]], [[XX]]
+; CHECK-NEXT:    [[R:%.*]] = icmp ne i16 [[AND]], 0
 ; CHECK-NEXT:    ret i1 [[R]]
 ;
   %xsmall = and i16 %x, 7
   %xx = lshr i16 512, %xsmall
 
   %and = and i16 %y, %xx
   %r = icmp eq i16 %and, %xx
   ret i1 %r

llvm/test/Transforms/InstCombine/and-add-shl.ll

 }
 
 ; https://alive2.llvm.org/ce/z/YNYYdV
 define i8 @and_not_shl(i8 %x) {
 ; CHECK-LABEL: define i8 @and_not_shl
 ; CHECK-SAME: (i8 [[X:%.*]]) {
 ; CHECK-NEXT:    [[OP1_P2:%.*]] = icmp ult i8 [[X]], 6
 ; CHECK-NEXT:    call void @llvm.assume(i1 [[OP1_P2]])
-; CHECK-NEXT:    [[SHIFT:%.*]] = shl i8 -1, [[X]]
+; CHECK-NEXT:    [[SHIFT:%.*]] = shl nsw i8 -1, [[X]]
 ; CHECK-NEXT:    [[NOT:%.*]] = and i8 [[SHIFT]], 32
 ; CHECK-NEXT:    [[R:%.*]] = xor i8 [[NOT]], 32
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %op1_p2 = icmp ule i8 %x, 5
   call void @llvm.assume(i1 %op1_p2)
   %shift = shl i8 -1, %x
   %not = xor i8 %shift, -1

llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-pr49778.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 
 ; PR49778: this should not be folded to 0.
 define i32 @src(i1 %x2) {
 ; CHECK-LABEL: @src(
 ; CHECK-NEXT:    [[X13:%.*]] = zext i1 [[X2:%.*]] to i32
-; CHECK-NEXT:    [[_7:%.*]] = shl i32 -1, [[X13]]
+; CHECK-NEXT:    [[_7:%.*]] = shl nsw i32 -1, [[X13]]
 ; CHECK-NEXT:    [[MASK:%.*]] = xor i32 [[_7]], -1
 ; CHECK-NEXT:    [[_8:%.*]] = and i32 [[MASK]], [[X13]]
-; CHECK-NEXT:    [[_9:%.*]] = shl i32 [[_8]], [[X13]]
+; CHECK-NEXT:    [[_9:%.*]] = shl nuw nsw i32 [[_8]], [[X13]]
 ; CHECK-NEXT:    ret i32 [[_9]]
 ;
   %x13 = zext i1 %x2 to i32
   %_7 = shl i32 4294967295, %x13
   %mask = xor i32 %_7, 4294967295
   %_8 = and i32 %mask, %x13
   %_9 = shl i32 %_8, %x13
   ret i32 %_9
 }

llvm/test/Transforms/InstCombine/rotate.ll

 ; Non-power-of-2 types. This could be transformed, but it's not a typical rotate pattern.
 
 define i9 @rotateleft_9_neg_mask_wide_amount_commute(i9 %v, i33 %shamt) {
 ; CHECK-LABEL: @rotateleft_9_neg_mask_wide_amount_commute(
 ; CHECK-NEXT:    [[NEG:%.*]] = sub i33 0, [[SHAMT:%.*]]
 ; CHECK-NEXT:    [[LSHAMT:%.*]] = and i33 [[SHAMT]], 8
 ; CHECK-NEXT:    [[RSHAMT:%.*]] = and i33 [[NEG]], 8
 ; CHECK-NEXT:    [[CONV:%.*]] = zext i9 [[V:%.*]] to i33
-; CHECK-NEXT:    [[SHL:%.*]] = shl i33 [[CONV]], [[LSHAMT]]
+; CHECK-NEXT:    [[SHL:%.*]] = shl nuw nsw i33 [[CONV]], [[LSHAMT]]
 ; CHECK-NEXT:    [[SHR:%.*]] = lshr i33 [[CONV]], [[RSHAMT]]
 ; CHECK-NEXT:    [[OR:%.*]] = or i33 [[SHL]], [[SHR]]
 ; CHECK-NEXT:    [[RET:%.*]] = trunc i33 [[OR]] to i9
 ; CHECK-NEXT:    ret i9 [[RET]]
 ;
   %neg = sub i33 0, %shamt
   %lshamt = and i33 %shamt, 8
   %rshamt = and i33 %neg, 8

llvm/test/Transforms/InstCombine/shift-flags.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 
 define i8 @shl_add_nuw(i8 %amt_in, i8 %cnt_in) {
 ; CHECK-LABEL: @shl_add_nuw(
 ; CHECK-NEXT:    [[AMT:%.*]] = and i8 [[AMT_IN:%.*]], 63
 ; CHECK-NEXT:    [[CNT:%.*]] = and i8 [[CNT_IN:%.*]], 2
-; CHECK-NEXT:    [[R:%.*]] = shl i8 [[AMT]], [[CNT]]
+; CHECK-NEXT:    [[R:%.*]] = shl nuw i8 [[AMT]], [[CNT]]
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %amt = and i8 %amt_in, 63
   %cnt = and i8 %cnt_in, 2
   %r = shl i8 %amt, %cnt
   ret i8 %r
 }
 
;
   %r = shl i8 %amt, %cnt
   ret i8 %r
 }
 
 define i8 @shl_add_nuw_and_nsw(i8 %amt_in, i8 %cnt_in) {
 ; CHECK-LABEL: @shl_add_nuw_and_nsw(
 ; CHECK-NEXT:    [[AMT:%.*]] = and i8 [[AMT_IN:%.*]], 31
 ; CHECK-NEXT:    [[CNT:%.*]] = and i8 [[CNT_IN:%.*]], 2
-; CHECK-NEXT:    [[R:%.*]] = shl i8 [[AMT]], [[CNT]]
+; CHECK-NEXT:    [[R:%.*]] = shl nuw nsw i8 [[AMT]], [[CNT]]
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %amt = and i8 %amt_in, 31
   %cnt = and i8 %cnt_in, 2
   %r = shl i8 %amt, %cnt
   ret i8 %r
 }
 
 define i8 @shl_add_nsw(i8 %amt_in, i8 %cnt_in) {
 ; CHECK-LABEL: @shl_add_nsw(
 ; CHECK-NEXT:    [[AMT:%.*]] = or i8 [[AMT_IN:%.*]], -32
 ; CHECK-NEXT:    [[CNT:%.*]] = and i8 [[CNT_IN:%.*]], 2
-; CHECK-NEXT:    [[R:%.*]] = shl i8 [[AMT]], [[CNT]]
+; CHECK-NEXT:    [[R:%.*]] = shl nsw i8 [[AMT]], [[CNT]]
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %amt = or i8 %amt_in, 224
   %cnt = and i8 %cnt_in, 2
   %r = shl i8 %amt, %cnt
   ret i8 %r
 }
 
;
   %r = shl i8 %amt, %cnt
   ret i8 %r
 }
 
 define i8 @lshr_add_exact(i8 %amt_in, i8 %cnt_in) {
 ; CHECK-LABEL: @lshr_add_exact(
 ; CHECK-NEXT:    [[AMT:%.*]] = and i8 [[AMT_IN:%.*]], -4
 ; CHECK-NEXT:    [[CNT:%.*]] = and i8 [[CNT_IN:%.*]], 2
-; CHECK-NEXT:    [[R:%.*]] = lshr i8 [[AMT]], [[CNT]]
+; CHECK-NEXT:    [[R:%.*]] = lshr exact i8 [[AMT]], [[CNT]]
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %amt = and i8 %amt_in, -4
   %cnt = and i8 %cnt_in, 2
   %r = lshr i8 %amt, %cnt
   ret i8 %r
 }
 
;
   %r = lshr i8 %amt, %cnt
   ret i8 %r
 }
 
 define i8 @ashr_add_exact(i8 %amt_in, i8 %cnt_in) {
 ; CHECK-LABEL: @ashr_add_exact(
 ; CHECK-NEXT:    [[AMT:%.*]] = and i8 [[AMT_IN:%.*]], -14
 ; CHECK-NEXT:    [[CNT:%.*]] = and i8 [[CNT_IN:%.*]], 1
-; CHECK-NEXT:    [[R:%.*]] = ashr i8 [[AMT]], [[CNT]]
+; CHECK-NEXT:    [[R:%.*]] = ashr exact i8 [[AMT]], [[CNT]]
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %amt = and i8 %amt_in, -14
   %cnt = and i8 %cnt_in, 1
   %r = ashr i8 %amt, %cnt
   ret i8 %r
 }
 

llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll

;
   ret i8 %Z
 }
 
 define i64 @test11(i32 %A, i32 %B) {
 ; CHECK-LABEL: @test11(
 ; CHECK-NEXT:    [[C:%.*]] = zext i32 [[A:%.*]] to i64
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[B:%.*]], 31
 ; CHECK-NEXT:    [[E:%.*]] = zext i32 [[TMP1]] to i64
-; CHECK-NEXT:    [[F:%.*]] = shl i64 [[C]], [[E]]
+; CHECK-NEXT:    [[F:%.*]] = shl nuw nsw i64 [[C]], [[E]]
 ; CHECK-NEXT:    ret i64 [[F]]
 ;
   %C = zext i32 %A to i128
   %D = zext i32 %B to i128
   %E = and i128 %D, 31
   %F = shl i128 %C, %E
   %G = trunc i128 %F to i64
   ret i64 %G
 }
 
 define <2 x i64> @test11_vec(<2 x i32> %A, <2 x i32> %B) {
 ; CHECK-LABEL: @test11_vec(
 ; CHECK-NEXT:    [[C:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64>
 ; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> [[B:%.*]], <i32 31, i32 31>
 ; CHECK-NEXT:    [[E:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT:    [[F:%.*]] = shl <2 x i64> [[C]], [[E]]
+; CHECK-NEXT:    [[F:%.*]] = shl nuw nsw <2 x i64> [[C]], [[E]]
 ; CHECK-NEXT:    ret <2 x i64> [[F]]
 ;
   %C = zext <2 x i32> %A to <2 x i128>
   %D = zext <2 x i32> %B to <2 x i128>
   %E = and <2 x i128> %D, <i128 31, i128 31>
   %F = shl <2 x i128> %C, %E
   %G = trunc <2 x i128> %F to <2 x i64>
   ret <2 x i64> %G
 }
 
 define <2 x i64> @test11_vec_nonuniform(<2 x i32> %A, <2 x i32> %B) {
 ; CHECK-LABEL: @test11_vec_nonuniform(
 ; CHECK-NEXT:    [[C:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64>
 ; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> [[B:%.*]], <i32 31, i32 15>
 ; CHECK-NEXT:    [[E:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT:    [[F:%.*]] = shl <2 x i64> [[C]], [[E]]
+; CHECK-NEXT:    [[F:%.*]] = shl nuw nsw <2 x i64> [[C]], [[E]]
 ; CHECK-NEXT:    ret <2 x i64> [[F]]
 ;
   %C = zext <2 x i32> %A to <2 x i128>
   %D = zext <2 x i32> %B to <2 x i128>
   %E = and <2 x i128> %D, <i128 31, i128 15>
   %F = shl <2 x i128> %C, %E
   %G = trunc <2 x i128> %F to <2 x i64>
   ret <2 x i64> %G

llvm/test/Transforms/InstCombine/trunc.ll

;
   ret i8 %Z
 }
 
 define i64 @test11(i32 %A, i32 %B) {
 ; CHECK-LABEL: @test11(
 ; CHECK-NEXT:    [[C:%.*]] = zext i32 [[A:%.*]] to i64
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[B:%.*]], 31
 ; CHECK-NEXT:    [[E:%.*]] = zext i32 [[TMP1]] to i64
-; CHECK-NEXT:    [[F:%.*]] = shl i64 [[C]], [[E]]
+; CHECK-NEXT:    [[F:%.*]] = shl nuw nsw i64 [[C]], [[E]]
 ; CHECK-NEXT:    ret i64 [[F]]
 ;
   %C = zext i32 %A to i128
   %D = zext i32 %B to i128
   %E = and i128 %D, 31
   %F = shl i128 %C, %E
   %G = trunc i128 %F to i64
   ret i64 %G
 }
 
 define <2 x i64> @test11_vec(<2 x i32> %A, <2 x i32> %B) {
 ; CHECK-LABEL: @test11_vec(
 ; CHECK-NEXT:    [[C:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64>
 ; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> [[B:%.*]], <i32 31, i32 31>
 ; CHECK-NEXT:    [[E:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT:    [[F:%.*]] = shl <2 x i64> [[C]], [[E]]
+; CHECK-NEXT:    [[F:%.*]] = shl nuw nsw <2 x i64> [[C]], [[E]]
 ; CHECK-NEXT:    ret <2 x i64> [[F]]
 ;
   %C = zext <2 x i32> %A to <2 x i128>
   %D = zext <2 x i32> %B to <2 x i128>
   %E = and <2 x i128> %D, <i128 31, i128 31>
   %F = shl <2 x i128> %C, %E
   %G = trunc <2 x i128> %F to <2 x i64>
   ret <2 x i64> %G
 }
 
 define <2 x i64> @test11_vec_nonuniform(<2 x i32> %A, <2 x i32> %B) {
 ; CHECK-LABEL: @test11_vec_nonuniform(
 ; CHECK-NEXT:    [[C:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64>
 ; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> [[B:%.*]], <i32 31, i32 15>
 ; CHECK-NEXT:    [[E:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT:    [[F:%.*]] = shl <2 x i64> [[C]], [[E]]
+; CHECK-NEXT:    [[F:%.*]] = shl nuw nsw <2 x i64> [[C]], [[E]]
 ; CHECK-NEXT:    ret <2 x i64> [[F]]
 ;
   %C = zext <2 x i32> %A to <2 x i128>
   %D = zext <2 x i32> %B to <2 x i128>
   %E = and <2 x i128> %D, <i128 31, i128 15>
   %F = shl <2 x i128> %C, %E
   %G = trunc <2 x i128> %F to <2 x i64>
   ret <2 x i64> %G

llvm/test/Transforms/PhaseOrdering/X86/SROA-after-final-loop-unrolling-2.ll

 
 ; Function Attrs: mustprogress nounwind uwtable
 define dso_local void @foo(i32 noundef %arg, ptr noundef nonnull align 4 dereferenceable(8) %arg1) #0 {
 ; CHECK-LABEL: @foo(
 ; CHECK-NEXT:  bb:
 ; CHECK-NEXT:    [[I9:%.*]] = sdiv i32 [[ARG:%.*]], 128
 ; CHECK-NEXT:    [[I10:%.*]] = shl nsw i32 [[I9]], 7
 ; CHECK-NEXT:    [[ARG_OFF:%.*]] = add i32 [[ARG]], 127
-; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[ARG_OFF]], 255
-; CHECK-NEXT:    br i1 [[TMP0]], label [[BB12:%.*]], label [[BB13:%.*]]
+; CHECK-NEXT:    [[I11_NOT4:%.*]] = icmp ult i32 [[ARG_OFF]], 255
+; CHECK-NEXT:    br i1 [[I11_NOT4]], label [[BB12:%.*]], label [[BB13:%.*]]
 ; CHECK:       bb12.loopexit:
 ; CHECK-NEXT:    [[I3_SROA_8_0_INSERT_EXT:%.*]] = zext i32 [[I21_3:%.*]] to i64
 ; CHECK-NEXT:    [[I3_SROA_8_0_INSERT_SHIFT:%.*]] = shl nuw i64 [[I3_SROA_8_0_INSERT_EXT]], 32
 ; CHECK-NEXT:    [[I3_SROA_0_0_INSERT_EXT:%.*]] = zext i32 [[I21_2:%.*]] to i64
 ; CHECK-NEXT:    [[I3_SROA_0_0_INSERT_INSERT:%.*]] = or i64 [[I3_SROA_8_0_INSERT_SHIFT]], [[I3_SROA_0_0_INSERT_EXT]]
 ; CHECK-NEXT:    br label [[BB12]]
 ; CHECK:       bb12:
-; CHECK-NEXT:    [[TMP1:%.*]] = phi i64 [ [[I3_SROA_0_0_INSERT_INSERT]], [[BB12_LOOPEXIT:%.*]] ], [ 180388626456, [[BB:%.*]] ]
-; CHECK-NEXT:    store i64 [[TMP1]], ptr [[ARG1:%.*]], align 4, !tbaa [[TBAA5:![0-9]+]]
+; CHECK-NEXT:    [[TMP0:%.*]] = phi i64 [ [[I3_SROA_0_0_INSERT_INSERT]], [[BB12_LOOPEXIT:%.*]] ], [ 180388626456, [[BB:%.*]] ]
+; CHECK-NEXT:    store i64 [[TMP0]], ptr [[ARG1:%.*]], align 4, !tbaa [[TBAA5:![0-9]+]]
 ; CHECK-NEXT:    ret void
 ; CHECK:       bb13:
 ; CHECK-NEXT:    [[I3_SROA_8_0:%.*]] = phi i32 [ [[I21_3]], [[BB13]] ], [ 42, [[BB]] ]
 ; CHECK-NEXT:    [[I3_SROA_0_0:%.*]] = phi i32 [ [[I21_2]], [[BB13]] ], [ 24, [[BB]] ]
 ; CHECK-NEXT:    [[I4_05:%.*]] = phi i32 [ [[I24_3:%.*]], [[BB13]] ], [ 0, [[BB]] ]
 ; CHECK-NEXT:    [[I21:%.*]] = mul nsw i32 [[I3_SROA_0_0]], [[I4_05]]
 ; CHECK-NEXT:    [[I24:%.*]] = or i32 [[I4_05]], 1
 ; CHECK-NEXT:    [[I21_1:%.*]] = mul nsw i32 [[I3_SROA_8_0]], [[I24]]