The previous commit 9c837b7d0e2e don't check the type width,
so the logic is incorrect because a shift left of vscale can be zero
if all bits get shifted out.
This PR add condition to check above issue.
Differential D157292
Reland [ValueTracking] Improve the coverage of isKnownToBeAPowerOfTwo for vscale Allen on Aug 7 2023, 8:39 AM. Authored by
Details
The previous commit 9c837b7d0e2e don't check the type width, This PR add condition to check above issue.
Diff Detail Event TimelineComment Actions Given the lack of test changes, do we need this? Presumably https://github.com/llvm/llvm-project/commit/5de89b4d99c913e3c7c2735886f2519a2ed39d8a already covered the motivating cases. Edit: To clarify, we do need to remove the incorrect code, the question is more about whether we need the new code this introduces. Comment Actions In my local test, there is some failure tests after the revert of f6c726472df1, and this PR can fix them LLVM :: Transforms/InstCombine/rem-mul-shl.ll LLVM :: Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll LLVM :: Transforms/LoopVectorize/AArch64/sve-widen-phi.ll Comment Actions oh, I find the commit 5de89b4d99c9 already fixed, thanks @goldstein.w.n and @nikic, so this is not necessary |
More robust would be to match shift as a value and use ComputeKnownBits to get max shift cnt.