[CodeGen] Pre-commit tests showing incorrect pattern FMLA_* pseudo instructions

[paulwalker-arm]

llvm/test/CodeGen/AArch64/sve-fp-combine.ll

1271

I'd remove this comment but let's certainly drop the mindlessly part.

1277–1279

This doesn't match the patterns you're moving in the follow on work. Is it possible to use llvm.fma and select as they appear in the PatFrags? You don't need to worry about FMA_PRED because that will be created automatically when ISD::FMA is lowered.

[igor.kirillov]

Remove comment. Update tests to match patterns better

[paulwalker-arm]

Before landing the patch please add equivalent testing for the bogus FMLS cases as well.

llvm/test/CodeGen/AArch64/sve-fp-combine.ll

1271

The function names could do with a tweak to match the new IR.

[igor.kirillov]

Update test functions names

[igor.kirillov]

Update CHECK lines

llvm/test/CodeGen/AArch64/sve-fp-combine.ll

 ; CHECK-NEXT:    fmul z1.s, z1.s, z2.s
 ; CHECK-NEXT:    fadd z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT:    ret
   %fmul = fmul <vscale x 4 x float> %b, %c
   %sel = select <vscale x 4 x i1> %mask, <vscale x 4 x float> %fmul, <vscale x 4 x float> zeroinitializer
   %fadd = fadd nsz <vscale x 4 x float> %a, %sel
   ret <vscale x 4 x float> %fadd
 }
+
+define <vscale x 8 x half> @fma_sel_h_different_arg_order(<vscale x 8 x i1> %pred, <vscale x 8 x half> %m1, <vscale x 8 x half> %m2, <vscale x 8 x half> %acc) {
+; CHECK-LABEL: fma_sel_h_different_arg_order:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmad z0.h, p0/m, z1.h, z2.h
+; CHECK-NEXT:    ret
+  %mul.add = call <vscale x 8 x half> @llvm.fma.nxv8f16(<vscale x 8 x half> %m1, <vscale x 8 x half> %m2, <vscale x 8 x half> %acc)
+  %masked.mul.add = select <vscale x 8 x i1> %pred, <vscale x 8 x half> %mul.add, <vscale x 8 x half> %acc
+  ret <vscale x 8 x half> %masked.mul.add
+}
+
+define <vscale x 4 x float> @fma_sel_s_different_arg_order(<vscale x 4 x i1> %pred, <vscale x 4 x float> %m1, <vscale x 4 x float> %m2, <vscale x 4 x float> %acc) {
+; CHECK-LABEL: fma_sel_s_different_arg_order:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmad z0.s, p0/m, z1.s, z2.s
+; CHECK-NEXT:    ret
+  %mul.add = call <vscale x 4 x float> @llvm.fma.nxv4f32(<vscale x 4 x float> %m1, <vscale x 4 x float> %m2, <vscale x 4 x float> %acc)
+  %masked.mul.add = select <vscale x 4 x i1> %pred, <vscale x 4 x float> %mul.add, <vscale x 4 x float> %acc
+  ret <vscale x 4 x float> %masked.mul.add
+}
+
+define <vscale x 2 x double> @fma_sel_d_different_arg_order(<vscale x 2 x i1> %pred, <vscale x 2 x double> %m1, <vscale x 2 x double> %m2, <vscale x 2 x double> %acc) {
+; CHECK-LABEL: fma_sel_d_different_arg_order:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmad z0.d, p0/m, z1.d, z2.d
+; CHECK-NEXT:    ret
+  %mul.add = call <vscale x 2 x double> @llvm.fma.nxv2f64(<vscale x 2 x double> %m1, <vscale x 2 x double> %m2, <vscale x 2 x double> %acc)
+  %masked.mul.add = select <vscale x 2 x i1> %pred, <vscale x 2 x double> %mul.add, <vscale x 2 x double> %acc
+  ret <vscale x 2 x double> %masked.mul.add
+}
+
+declare <vscale x 8 x half> @llvm.fma.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)
+declare <vscale x 4 x float> @llvm.fma.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 2 x double> @llvm.fma.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)