[MachinePipeliner] Fix a bug in write-after-read scheduling

[alonkom]

Summary

When computing the early/late start/end cycle only the case of loop-carried-dependence where the read comes before the write is handled.
This code guarantees they will be scheduled at the same stage, no more than II cycles apart.
This didn't work properly when the write occurs before the read, even though they may be loop-carried dependent.
For example:

a[idx] = 1;
b[idx] = long_compute_chain(a[idx + 1]);

In this case, where the write a[idx], comes before the read a[idx+1], the read cannot be scheduled more than II cycles from the write, as the write may store new data that should have been read already in previous iteration.

Unfortunately, I'm working on an out-of-tree target, and couldn't create a lit test of this case.

[bcahoon]

In your test case, does the addLoopCarriedDependences function add a Barrier edge between the load and store? If so, that should prevent the case described in the comment.

llvm/lib/CodeGen/MachinePipeliner.cpp

             int EarlyStart = cycle + Dep.getLatency() -
                              DAG->getDistance(Dep.getSUnit(), SU, Dep) * II;
             *MaxEarlyStart = std::max(*MaxEarlyStart, EarlyStart);
-            if (DAG->isLoopCarriedDep(SU, Dep, false)) {
+            if (DAG->isLoopCarriedDep(SU, Dep, false) ||
+                DAG->isLoopCarriedDep(SU, Dep)) {
               int End = earliestCycleInChain(Dep) + (II - 1);
               *MinEnd = std::min(*MinEnd, End);
             }

             int LateStart = cycle - Dep.getLatency() +
                             DAG->getDistance(SU, Dep.getSUnit(), Dep) * II;
             *MinLateStart = std::min(*MinLateStart, LateStart);
-            if (DAG->isLoopCarriedDep(SU, Dep)) {
+            if (DAG->isLoopCarriedDep(SU, Dep) ||
+                DAG->isLoopCarriedDep(SU, Dep, false)) {
               int Start = latestCycleInChain(Dep) + 1 - II;
               *MaxStart = std::max(*MaxStart, Start);
             }