[LoongArch] Implement isSExtCheaperThanZExt

[hev]

Summary

Implement isSExtCheaperThanZExt.

Signed-off-by: WANG Rui <[e-mail]>

[hev]

llvm/test/CodeGen/LoongArch/ir-instruction/br.ll

29–30

Future patches will utilize the W instruction, thereby eliminating unnecessary sign extensions.

[xen0n]

llvm/test/CodeGen/LoongArch/ir-instruction/br.ll

29–30

Mind explaining a bit what's the codegen you intended? Right now I couldn't think of a *.w instruction that would allow us to reduce this basic block any further.

[hev]

Thanks.

llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll

308

Here. This sign extension instruction should be removed.

llvm/test/CodeGen/LoongArch/ir-instruction/br.ll

29–30

Uh, I posted my comments in the wrong place... It was supposed to appear in the place I marked above.

[xen0n]

llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll

308

Okay. To be sure no one is forgetting about this you could add a note like "TODO: Optimize away the redundant sign extension before the atomicrmw loop" above the function, but if you're following up with a patch shortly it may be better to not do this (for less churn).

[SixWeining]

rebase

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

public:
 
   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
                              unsigned AS,
                              Instruction *I = nullptr) const override;
 
   bool isLegalICmpImmediate(int64_t Imm) const override;
   bool isLegalAddImmediate(int64_t Imm) const override;
   bool isZExtFree(SDValue Val, EVT VT2) const override;
+  bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
 
   bool hasAndNotCompare(SDValue Y) const override;
 
   bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
 
   bool allowsMisalignedMemoryAccesses(
       EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
       MachineMemOperand::Flags Flags = MachineMemOperand::MONone,

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

if ((MemVT == MVT::i8 || MemVT == MVT::i16) &&
         (LD->getExtensionType() == ISD::NON_EXTLOAD ||
          LD->getExtensionType() == ISD::ZEXTLOAD))
       return true;
   }
 
   return TargetLowering::isZExtFree(Val, VT2);
 }
 
+bool LoongArchTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const {
+  return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64;
+}
+
 bool LoongArchTargetLowering::hasAndNotCompare(SDValue Y) const {
   // TODO: Support vectors.
   if (Y.getValueType().isVector())
     return false;
 
   return !isa<ConstantSDNode>(Y);
 }

llvm/test/CodeGen/LoongArch/atomicrmw-uinc-udec-wrap.ll

; LA64-NEXT:    ret
   %result = atomicrmw uinc_wrap ptr %ptr, i16 %val seq_cst
   ret i16 %result
 }
 
 define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) {
 ; LA64-LABEL: atomicrmw_uinc_wrap_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.w $a3, $a0, 0
-; LA64-NEXT:    bstrpick.d $a2, $a1, 31, 0
+; LA64-NEXT:    addi.w $a2, $a1, 0
 ; LA64-NEXT:  .LBB2_1: # %atomicrmw.start
 ; LA64-NEXT:    # =>This Loop Header: Depth=1
 ; LA64-NEXT:    # Child Loop BB2_3 Depth 2
-; LA64-NEXT:    bstrpick.d $a1, $a3, 31, 0
-; LA64-NEXT:    sltu $a1, $a1, $a2
+; LA64-NEXT:    addi.w $a4, $a3, 0
+; LA64-NEXT:    sltu $a1, $a4, $a2
 ; LA64-NEXT:    xori $a1, $a1, 1
-; LA64-NEXT:    addi.d $a4, $a3, 1
-; LA64-NEXT:    masknez $a4, $a4, $a1
+; LA64-NEXT:    addi.d $a5, $a3, 1
+; LA64-NEXT:    masknez $a5, $a5, $a1
 ; LA64-NEXT:  .LBB2_3: # %atomicrmw.start
 ; LA64-NEXT:    # Parent Loop BB2_1 Depth=1
 ; LA64-NEXT:    # => This Inner Loop Header: Depth=2
 ; LA64-NEXT:    ll.w $a1, $a0, 0
 ; LA64-NEXT:    bne $a1, $a3, .LBB2_5
 ; LA64-NEXT:  # %bb.4: # %atomicrmw.start
 ; LA64-NEXT:    # in Loop: Header=BB2_3 Depth=2
 ; LA64-NEXT:    dbar 0
-; LA64-NEXT:    move $a5, $a4
-; LA64-NEXT:    sc.w $a5, $a0, 0
-; LA64-NEXT:    beqz $a5, .LBB2_3
+; LA64-NEXT:    move $a6, $a5
+; LA64-NEXT:    sc.w $a6, $a0, 0
+; LA64-NEXT:    beqz $a6, .LBB2_3
 ; LA64-NEXT:    b .LBB2_6
 ; LA64-NEXT:  .LBB2_5: # %atomicrmw.start
 ; LA64-NEXT:    # in Loop: Header=BB2_1 Depth=1
 ; LA64-NEXT:    dbar 1792
 ; LA64-NEXT:  .LBB2_6: # %atomicrmw.start
 ; LA64-NEXT:    # in Loop: Header=BB2_1 Depth=1
-; LA64-NEXT:    addi.w $a4, $a3, 0
 ; LA64-NEXT:    move $a3, $a1
 ; LA64-NEXT:    bne $a1, $a4, .LBB2_1
 ; LA64-NEXT:  # %bb.2: # %atomicrmw.end
 ; LA64-NEXT:    move $a0, $a1
 ; LA64-NEXT:    ret
   %result = atomicrmw uinc_wrap ptr %ptr, i32 %val seq_cst
   ret i32 %result
 }
; LA64-NEXT:    ret
   %result = atomicrmw udec_wrap ptr %ptr, i16 %val seq_cst
   ret i16 %result
 }
 
 define i32 @atomicrmw_udec_wrap_i32(ptr %ptr, i32 %val) {
 ; LA64-LABEL: atomicrmw_udec_wrap_i32:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    ld.w $a4, $a0, 0
-; LA64-NEXT:    bstrpick.d $a3, $a1, 31, 0
+; LA64-NEXT:    addi.w $a3, $a1, 0
 ; LA64-NEXT:  .LBB6_1: # %atomicrmw.start
 ; LA64-NEXT:    # =>This Loop Header: Depth=1
 ; LA64-NEXT:    # Child Loop BB6_3 Depth 2
-; LA64-NEXT:    bstrpick.d $a2, $a4, 31, 0
-; LA64-NEXT:    sltu $a5, $a3, $a2
+; LA64-NEXT:    addi.w $a5, $a4, 0
+; LA64-NEXT:    sltu $a2, $a3, $a5
 ; LA64-NEXT:    addi.d $a6, $a4, -1
-; LA64-NEXT:    masknez $a6, $a6, $a5
-; LA64-NEXT:    maskeqz $a5, $a1, $a5
-; LA64-NEXT:    or $a5, $a5, $a6
-; LA64-NEXT:    sltui $a2, $a2, 1
-; LA64-NEXT:    masknez $a5, $a5, $a2
+; LA64-NEXT:    masknez $a6, $a6, $a2
 ; LA64-NEXT:    maskeqz $a2, $a1, $a2
-; LA64-NEXT:    or $a5, $a2, $a5
+; LA64-NEXT:    or $a2, $a2, $a6
+; LA64-NEXT:    sltui $a6, $a5, 1
+; LA64-NEXT:    masknez $a2, $a2, $a6
+; LA64-NEXT:    maskeqz $a6, $a1, $a6
+; LA64-NEXT:    or $a6, $a6, $a2
 ; LA64-NEXT:  .LBB6_3: # %atomicrmw.start
 ; LA64-NEXT:    # Parent Loop BB6_1 Depth=1
 ; LA64-NEXT:    # => This Inner Loop Header: Depth=2
 ; LA64-NEXT:    ll.w $a2, $a0, 0
 ; LA64-NEXT:    bne $a2, $a4, .LBB6_5
 ; LA64-NEXT:  # %bb.4: # %atomicrmw.start
 ; LA64-NEXT:    # in Loop: Header=BB6_3 Depth=2
 ; LA64-NEXT:    dbar 0
-; LA64-NEXT:    move $a6, $a5
-; LA64-NEXT:    sc.w $a6, $a0, 0
-; LA64-NEXT:    beqz $a6, .LBB6_3
+; LA64-NEXT:    move $a7, $a6
+; LA64-NEXT:    sc.w $a7, $a0, 0
+; LA64-NEXT:    beqz $a7, .LBB6_3
 ; LA64-NEXT:    b .LBB6_6
 ; LA64-NEXT:  .LBB6_5: # %atomicrmw.start
 ; LA64-NEXT:    # in Loop: Header=BB6_1 Depth=1
 ; LA64-NEXT:    dbar 1792
 ; LA64-NEXT:  .LBB6_6: # %atomicrmw.start
 ; LA64-NEXT:    # in Loop: Header=BB6_1 Depth=1
-; LA64-NEXT:    addi.w $a5, $a4, 0
 ; LA64-NEXT:    move $a4, $a2
 ; LA64-NEXT:    bne $a2, $a5, .LBB6_1
 ; LA64-NEXT:  # %bb.2: # %atomicrmw.end
 ; LA64-NEXT:    move $a0, $a2
 ; LA64-NEXT:    ret
   %result = atomicrmw udec_wrap ptr %ptr, i32 %val seq_cst
   ret i32 %result
 }

llvm/test/CodeGen/LoongArch/duplicate-returns-for-tailcall.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
 ;; Perform tail call optimization for duplicate returns.
 declare i32 @test()
 declare i32 @test1()
 declare i32 @test2()
 declare i32 @test3()
 define i32 @duplicate_returns(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: duplicate_returns:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    bstrpick.d $a2, $a0, 31, 0
-; CHECK-NEXT:    beqz $a2, .LBB0_4
-; CHECK-NEXT:  # %bb.1: # %if.else
-; CHECK-NEXT:    bstrpick.d $a2, $a1, 31, 0
-; CHECK-NEXT:    beqz $a2, .LBB0_5
-; CHECK-NEXT:  # %bb.2: # %if.else2
 ; CHECK-NEXT:    addi.w $a0, $a0, 0
+; CHECK-NEXT:    beqz $a0, .LBB0_4
+; CHECK-NEXT:  # %bb.1: # %if.else
 ; CHECK-NEXT:    addi.w $a1, $a1, 0
+; CHECK-NEXT:    beqz $a1, .LBB0_5
+; CHECK-NEXT:  # %bb.2: # %if.else2
 ; CHECK-NEXT:    bge $a1, $a0, .LBB0_6
 ; CHECK-NEXT:  # %bb.3: # %if.then3
 ; CHECK-NEXT:    b %plt(test2)
 ; CHECK-NEXT:  .LBB0_4: # %if.then
 ; CHECK-NEXT:    b %plt(test)
 ; CHECK-NEXT:  .LBB0_5: # %if.then2
 ; CHECK-NEXT:    b %plt(test1)
 ; CHECK-NEXT:  .LBB0_6: # %if.else3

llvm/test/CodeGen/LoongArch/get-setcc-result-type.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s
 
 define void @getSetCCResultType(ptr %p) {
 ; CHECK-LABEL: getSetCCResultType:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ld.wu $a1, $a0, 12
+; CHECK-NEXT:    ld.w $a1, $a0, 12
 ; CHECK-NEXT:    sltui $a1, $a1, 1
 ; CHECK-NEXT:    sub.d $a1, $zero, $a1
 ; CHECK-NEXT:    st.w $a1, $a0, 12
-; CHECK-NEXT:    ld.wu $a1, $a0, 8
+; CHECK-NEXT:    ld.w $a1, $a0, 8
 ; CHECK-NEXT:    sltui $a1, $a1, 1
 ; CHECK-NEXT:    sub.d $a1, $zero, $a1
 ; CHECK-NEXT:    st.w $a1, $a0, 8
-; CHECK-NEXT:    ld.wu $a1, $a0, 4
+; CHECK-NEXT:    ld.w $a1, $a0, 4
 ; CHECK-NEXT:    sltui $a1, $a1, 1
 ; CHECK-NEXT:    sub.d $a1, $zero, $a1
 ; CHECK-NEXT:    st.w $a1, $a0, 4
-; CHECK-NEXT:    ld.wu $a1, $a0, 0
+; CHECK-NEXT:    ld.w $a1, $a0, 0
 ; CHECK-NEXT:    sltui $a1, $a1, 1
 ; CHECK-NEXT:    sub.d $a1, $zero, $a1
 ; CHECK-NEXT:    st.w $a1, $a0, 0
 ; CHECK-NEXT:    ret
 entry:
   %0 = load <4 x i32>, ptr %p, align 16
   %cmp = icmp eq <4 x i32> %0, zeroinitializer
   %sext = sext <4 x i1> %cmp to <4 x i32>
   store <4 x i32> %sext, ptr %p, align 16
   ret void
 }

llvm/test/CodeGen/LoongArch/ir-instruction/atomic-cmpxchg.ll

 }
 
 define i1 @cmpxchg_i8_acquire_acquire_reti1(ptr %ptr, i8 %cmp, i8 %val) nounwind {
 ; LA64-LABEL: cmpxchg_i8_acquire_acquire_reti1:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.w $a3, $zero, -4
 ; LA64-NEXT:    and $a3, $a0, $a3
 ; LA64-NEXT:    slli.d $a0, $a0, 3
-; LA64-NEXT:    andi $a1, $a1, 255
-; LA64-NEXT:    sll.w $a1, $a1, $a0
 ; LA64-NEXT:    ori $a4, $zero, 255
 ; LA64-NEXT:    sll.w $a4, $a4, $a0
+; LA64-NEXT:    andi $a1, $a1, 255
+; LA64-NEXT:    sll.w $a1, $a1, $a0
 ; LA64-NEXT:    andi $a2, $a2, 255
 ; LA64-NEXT:    sll.w $a0, $a2, $a0
 ; LA64-NEXT:    addi.w $a0, $a0, 0
+; LA64-NEXT:    addi.w $a1, $a1, 0
 ; LA64-NEXT:    addi.w $a2, $a4, 0
-; LA64-NEXT:    addi.w $a5, $a1, 0
 ; LA64-NEXT:  .LBB8_1: # =>This Inner Loop Header: Depth=1
-; LA64-NEXT:    ll.w $a6, $a3, 0
-; LA64-NEXT:    and $a7, $a6, $a2
-; LA64-NEXT:    bne $a7, $a5, .LBB8_3
+; LA64-NEXT:    ll.w $a5, $a3, 0
+; LA64-NEXT:    and $a6, $a5, $a2
+; LA64-NEXT:    bne $a6, $a1, .LBB8_3
 ; LA64-NEXT:  # %bb.2: # in Loop: Header=BB8_1 Depth=1
 ; LA64-NEXT:    dbar 0
-; LA64-NEXT:    andn $a7, $a6, $a2
-; LA64-NEXT:    or $a7, $a7, $a0
-; LA64-NEXT:    sc.w $a7, $a3, 0
-; LA64-NEXT:    beqz $a7, .LBB8_1
+; LA64-NEXT:    andn $a6, $a5, $a2
+; LA64-NEXT:    or $a6, $a6, $a0
+; LA64-NEXT:    sc.w $a6, $a3, 0
+; LA64-NEXT:    beqz $a6, .LBB8_1
 ; LA64-NEXT:    b .LBB8_4
 ; LA64-NEXT:  .LBB8_3:
 ; LA64-NEXT:    dbar 1792
 ; LA64-NEXT:  .LBB8_4:
-; LA64-NEXT:    and $a0, $a6, $a4
-; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
-; LA64-NEXT:    bstrpick.d $a1, $a1, 31, 0
+; LA64-NEXT:    and $a0, $a5, $a4
+; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    xor $a0, $a1, $a0
 ; LA64-NEXT:    sltui $a0, $a0, 1
 ; LA64-NEXT:    ret
   %tmp = cmpxchg ptr %ptr, i8 %cmp, i8 %val acquire acquire
   %res = extractvalue { i8, i1 } %tmp, 1
   ret i1 %res
 }
 
 define i1 @cmpxchg_i16_acquire_acquire_reti1(ptr %ptr, i16 %cmp, i16 %val) nounwind {
 ; LA64-LABEL: cmpxchg_i16_acquire_acquire_reti1:
 ; LA64:       # %bb.0:
 ; LA64-NEXT:    addi.w $a3, $zero, -4
 ; LA64-NEXT:    and $a3, $a0, $a3
 ; LA64-NEXT:    slli.d $a0, $a0, 3
-; LA64-NEXT:    bstrpick.d $a1, $a1, 15, 0
-; LA64-NEXT:    sll.w $a1, $a1, $a0
 ; LA64-NEXT:    lu12i.w $a4, 15
 ; LA64-NEXT:    ori $a4, $a4, 4095
 ; LA64-NEXT:    sll.w $a4, $a4, $a0
+; LA64-NEXT:    bstrpick.d $a1, $a1, 15, 0
+; LA64-NEXT:    sll.w $a1, $a1, $a0
 ; LA64-NEXT:    bstrpick.d $a2, $a2, 15, 0
 ; LA64-NEXT:    sll.w $a0, $a2, $a0
 ; LA64-NEXT:    addi.w $a0, $a0, 0
+; LA64-NEXT:    addi.w $a1, $a1, 0
 ; LA64-NEXT:    addi.w $a2, $a4, 0
-; LA64-NEXT:    addi.w $a5, $a1, 0
 ; LA64-NEXT:  .LBB9_1: # =>This Inner Loop Header: Depth=1
-; LA64-NEXT:    ll.w $a6, $a3, 0
-; LA64-NEXT:    and $a7, $a6, $a2
-; LA64-NEXT:    bne $a7, $a5, .LBB9_3
+; LA64-NEXT:    ll.w $a5, $a3, 0
+; LA64-NEXT:    and $a6, $a5, $a2
+; LA64-NEXT:    bne $a6, $a1, .LBB9_3
 ; LA64-NEXT:  # %bb.2: # in Loop: Header=BB9_1 Depth=1
 ; LA64-NEXT:    dbar 0
-; LA64-NEXT:    andn $a7, $a6, $a2
-; LA64-NEXT:    or $a7, $a7, $a0
-; LA64-NEXT:    sc.w $a7, $a3, 0
-; LA64-NEXT:    beqz $a7, .LBB9_1
+; LA64-NEXT:    andn $a6, $a5, $a2
+; LA64-NEXT:    or $a6, $a6, $a0
+; LA64-NEXT:    sc.w $a6, $a3, 0
+; LA64-NEXT:    beqz $a6, .LBB9_1
 ; LA64-NEXT:    b .LBB9_4
 ; LA64-NEXT:  .LBB9_3:
 ; LA64-NEXT:    dbar 1792
 ; LA64-NEXT:  .LBB9_4:
-; LA64-NEXT:    and $a0, $a6, $a4
-; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
-; LA64-NEXT:    bstrpick.d $a1, $a1, 31, 0
+; LA64-NEXT:    and $a0, $a5, $a4
+; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    xor $a0, $a1, $a0
 ; LA64-NEXT:    sltui $a0, $a0, 1
 ; LA64-NEXT:    ret
   %tmp = cmpxchg ptr %ptr, i16 %cmp, i16 %val acquire acquire
   %res = extractvalue { i16, i1 } %tmp, 1
   ret i1 %res
 }
 

llvm/test/CodeGen/LoongArch/ir-instruction/br.ll

 ; LA32-NEXT:    beq $a2, $a0, .LBB1_2
 ; LA32-NEXT:  # %bb.1: # %test
 ; LA32-NEXT:    ld.w $a0, $a1, 0
 ; LA32-NEXT:  .LBB1_2: # %end
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: foo_br_eq:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    ld.wu $a2, $a1, 0
-; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
+; LA64-NEXT:    ld.w $a2, $a1, 0
+; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    beq $a2, $a0, .LBB1_2
 ; LA64-NEXT:  # %bb.1: # %test
 ; LA64-NEXT:    ld.w $a0, $a1, 0
 ; LA64-NEXT:  .LBB1_2: # %end
 ; LA64-NEXT:    ret
   %val = load volatile i32, ptr %b
   %cc = icmp eq i32 %val, %a
   br i1 %cc, label %end, label %test

 ; LA32-NEXT:    bne $a2, $a0, .LBB2_2
 ; LA32-NEXT:  # %bb.1: # %test
 ; LA32-NEXT:    ld.w $a0, $a1, 0
 ; LA32-NEXT:  .LBB2_2: # %end
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: foo_br_ne:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    ld.wu $a2, $a1, 0
-; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
+; LA64-NEXT:    ld.w $a2, $a1, 0
+; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    bne $a2, $a0, .LBB2_2
 ; LA64-NEXT:  # %bb.1: # %test
 ; LA64-NEXT:    ld.w $a0, $a1, 0
 ; LA64-NEXT:  .LBB2_2: # %end
 ; LA64-NEXT:    ret
   %val = load volatile i32, ptr %b
   %cc = icmp ne i32 %val, %a
   br i1 %cc, label %end, label %test

 ; LA32-NEXT:    bltu $a2, $a0, .LBB5_2
 ; LA32-NEXT:  # %bb.1: # %test
 ; LA32-NEXT:    ld.w $a0, $a1, 0
 ; LA32-NEXT:  .LBB5_2: # %end
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: foo_br_ult:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    ld.wu $a2, $a1, 0
-; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
+; LA64-NEXT:    ld.w $a2, $a1, 0
+; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    bltu $a2, $a0, .LBB5_2
 ; LA64-NEXT:  # %bb.1: # %test
 ; LA64-NEXT:    ld.w $a0, $a1, 0
 ; LA64-NEXT:  .LBB5_2: # %end
 ; LA64-NEXT:    ret
   %val = load volatile i32, ptr %b
   %cc = icmp ult i32 %val, %a
   br i1 %cc, label %end, label %test

 ; LA32-NEXT:    bgeu $a2, $a0, .LBB6_2
 ; LA32-NEXT:  # %bb.1: # %test
 ; LA32-NEXT:    ld.w $a0, $a1, 0
 ; LA32-NEXT:  .LBB6_2: # %end
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: foo_br_uge:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    ld.wu $a2, $a1, 0
-; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
+; LA64-NEXT:    ld.w $a2, $a1, 0
+; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    bgeu $a2, $a0, .LBB6_2
 ; LA64-NEXT:  # %bb.1: # %test
 ; LA64-NEXT:    ld.w $a0, $a1, 0
 ; LA64-NEXT:  .LBB6_2: # %end
 ; LA64-NEXT:    ret
   %val = load volatile i32, ptr %b
   %cc = icmp uge i32 %val, %a
   br i1 %cc, label %end, label %test

 ; LA32-NEXT:    bltu $a0, $a2, .LBB9_2
 ; LA32-NEXT:  # %bb.1: # %test
 ; LA32-NEXT:    ld.w $a0, $a1, 0
 ; LA32-NEXT:  .LBB9_2: # %end
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: foo_br_ugt:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    ld.wu $a2, $a1, 0
-; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
+; LA64-NEXT:    ld.w $a2, $a1, 0
+; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    bltu $a0, $a2, .LBB9_2
 ; LA64-NEXT:  # %bb.1: # %test
 ; LA64-NEXT:    ld.w $a0, $a1, 0
 ; LA64-NEXT:  .LBB9_2: # %end
 ; LA64-NEXT:    ret
   %val = load volatile i32, ptr %b
   %cc = icmp ugt i32 %val, %a
   br i1 %cc, label %end, label %test

 ; LA32-NEXT:    bgeu $a0, $a2, .LBB10_2
 ; LA32-NEXT:  # %bb.1: # %test
 ; LA32-NEXT:    ld.w $a0, $a1, 0
 ; LA32-NEXT:  .LBB10_2: # %end
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: foo_br_ule:
 ; LA64:       # %bb.0:
-; LA64-NEXT:    ld.wu $a2, $a1, 0
-; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
+; LA64-NEXT:    ld.w $a2, $a1, 0
+; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    bgeu $a0, $a2, .LBB10_2
 ; LA64-NEXT:  # %bb.1: # %test
 ; LA64-NEXT:    ld.w $a0, $a1, 0
 ; LA64-NEXT:  .LBB10_2: # %end
 ; LA64-NEXT:    ret
   %val = load volatile i32, ptr %b
   %cc = icmp ule i32 %val, %a
   br i1 %cc, label %end, label %test

llvm/test/CodeGen/LoongArch/jump-table.ll

 ; LA32-NEXT:    ret
 ; LA32-NEXT:  .LBB0_8: # %bb3
 ; LA32-NEXT:    st.w $a2, $a1, 0
 ; LA32-NEXT:  .LBB0_9: # %exit
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: switch_4_arms:
 ; LA64:       # %bb.0: # %entry
-; LA64-NEXT:    bstrpick.d $a0, $a0, 31, 0
+; LA64-NEXT:    addi.w $a0, $a0, 0
 ; LA64-NEXT:    ori $a2, $zero, 2
 ; LA64-NEXT:    blt $a2, $a0, .LBB0_4
 ; LA64-NEXT:  # %bb.1: # %entry
 ; LA64-NEXT:    ori $a3, $zero, 1
 ; LA64-NEXT:    beq $a0, $a3, .LBB0_7
 ; LA64-NEXT:  # %bb.2: # %entry
 ; LA64-NEXT:    bne $a0, $a2, .LBB0_9
 ; LA64-NEXT:  # %bb.3: # %bb2

 ; LA32-JT-NEXT:    ori $a0, $zero, 1
 ; LA32-JT-NEXT:  .LBB0_5: # %exit
 ; LA32-JT-NEXT:    st.w $a0, $a1, 0
 ; LA32-JT-NEXT:  .LBB0_6: # %exit
 ; LA32-JT-NEXT:    ret
 ;
 ; LA64-JT-LABEL: switch_4_arms:
 ; LA64-JT:       # %bb.0: # %entry
-; LA64-JT-NEXT:    bstrpick.d $a0, $a0, 31, 0
+; LA64-JT-NEXT:    addi.w $a0, $a0, 0
 ; LA64-JT-NEXT:    addi.d $a2, $a0, -1
 ; LA64-JT-NEXT:    ori $a0, $zero, 3
 ; LA64-JT-NEXT:    bltu $a0, $a2, .LBB0_6
 ; LA64-JT-NEXT:  # %bb.1: # %entry
 ; LA64-JT-NEXT:    slli.d $a2, $a2, 3
 ; LA64-JT-NEXT:    pcalau12i $a3, %pc_hi20(.LJTI0_0)
 ; LA64-JT-NEXT:    addi.d $a3, $a3, %pc_lo12(.LJTI0_0)
 ; LA64-JT-NEXT:    ldx.d $a2, $a2, $a3

llvm/test/CodeGen/LoongArch/nomerge.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
 define void @foo(i32 %i) nounwind {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi.d $sp, $sp, -16
 ; CHECK-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
-; CHECK-NEXT:    bstrpick.d $a0, $a0, 31, 0
+; CHECK-NEXT:    addi.w $a0, $a0, 0
 ; CHECK-NEXT:    ori $a1, $zero, 7
 ; CHECK-NEXT:    beq $a0, $a1, .LBB0_3
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    ori $a1, $zero, 5
 ; CHECK-NEXT:    bne $a0, $a1, .LBB0_4
 ; CHECK-NEXT:  # %bb.2: # %if.then
 ; CHECK-NEXT:    bl %plt(bar)
 ; CHECK-NEXT:    b .LBB0_4

llvm/test/CodeGen/LoongArch/sext-cheaper-than-zext.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
 define signext i32 @sext_icmp(i32 signext %x, i32 signext %y) {
 ; CHECK-LABEL: sext_icmp:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    bstrpick.d $a1, $a1, 31, 0
-; CHECK-NEXT:    addi.d $a0, $a0, 1
-; CHECK-NEXT:    bstrpick.d $a0, $a0, 31, 0
+; CHECK-NEXT:    addi.w $a0, $a0, 1
 ; CHECK-NEXT:    xor $a0, $a0, $a1
 ; CHECK-NEXT:    sltu $a0, $zero, $a0
 ; CHECK-NEXT:    ret
   %1 = add nsw i32 %x, 1
   %2 = icmp ne i32 %1, %y
   %3 = zext i1 %2 to i32
   ret i32 %3
 }

llvm/test/CodeGen/LoongArch/shrinkwrap.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 -O0 < %s | FileCheck %s --check-prefix=NOSHRINKW
 ; RUN: llc --mtriple=loongarch64 -O2 < %s | FileCheck %s --check-prefix=SHRINKW
 
 declare void @abort()
 
 define void @eliminate_restore(i32 %n) nounwind {
 ; NOSHRINKW-LABEL: eliminate_restore:
 ; NOSHRINKW:       # %bb.0:
 ; NOSHRINKW-NEXT:    addi.d $sp, $sp, -16
 ; NOSHRINKW-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; NOSHRINKW-NEXT:    # kill: def $r5 killed $r4
-; NOSHRINKW-NEXT:    bstrpick.d $a1, $a0, 31, 0
+; NOSHRINKW-NEXT:    addi.w $a1, $a0, 0
 ; NOSHRINKW-NEXT:    ori $a0, $zero, 32
 ; NOSHRINKW-NEXT:    bltu $a0, $a1, .LBB0_2
 ; NOSHRINKW-NEXT:    b .LBB0_1
 ; NOSHRINKW-NEXT:  .LBB0_1: # %if.then
 ; NOSHRINKW-NEXT:    bl %plt(abort)
 ; NOSHRINKW-NEXT:  .LBB0_2: # %if.end
 ; NOSHRINKW-NEXT:    ld.d $ra, $sp, 8 # 8-byte Folded Reload
 ; NOSHRINKW-NEXT:    addi.d $sp, $sp, 16
 ; NOSHRINKW-NEXT:    ret
 ;
 ; SHRINKW-LABEL: eliminate_restore:
 ; SHRINKW:       # %bb.0:
-; SHRINKW-NEXT:    bstrpick.d $a0, $a0, 31, 0
+; SHRINKW-NEXT:    addi.w $a0, $a0, 0
 ; SHRINKW-NEXT:    ori $a1, $zero, 32
 ; SHRINKW-NEXT:    bgeu $a1, $a0, .LBB0_2
 ; SHRINKW-NEXT:  # %bb.1: # %if.end
 ; SHRINKW-NEXT:    ret
 ; SHRINKW-NEXT:  .LBB0_2: # %if.then
 ; SHRINKW-NEXT:    addi.d $sp, $sp, -16
 ; SHRINKW-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; SHRINKW-NEXT:    bl %plt(abort)

 ; NOSHRINKW-LABEL: conditional_alloca:
 ; NOSHRINKW:       # %bb.0:
 ; NOSHRINKW-NEXT:    addi.d $sp, $sp, -32
 ; NOSHRINKW-NEXT:    st.d $ra, $sp, 24 # 8-byte Folded Spill
 ; NOSHRINKW-NEXT:    st.d $fp, $sp, 16 # 8-byte Folded Spill
 ; NOSHRINKW-NEXT:    addi.d $fp, $sp, 32
 ; NOSHRINKW-NEXT:    move $a1, $a0
 ; NOSHRINKW-NEXT:    st.d $a1, $fp, -24 # 8-byte Folded Spill
-; NOSHRINKW-NEXT:    bstrpick.d $a1, $a0, 31, 0
+; NOSHRINKW-NEXT:    addi.w $a1, $a0, 0
 ; NOSHRINKW-NEXT:    ori $a0, $zero, 32
 ; NOSHRINKW-NEXT:    bltu $a0, $a1, .LBB1_2
 ; NOSHRINKW-NEXT:    b .LBB1_1
 ; NOSHRINKW-NEXT:  .LBB1_1: # %if.then
 ; NOSHRINKW-NEXT:    ld.d $a0, $fp, -24 # 8-byte Folded Reload
 ; NOSHRINKW-NEXT:    bstrpick.d $a0, $a0, 31, 0
 ; NOSHRINKW-NEXT:    addi.d $a0, $a0, 15
 ; NOSHRINKW-NEXT:    bstrpick.d $a0, $a0, 32, 4
 ; NOSHRINKW-NEXT:    slli.d $a1, $a0, 4
 ; NOSHRINKW-NEXT:    move $a0, $sp
 ; NOSHRINKW-NEXT:    sub.d $a0, $a0, $a1
 ; NOSHRINKW-NEXT:    move $sp, $a0
 ; NOSHRINKW-NEXT:    bl %plt(notdead)
 ; NOSHRINKW-NEXT:    b .LBB1_2
 ; NOSHRINKW-NEXT:  .LBB1_2: # %if.end
 ; NOSHRINKW-NEXT:    addi.d $sp, $fp, -32
 ; NOSHRINKW-NEXT:    ld.d $fp, $sp, 16 # 8-byte Folded Reload
 ; NOSHRINKW-NEXT:    ld.d $ra, $sp, 24 # 8-byte Folded Reload
 ; NOSHRINKW-NEXT:    addi.d $sp, $sp, 32
 ; NOSHRINKW-NEXT:    ret
 ;
 ; SHRINKW-LABEL: conditional_alloca:
 ; SHRINKW:       # %bb.0:
-; SHRINKW-NEXT:    bstrpick.d $a0, $a0, 31, 0
-; SHRINKW-NEXT:    ori $a1, $zero, 32
-; SHRINKW-NEXT:    bltu $a1, $a0, .LBB1_2
+; SHRINKW-NEXT:    addi.w $a1, $a0, 0
+; SHRINKW-NEXT:    ori $a2, $zero, 32
+; SHRINKW-NEXT:    bltu $a2, $a1, .LBB1_2
 ; SHRINKW-NEXT:  # %bb.1: # %if.then
 ; SHRINKW-NEXT:    addi.d $sp, $sp, -16
 ; SHRINKW-NEXT:    st.d $ra, $sp, 8 # 8-byte Folded Spill
 ; SHRINKW-NEXT:    st.d $fp, $sp, 0 # 8-byte Folded Spill
 ; SHRINKW-NEXT:    addi.d $fp, $sp, 16
+; SHRINKW-NEXT:    bstrpick.d $a0, $a0, 31, 0
 ; SHRINKW-NEXT:    addi.d $a0, $a0, 15
 ; SHRINKW-NEXT:    bstrpick.d $a0, $a0, 32, 4
 ; SHRINKW-NEXT:    slli.d $a0, $a0, 4
 ; SHRINKW-NEXT:    sub.d $a0, $sp, $a0
 ; SHRINKW-NEXT:    move $sp, $a0
 ; SHRINKW-NEXT:    bl %plt(notdead)
 ; SHRINKW-NEXT:    addi.d $sp, $fp, -16
 ; SHRINKW-NEXT:    ld.d $fp, $sp, 0 # 8-byte Folded Reload

llvm/test/CodeGen/LoongArch/spill-ra-without-kill.ll

 ; CHECK-NEXT:    .cfi_offset 1, -8
 ; CHECK-NEXT:    .cfi_offset 22, -16
 ; CHECK-NEXT:    addi.d $fp, $sp, 48
 ; CHECK-NEXT:    .cfi_def_cfa 22, 0
 ; CHECK-NEXT:    st.d $ra, $fp, -40 # 8-byte Folded Spill
 ; CHECK-NEXT:    move $a1, $a0
 ; CHECK-NEXT:    pcalau12i $a0, %pc_hi20(calls)
 ; CHECK-NEXT:    addi.d $a3, $a0, %pc_lo12(calls)
-; CHECK-NEXT:    ld.wu $a0, $a3, 0
+; CHECK-NEXT:    ld.w $a0, $a3, 0
 ; CHECK-NEXT:    addi.d $a2, $a0, 1
 ; CHECK-NEXT:    st.w $a2, $a3, 0
 ; CHECK-NEXT:    st.w $a1, $fp, -28
 ; CHECK-NEXT:    bnez $a0, .LBB0_2
 ; CHECK-NEXT:    b .LBB0_1
 ; CHECK-NEXT:  .LBB0_1: # %if.then
 ; CHECK-NEXT:    ld.d $a0, $fp, -40 # 8-byte Folded Reload
 ; CHECK-NEXT:    st.d $a0, $fp, -24
 ; CHECK-NEXT:    b .LBB0_7
 ; CHECK-NEXT:  .LBB0_2: # %if.end
-; CHECK-NEXT:    ld.wu $a0, $fp, -28
+; CHECK-NEXT:    ld.w $a0, $fp, -28
 ; CHECK-NEXT:    st.d $a0, $fp, -48 # 8-byte Folded Spill
 ; CHECK-NEXT:    beqz $a0, .LBB0_5
 ; CHECK-NEXT:    b .LBB0_3
 ; CHECK-NEXT:  .LBB0_3: # %if.end
 ; CHECK-NEXT:    ld.d $a0, $fp, -48 # 8-byte Folded Reload
 ; CHECK-NEXT:    ori $a1, $zero, 1
 ; CHECK-NEXT:    bne $a0, $a1, .LBB0_6
 ; CHECK-NEXT:    b .LBB0_4

llvm/test/CodeGen/LoongArch/tail-calls.ll

 }
 
 ;; Perform indirect tail call optimization (for function pointer call).
 declare void @callee_indirect1()
 declare void @callee_indirect2()
 define void @caller_indirect_tail(i32 %a) nounwind {
 ; CHECK-LABEL: caller_indirect_tail:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    bstrpick.d $a0, $a0, 31, 0
+; CHECK-NEXT:    addi.w $a0, $a0, 0
 ; CHECK-NEXT:    sltui $a0, $a0, 1
 ; CHECK-NEXT:    pcalau12i $a1, %got_pc_hi20(callee_indirect2)
 ; CHECK-NEXT:    ld.d $a1, $a1, %got_pc_lo12(callee_indirect2)
 ; CHECK-NEXT:    masknez $a1, $a1, $a0
 ; CHECK-NEXT:    pcalau12i $a2, %got_pc_hi20(callee_indirect1)
 ; CHECK-NEXT:    ld.d $a2, $a2, %got_pc_lo12(callee_indirect1)
 ; CHECK-NEXT:    maskeqz $a0, $a2, $a0
 ; CHECK-NEXT:    or $a0, $a0, $a1