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[LoongArch] Implement isZextFree
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Authored by hev on Jul 10 2023, 1:08 AM.

Details

Summary

This returns true for 8-bit and 16-bit loads, allowing ld.bu/ld.hu to be selected and avoiding unnecessary masks.

Signed-off-by: WANG Rui <wangrui@loongson.cn>

Depends on D154818

Diff Detail

Event Timeline

hev created this revision.Jul 10 2023, 1:08 AM
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hev requested review of this revision.Jul 10 2023, 1:08 AM
xen0n accepted this revision.Jul 10 2023, 6:14 AM
This revision is now accepted and ready to land.Jul 10 2023, 6:14 AM
SixWeining accepted this revision.Jul 10 2023, 8:08 AM
SixWeining added inline comments.Jul 10 2023, 7:26 PM
llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
3256

I'm not sure why we cannot do this. But seems that RISCV is the same.

llvm/test/CodeGen/LoongArch/zext-with-load-is-free.ll
7

Do you mind switching to a simpler program:

define zeroext i8 @test_zext_i8(ptr %p) nounwind {
  %a = load i8, ptr %p, align 1
  br label %exit
exit:
  ret i8 %a
}
hev added inline comments.Jul 10 2023, 10:54 PM
llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
3256

There is no register width in LoongArch's instruction encoding, and the results of most 32-bit (W) instructions are sign-extended to 64-bit registers. Zero-extended values have additional overhead as input to the W instruction.

hev updated this revision to Diff 539458.Jul 12 2023, 3:02 AM

Rebase.

hev marked an inline comment as done.Jul 12 2023, 3:02 AM

Thanks.

This revision was landed with ongoing or failed builds.Jul 24 2023, 2:50 AM
Closed by commit rG9c21f9554114: [LoongArch] Implement isZextFree (authored by hev, committed by SixWeining). · Explain Why
This revision was automatically updated to reflect the committed changes.