[LoongArch] Implement isZextFree

[hev]

Summary

This returns true for 8-bit and 16-bit loads, allowing ld.bu/ld.hu to be selected and avoiding unnecessary masks.

Signed-off-by: WANG Rui <[e-mail]>

Depends on D154818

[SixWeining]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

3256

I'm not sure why we cannot do this. But seems that RISCV is the same.

llvm/test/CodeGen/LoongArch/zext-with-load-is-free.ll

10

Do you mind switching to a simpler program:

define zeroext i8 @test_zext_i8(ptr %p) nounwind {
  %a = load i8, ptr %p, align 1
  br label %exit
exit:
  ret i8 %a
}

[hev]

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

3256

There is no register width in LoongArch's instruction encoding, and the results of most 32-bit (W) instructions are sign-extended to 64-bit registers. Zero-extended values have additional overhead as input to the W instruction.

[hev]

Rebase.

[hev]

Thanks.

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

public:
   bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
 
   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
                              unsigned AS,
                              Instruction *I = nullptr) const override;
 
   bool isLegalICmpImmediate(int64_t Imm) const override;
   bool isLegalAddImmediate(int64_t Imm) const override;
+  bool isZExtFree(SDValue Val, EVT VT2) const override;
 
   bool hasAndNotCompare(SDValue Y) const override;
 
   bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
 
   bool allowsMisalignedMemoryAccesses(
       EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
       MachineMemOperand::Flags Flags = MachineMemOperand::MONone,

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

 bool LoongArchTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
   return isInt<12>(Imm);
 }
 
 bool LoongArchTargetLowering::isLegalAddImmediate(int64_t Imm) const {
   return isInt<12>(Imm);
 }
 
+bool LoongArchTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
+  // Zexts are free if they can be combined with a load.
+  // Don't advertise i32->i64 zextload as being free for LA64. It interacts
+  // poorly with type legalization of compares preferring sext.
+  if (auto *LD = dyn_cast<LoadSDNode>(Val)) {
+    EVT MemVT = LD->getMemoryVT();
+    if ((MemVT == MVT::i8 || MemVT == MVT::i16) &&
+        (LD->getExtensionType() == ISD::NON_EXTLOAD ||
+         LD->getExtensionType() == ISD::ZEXTLOAD))
+      return true;
+  }
+
+  return TargetLowering::isZExtFree(Val, VT2);
+}
+
 bool LoongArchTargetLowering::hasAndNotCompare(SDValue Y) const {
   // TODO: Support vectors.
   if (Y.getValueType().isVector())
     return false;
 
   return !isa<ConstantSDNode>(Y);
 }

llvm/test/CodeGen/LoongArch/zext-with-load-is-free.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
 ;; Adapted from the RISCV test case.
 ; RUN: llc --mtriple=loongarch32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefix=LA32
 ; RUN: llc --mtriple=loongarch64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefix=LA64
 
 @bytes = dso_local global [5 x i8] zeroinitializer, align 1
 
 define dso_local i32 @test_zext_i8() nounwind {
 ; LA32-LABEL: test_zext_i8:
 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    pcalau12i $a0, %pc_hi20(bytes)
 ; LA32-NEXT:    addi.w $a0, $a0, %pc_lo12(bytes)
 ; LA32-NEXT:    ld.bu $a1, $a0, 0
 ; LA32-NEXT:    ori $a2, $zero, 136
 ; LA32-NEXT:    bne $a1, $a2, .LBB0_3
 ; LA32-NEXT:  # %bb.1: # %entry
-; LA32-NEXT:    ld.b $a0, $a0, 1
-; LA32-NEXT:    andi $a0, $a0, 255
+; LA32-NEXT:    ld.bu $a0, $a0, 1
 ; LA32-NEXT:    ori $a1, $zero, 7
 ; LA32-NEXT:    bne $a0, $a1, .LBB0_3
 ; LA32-NEXT:  # %bb.2: # %if.end
 ; LA32-NEXT:    move $a0, $zero
 ; LA32-NEXT:    ret
 ; LA32-NEXT:  .LBB0_3: # %if.then
 ; LA32-NEXT:    ori $a0, $zero, 1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_zext_i8:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    pcalau12i $a0, %pc_hi20(bytes)
 ; LA64-NEXT:    addi.d $a0, $a0, %pc_lo12(bytes)
 ; LA64-NEXT:    ld.bu $a1, $a0, 0
 ; LA64-NEXT:    ori $a2, $zero, 136
 ; LA64-NEXT:    bne $a1, $a2, .LBB0_3
 ; LA64-NEXT:  # %bb.1: # %entry
-; LA64-NEXT:    ld.b $a0, $a0, 1
-; LA64-NEXT:    andi $a0, $a0, 255
+; LA64-NEXT:    ld.bu $a0, $a0, 1
 ; LA64-NEXT:    ori $a1, $zero, 7
 ; LA64-NEXT:    bne $a0, $a1, .LBB0_3
 ; LA64-NEXT:  # %bb.2: # %if.end
 ; LA64-NEXT:    move $a0, $zero
 ; LA64-NEXT:    ret
 ; LA64-NEXT:  .LBB0_3: # %if.then
 ; LA64-NEXT:    ori $a0, $zero, 1
 ; LA64-NEXT:    ret

 ; LA32:       # %bb.0: # %entry
 ; LA32-NEXT:    pcalau12i $a0, %pc_hi20(shorts)
 ; LA32-NEXT:    addi.w $a0, $a0, %pc_lo12(shorts)
 ; LA32-NEXT:    lu12i.w $a1, 15
 ; LA32-NEXT:    ori $a1, $a1, 3976
 ; LA32-NEXT:    ld.hu $a2, $a0, 0
 ; LA32-NEXT:    bne $a2, $a1, .LBB1_3
 ; LA32-NEXT:  # %bb.1: # %entry
-; LA32-NEXT:    ld.h $a0, $a0, 2
-; LA32-NEXT:    bstrpick.w $a0, $a0, 15, 0
+; LA32-NEXT:    ld.hu $a0, $a0, 2
 ; LA32-NEXT:    ori $a1, $zero, 7
 ; LA32-NEXT:    bne $a0, $a1, .LBB1_3
 ; LA32-NEXT:  # %bb.2: # %if.end
 ; LA32-NEXT:    move $a0, $zero
 ; LA32-NEXT:    ret
 ; LA32-NEXT:  .LBB1_3: # %if.then
 ; LA32-NEXT:    ori $a0, $zero, 1
 ; LA32-NEXT:    ret
 ;
 ; LA64-LABEL: test_zext_i16:
 ; LA64:       # %bb.0: # %entry
 ; LA64-NEXT:    pcalau12i $a0, %pc_hi20(shorts)
 ; LA64-NEXT:    addi.d $a0, $a0, %pc_lo12(shorts)
 ; LA64-NEXT:    lu12i.w $a1, 15
 ; LA64-NEXT:    ori $a1, $a1, 3976
 ; LA64-NEXT:    ld.hu $a2, $a0, 0
 ; LA64-NEXT:    bne $a2, $a1, .LBB1_3
 ; LA64-NEXT:  # %bb.1: # %entry
-; LA64-NEXT:    ld.h $a0, $a0, 2
-; LA64-NEXT:    bstrpick.d $a0, $a0, 15, 0
+; LA64-NEXT:    ld.hu $a0, $a0, 2
 ; LA64-NEXT:    ori $a1, $zero, 7
 ; LA64-NEXT:    bne $a0, $a1, .LBB1_3
 ; LA64-NEXT:  # %bb.2: # %if.end
 ; LA64-NEXT:    move $a0, $zero
 ; LA64-NEXT:    ret
 ; LA64-NEXT:  .LBB1_3: # %if.then
 ; LA64-NEXT:    ori $a0, $zero, 1
 ; LA64-NEXT:    ret