[LoongArch] Implement isLegalICmpImmediate

[hev]

Summary

This brings a trivial improvement in the legalicmpimm.ll test case.

Signed-off-by: WANG Rui <[e-mail]>

[hev]

Rebase.

[SixWeining]

llvm/test/CodeGen/LoongArch/legalicmpimm.ll

16

Seems this line is useless to demonstrate the diff?

llvm/lib/Target/LoongArch/LoongArchISelLowering.h

bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
                               SDValue C) const override;
 
   bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
 
   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
                              unsigned AS,
                              Instruction *I = nullptr) const override;
 
+  bool isLegalICmpImmediate(int64_t Imm) const override;
   bool isLegalAddImmediate(int64_t Imm) const override;
 
   bool hasAndNotCompare(SDValue Y) const override;
 
   bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
 
   bool allowsMisalignedMemoryAccesses(
       EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

case 2:
     break;
   default:
     return false;
   }
 
   return true;
 }
 
+bool LoongArchTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
+  return isInt<12>(Imm);
+}
+
 bool LoongArchTargetLowering::isLegalAddImmediate(int64_t Imm) const {
   return isInt<12>(Imm);
 }
 
 bool LoongArchTargetLowering::hasAndNotCompare(SDValue Y) const {
   // TODO: Support vectors.
   if (Y.getValueType().isVector())
     return false;
 
   return !isa<ConstantSDNode>(Y);
 }

llvm/test/CodeGen/LoongArch/legalicmpimm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
 define i32 @icmpimm(i32 %x) {
 ; CHECK-LABEL: icmpimm:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lu12i.w $a1, -1
-; CHECK-NEXT:    lu32i.d $a1, 0
-; CHECK-NEXT:    and $a0, $a0, $a1
-; CHECK-NEXT:    lu12i.w $a1, 1
-; CHECK-NEXT:    xor $a0, $a0, $a1
+; CHECK-NEXT:    bstrpick.d $a0, $a0, 31, 12
+; CHECK-NEXT:    addi.d $a0, $a0, -1
 ; CHECK-NEXT:    sltui $a0, $a0, 1
 ; CHECK-NEXT:    ret
   %1 = and i32 %x, -4096
   %2 = icmp eq i32 %1, 4096
   %3 = zext i1 %2 to i32
   ret i32 %3
 }